PCF8534H [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCF8534H |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总40页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCF8534
Universal LCD driver for low multiplex rates
Rev. 00.05 — 20 February 2007
Preliminary datasheet
1. General description
The PCF8534 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 60 segments and can easily be cascaded
for larger LCD applications. The PCF8534 is compatible with most
microprocessors / microcontrollers and communicates via a two-line bidirectional I2C-bus.
Communication overheads are minimized using a display RAM with auto-incremented
addressing, hardware subaddressing and display memory switching (static and duplex
drive modes).
2. Features
Single-chip LCD controller / driver
Selectable backplane drive
configuration: static or 2 / 3 / 4
backplane multiplexing
Selectable display bias configuration:
static, 1⁄2 or 1⁄3
Internal LCD bias generation with
voltage-follower buffers
60 segment drives: up to thirty
8-segment numeric characters; up to
sixteen 15-segment alphanumeric
characters; or any graphics of up to
240 elements
60 x 4-bit RAM for display data storage
Auto-incremented display data loading Display memory bank switching in static
across device subaddress boundaries
and duplex drive modes
Versatile blinking modes
LCD and logic supplies may be
separated
Wide power supply range: from
Wide LCD supply range: from 2.5 V for
low threshold LCDs and up to 6.5 V for
guest-host LCDs and high threshold
(automobile) twisted nematic LCDs
1.8 to 5.5 V
Low power consumption
TTL/CMOS compatible
400 kHz I2C-bus interface
Compatible with 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
May be cascaded for 2 LCD applications No external components
Manufactured in silicon gate CMOS
process.
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number Topside
mark
Package
Name
Description
Version
PCF8534H
PCF8534H LQFP80 plastic, low profile, quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
2 of 40
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4. Block diagram
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Fig 1. PCF8534 block diagram
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
5. Pinning information
5.1 Pinning
60
59
58
57
56
S10
S9
S8
S7
S6
1
2
3
4
5
6
7
8
9
S31
S32
S33
S34
S35
S36
S37
S38
S39
55 S5
54 S4
53 S3
52 S2
51 S1
S40 10
S41 11
S42 12
S43 13
S44 14
S45 15
S46 16
PCF8534
50 S0
49 VLCD
48 VSS
47 SA0
46 A2
45 A1
44 A0
17
18
19
20
S47
S48
S49
S50
43 OSC
42 SYNC
41 VDD
MDB073v02
Fig 2. PCF8534 pin configuration
Table 2.
Pin allocation table
Pin
1
Symbol
S31
Pin
41
42
43
44
45
46
47
48
49
Symbol
VDD
2
S32
SYNC
OSC
A0
3
S33
4
S34
5
S35
A1
6
S36
A2
7
S37
SA0
VSS
8
S38
9
S39
VLCD
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
4 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 2.
Pin allocation table …continued
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
BP0
BP1
BP2
BP3
n.c.
Pin
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
n.c.
n.c.
n.c.
SDA
SCL
CLK
5.2 Pin description
Table 3.
Symbol
SDA
Pin description
Pin
38
39
40
41
42
Description
I2C-bus serial data input / output
I2C-bus serial clock input
SCL
CLK
external clock input / output
supply voltage
VDD
SYNC
cascade synchronization input / output
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
5 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 3.
Pin description
Symbol
Pin
Description
OSC
43
internal oscillator enable input
A0, A1 and A2
44 to 46
47
subaddress inputs
SA0
I2C-bus slave address input: [0]
logic ground
VSS
48
VLCD
49
LCD supply voltage
LCD backplane outputs
LCD segment outputs
BP0, BP1, BP2 and BP3
S0 to S59
30 to 33
50 to 80
and 1 to 29
6. Functional description
The PCF8534 is a versatile peripheral device designed to interface any
microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up to 60 segments.
The display configurations possible with the PCF8534 depend on the number of active
backplane outputs required; a selection of display configurations is given in Table 4.
All of the display configurations given in Table 4 can be implemented in the typical system
shown in Figure 3.
The host microprocessor / microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8534. The internal oscillator is selected by connecting pad OSC
to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required to complete the system are the
power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.
Table 4.
Selection of display configurations
7 segment numeric
Number of
14 segment numeric
Dot matrix
Backplanes
Segments
Digits
Indicator
Characters
Indicator
symbols
symbols
4
3
2
1
240
180
120
60
30
22
15
7
30
26
15
11
16
12
8
16
12
8
240 (4 x 60)
180 (3 x 60)
120 (2 x 60)
60 (1 x 60)
4
4
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
6 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
DD
t
r
R
2C
B
V
V
DD
LCD
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
60 segment drives
4 backplanes
LCD PANEL
PCF8534
(up to 240
elements)
OSC
A0 A1 A2 SA0
V
SS
MGL744v02
V
SS
Fig 3. Typical system configuration
6.1 Power-on-reset
At power on the PCF8534 resets to a starting condition as follows:
1. All backplane outputs are set to VLCD
2. All segment outputs are set to VLCD
.
.
3. The drive mode ‘1 : 4 multiplex with 1⁄3 bias’ is selected.
4. Blinking is switched off.
5. Input and output bank selectors are reset (as defined in Table 7 old datasheet).
6. The I2C-bus interface is initialized.
7. The data pointer and the subaddress counter are cleared.
8. Display disabled.
You must avoid data transfers on the I2C-bus for 1 ms following power on to allow the
reset action to complete.
6.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three
series resistors connected between VLCD and VSS. The centre resistor can be switched
out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex configuration.
6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
MODE SET commands from the command decoder.
The biasing configurations that apply to the preferred modes of operation, together with
the biasing characteristics as functions of VOP and the resulting discrimination ratios (D),
are shown in Table 5.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
7 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
A practical value for VOP is determined by equating VOFF(rms) with a defined LCD threshold
voltage (VTH), typically when the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is VOP > 3VTH
.
Multiplex drive ratios of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller e.g.:
21
3
⎛
⎝
⎞
---------
3 = 1.732 for 1:3 multiplex or
= 1.528 for 1:4 multiplex
⎠
The advantage of these modes is a reduction of the LCD full-scale voltage VOP as follows:
• 1:3 multiplex (1⁄2 bias): VOP
=
6 × VOFF(rms) = 2.449VOFF(rms)
(4 × 3)
• 1:4 multiplex (1⁄2 bias): VOP
=
= 2.309VOFF(rms)
--------------------
3
These compare with VOP = 3 x VOFF(rms) when 1⁄3 bias is used. Note: VOP = VLCD
.
Table 5.
Preferred LCD drive modes: summary of characteristics
LCD drive
mode
Number of:
LCD bias
configuration
VON(ms)
-------------------
VOP
VON(ms)
----------------------
VOFF(ms)
VOFF(ms)
----------------------
VOP
D =
Backplanes
Levels
static
1:2
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
⁄
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
2
1
1:2
⁄
3
1
1:3
⁄
3
1
1:4
⁄
3
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
8 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.4 LCD drive mode waveforms
6.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure 4.
T
frame
LCD segments
V
LCD
BP0
V
SS
state 1
(on)
state 2
(off)
V
LCD
S
n
V
SS
V
LCD
S
n+1
V
SS
(a) Waveforms at driver.
V
LCD
state 1
0 V
−V
LCD
V
LCD
state 2
0 V
−V
LCD
(b) Resultant waveforms
at LCD segment.
mgl745
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = VLCD
Vstate2(t) = V(sn + 1)(t) − VBP0(t).
OFF(rms) = 0 V.
.
V
Fig 4. Static drive mode waveforms
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
9 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8534 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 5 and
Figure 6.
T
frame
V
LCD
LCD segments
V
/2
BP0
BP1
LCD
V
V
SS
state 1
V
LCD
state 2
/2
LCD
SS
V
V
LCD
S
n
V
SS
V
LCD
S
n+1
V
V
SS
(a) Waveforms at driver.
V
LCD
/2
LCD
0 V
state 1
−V
/2
LCD
−V
LCD
V
LCD
V
/2
LCD
0 V
state 2
−V
−V
/2
LCD
LCD
(b) Resultant waveforms
at LCD segment.
mgl746
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.791 VLCD
Vstate2(t) = V(sn)(t) − VBP1(t).
OFF(rms) = 0.354 VLCD
.
V
.
Fig 5. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
10 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
T
frame
V
LCD
2V
LCD segments
/3
LCD
/3
BP0
BP1
V
LCD
V
SS
state 1
V
LCD
2V
state 2
/3
LCD
/3
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
S
n
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
S
n+1
V
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 1
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
−V
state 2
/3
LCD
−2V
−V
/3
LCD
LCD
(b) Resultant waveforms
at LCD segment.
mgl747
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.745 VLCD
state2(t) = V(sn)(t) − VBP1(t).
VOFF(rms) = 0.333 VLCD
.
V
.
Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
11 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 7.
T
frame
V
LCD
2V
LCD segments
/3
LCD
/3
BP0
BP1
BP2
V
LCD
V
SS
state 1
state 2
V
LCD
2V
/3
LCD
/3
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
S
n
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
S
n+1
S
n+2
V
LCD
V
SS
V
LCD
2V
/3
LCD
/3
V
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
/3
V
LCD
0 V
−V
state 1
/3
LCD
−2V
LCD
/3
LCD
−V
V
LCD
2V
/3
LCD
/3
V
LCD
0 V
−V
state 2
/3
LCD
−2V /3
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
mgl748
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.638 VLCD
Vstate2(t) = V(sn)(t) − VBP1(t).
OFF(rms) = 0.333 VLCD
.
V
.
Fig 7. Waveforms for the 1:3 multiplex drive mode.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
12 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 8.
T
frame
V
LCD segments
LCD
2V
/3
LCD
BP0
BP1
BP2
BP3
V
/3
LCD
V
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
LCD
/3
V
SS
V
LCD
2V
/3
LCD
/3
V
LCD
V
SS
V
LCD
2V
/3
LCD
V
LCD
/3
V
SS
V
LCD
2V
/3
LCD
/3
S
n
V
LCD
V
SS
V
LCD
2V
/3
LCD
S
n+1
V
LCD
/3
V
SS
V
LCD
2V
/3
LCD
S
S
n+2
n+3
V /3
LCD
V
SS
V
LCD
2V
/3
LCD
V /3
LCD
V
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
state 1
0 V
−V
/3
LCD
−2V
−V
/3
LCD
LCD
V
LCD
2V
/3
LCD
V /3
LCD
0 V
−V
state 2
/3
LCD
−2V /3
LCD
−V
LCD
(b) Resultant waveforms
at LCD segment.
mgl749
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.577 VLCD
state2(t) = V(sn)(t) − VBP1(t).
VOFF(rms) = 0.333 VLCD
.
V
.
Fig 8. Waveforms for the 1:4 multiplex drive mode.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
13 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.5 Oscillator
6.5.1 Internal clock
The internal logic and the LCD drive signals of the PCF8534 are timed either by the
built-in oscillator or from an external clock. When the internal oscillator is used, you must
connect pad OSC to VSS. In this event, the output from pad CLK provides the clock signal
for cascaded PCF8534’s in the system. After power-up, SDA must be HIGH to guarantee
that the clock starts.
6.5.2 External clock
The condition for external clock is made by tying pad OSC to VDD; pad CLK then becomes
the external clock input.
The clock frequency (fCLK) determines the LCD frame frequency.
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state.
6.6 Timing
The timing of the PCF8534 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8534’s in the system. The timing also generates the LCD
frame frequency which it derives as an integer division of the clock frequency
(see Table 6). The frame frequency is a fixed division of the internal clock or of the
frequency applied to pad CLK when an external clock is used.
6.7 Display register
The display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs and one column of the display RAM.
6.8 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data resident in the display latch. When less than
60 segment outputs are required the unused segment outputs must be left open-circuit.
6.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required the
unused outputs can be left open-circuit. In the 1:3 multiplex drive mode BP3 carries the
same signal as BP1, therefore these two adjacent outputs can be tied together to give
enhanced drive capabilities. In the 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3
respectively carry the same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is carried by all four backplane
outputs and they can be connected in parallel for very high drive requirements.
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
14 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
6.10 Display RAM
The display RAM is a static 60 x 4-bit RAM which stores LCD data. A logic 1 in the RAM
bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0
indicates the off-state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the individual bits of a RAM word and
the backplane outputs. The first RAM column corresponds to the 60 segments operated
with respect to backplane BP0 (see Figure 9). In multiplexed LCD applications the
segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8534 the display bytes received are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and does not wait for the acknowledge cycle as with the commands. Depending on
the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1:2
mux mode the RAM data is stored every second bit. To illustrate the filling order, an
example of a 7-segment numeric display showing all drive modes is given in Figure 10;
the RAM filling organization depicted applies equally to other LCD types. With reference
to Figure 10, in the static drive mode the eight transmitted data bits are placed in bit 0 of
eight successive display RAM addresses. In the 1:2 multiplex drive mode the eight
transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses.
In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three
successive addresses, with bit 2 of the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this address but care should be taken
to avoid overriding adjacent data because full bytes are always transmitted. In the 1:4
multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two
successive display RAM addresses.
Table 6.
LCD frame frequencies
Frame frequency
Nominal frame frequency (Hz)
fCLK
----------
24
64
DISPLAY 2!- ADDRESSES ꢊROWSꢋ ꢌ SEGMENT OUTPUTS ꢊ3ꢋ
ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ
U
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢁ
ꢂ
ꢃ
DISPLAY 2!- BITS
ꢊCOLUMNSꢋ ꢌ
BACKPLANE OUTPUTS
ꢊ"0ꢋ
-',ꢀꢅꢃVꢃꢄ
Fig 9. Display RAM bit map showing direct relationship between backplane outputs, display RAM addresses and
segment outputs, and between bits in a RAM word and backplane outputs.
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Universal LCD driver for low multiplex rates
6.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte
is stored starting at the display RAM address indicated by the data pointer thereby
observing the filling order shown in Figure 10. The data pointer is automatically
incremented in accordance with the chosen LCD configuration. That is, after each byte is
stored, the contents of the data pointer are incremented by eight (static drive mode), by
four (1:2 multiplex drive mode), by three (1:3 multiplex drive mode) or by two (1:4
multiplex drive mode). If an I2C-bus data access is terminated early then the state of the
data pointer is unknown. The data pointer must be re-written prior to further RAM
accesses.
6.12 Subaddress counter
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter agree
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the DEVICE SELECT command. If the contents of the subaddress counter and
the hardware subaddress do not agree then data storage is inhibited but the data pointer
is incremented as if data storage had taken place.
The subaddress counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8534 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 27th
display data byte transmitted in 1 : 3 multiplex mode).
The hardware subaddress should not be changed whilst the device is being accessed on
the I2C-bus interface.
6.13 Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer
to the display latch. The actual bit selected depends on the particular LCD drive mode in
operation and on the instant in the multiplex sequence. In 1:4 multiplex, all RAM
addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then
bit 3. Similarly in 1:3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1:2 multiplex,
bits 0 and 1 are selected and, in the static mode, bit 0 is selected.
The SYNC signal will reset these sequences to the following starting points; bit 3 for 1:4
multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode.
The PCF8534 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the BANK SELECT command may request the contents
of bit 2 to be selected for display instead of the contents of bit 0. In the 1:2 drive mode, the
contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision
for preparing display information in an alternative bank and to be able to switch to it once
it is assembled.
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Universal LCD driver for low multiplex rates
6.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode
or in bits 2 and 3 in 1:2 drive mode by using the BANK SELECT command. The input
bank selector functions independently to the output bank selector.
6.15 Blinker
The display blinking capabilities of the PCF8534 are very versatile. The whole display can
be blinked at frequencies selected by the BLINK command. The blinking frequencies are
integer multiples of the clock frequency. The ratios between the clock and blinking
frequencies depend on the mode in which the device is operating, see Table 7.
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 LCD drive modes and is implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blinking frequency. This mode can
also be specified by the BLINK command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display is to be blinked at a frequency other than the nominal blinking
frequency, this can be effectively performed by resetting and setting the display enable
bit E at the required rate using the MODE SET command.
Table 7.
Blinking frequencies
Blinking mode
Normal operating mode
ratio
Normal blinking frequency
Off
-
Blinking off
2 Hz
fCLK
----------
768
2 Hz
fCLK
-----------
1536
1 Hz
1 Hz
fCLK
-----------
3072
0.5 Hz
0.5 Hz
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drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
n+2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
b
BP0
f
S
n+3
S
n+1
MSB
LSB
DP
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
S
n+4
S
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
S
n+7
n+5
n+6
c
d
DP
S
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
n+1
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
multiplex
n+2
n+3
c
c
c
d
d
d
DP
BP0
BP1
S
n+1
a
n
n 2
S
S
n
f
1 : 3
n+2
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
n+1
DP
mgl751
X = data bit unchanged
Fig 10. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C bus.
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Application design-in information
7.1 Characteristics of the I2C bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer is initiated only when the bus is not busy.
7.2 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as a control signal. Bit transfer is
illustrated in Figure 11.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 11. Bit transfer
7.3 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 12.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 12. Definition of START and STOP conditions
7.4 System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’. The system configuration is illustrated in
Figure 13.
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Universal LCD driver for low multiplex rates
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Fig 13. System configuration
7.5 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge after the reception of each
byte. Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter. The device that acknowledges
must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master receiver must signal an end of data
to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is
illustrated in Figure 14.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 14. Acknowledgement of the I2C-bus
7.6 PCF8534 I2C-bus controller
The PCF8534 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8534 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
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Universal LCD driver for low multiplex rates
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such
that no two devices with a common I2C-bus slave address have the same hardware
subaddress.
7.7 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.8 I2C-bus protocol
Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8534.
The least significant bit of the slave address that a PCF8534 will respond to is defined by
the level tied at its input SA0. The PCF8534 is a write only device and will not respond to
a read access. Therefore, two types of PCF8534 can be distinguished on the same
I2C-bus which allows:
1. Up to 16 PCF8534’s on the same I2C-bus for very large LCD applications
2. The use of two types of LCD multiplex on the same I2C-bus.
The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two PCF8534 slave
addresses available. All PCF8534’s with the corresponding SA0 level acknowledge in
parallel to the slave address, but all PCF8534’s with the alternative SA0 level ignore the
whole I2C-bus transfer.
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte also defines if the next following byte is a control
byte or further RAM/command data.
In this way it is possible to configure the device then fill the display RAM with little
overhead.
The command bytes and control bytes are also acknowledged by all addressed
PCF8534’s connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated and the data is directed to the intended PCF8534 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8534. After the last display byte, the I2C-bus master issues a STOP condition (P).
Alternatively a START may be issued to RESTART an I2C-bus access.
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R/W = 0
slave address
control byte
A CoRS
0
RAM/command byte
S
A
0
M
S
B
L
S
B
S
0
1
1
1
0
0
P
A
EXAMPLES
a) transmit two bytes of RAM data
S
A
S
0
1
1
1
0
0
0
0
1
1
0
A
0
A
A
A
RAM DATA
COMMAND
COMMAND
A
A
A
RAM DATA
A
A
A
P
b) transmit two command bytes
S
A
S
0
1
1
1
0
0
0
0
0
0
1
A
0
COMMAND
RAM DATA
A
A
P
c) transmit one command byte and two RAM bytes
S
A
1 0
S
0
1
1
1
0
0
0
A
0
RAM DATA
A P
MGL752
Fig 15. I2C-bus protocol
MSB
Co RS
LSB
UNUSED
MGL753
(1) C0 = 0; last control byte
(2) C0 = 1; control bytes continue
(3) RS = 0; data is a command byte
(4) Rs = 1; data is a display byte
Fig 16. Control byte format
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.9 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The five
commands available to the PCF8534 are defined in Table 8.
Table 8.
Definition of PCF8534 commands
OPCODE
Command
Mode set
Options
Table 9
Description
1 1 0 0 E B M1 M0
defines LCD drive mode
defines LCD bias configuration
Table 10
Table 11
defines display status; the possibility to disable
the display allows implementation of blinking
under external control
Load data pointer
Device select
Bank select
0 P6 P5 P4 P3 P2 P1 P0
1 1 1 0 0 A2 A1 A0
1 1 1 1 1 0 I O
Table 12
Table 13
7 bits of immediate data, bits P6 to P0, are
transferred to the data pointer to define one of 8
hardware subaddresses
3 bits of immediate data, bits A0 to A3 are
transferred to the subaddress counter to define
one of 8 hardware subaddresses
Table 14
Table 15
defines input bank selection (storage of arriving
display data)
defines output bank selection (retrieval of LCD
display data); the BANK SELECT command has
no effect in 1:3 or 1:4 multiplex drive modes
Blink
1 1 1 1 0 A BF BF
1 0
Table 16
Table 17
defines the blinking frequency
selects the blinking mode; normal operation with
frequency set by BF1, BF0 or blinking by
alteration of display RAM banks. Alteration
blinking does not apply in 1:3 or 1:4 multiplex
drive modes.
Table 9.
Mode set option 1
LCD drive mode
Bits
Drive mode
Backplane
1 BP
M1
0
M0
1
static
1:2
MUX (2BP)
MUX (3BP)
MUX (4BP)
1
0
1:3
1
1
1:4
0
0
Table 10. Mode set option 2
LCD bias
1⁄3 bias
1⁄2 bias
Bit B
0
1
Table 11. Mode set option 3
Display status
Bit E
disabled (blank)
0
1
enabled
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Universal LCD driver for low multiplex rates
Table 12. Load data pointer option 1
Description
Bits
P6
7 bit ordinary value of 0 to 59
P5
P4
P3
P2
A1
P1
P0
Table 13. Device selected option 1
Description
Bits
A2
3 bit binary value of 0 to 7
A0
Table 14. Blank select option 1 (input)
Static
1:2 MUX
Bit I
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Table 15. Blank select option 2 (output)
Static
1:2 MUX
Bit O
RAM bit 0
RAM bit 2
RAM bits 0 and 1
RAM bits 2 and 3
0
1
Table 16. Blink option 1
Blink frequency
Bits
BF1
0
BF0
0
off
2 Hz
1 Hz
1.5 Hz
0
1
1
0
1
1
Table 17. Blink option 2
Blink mode
Bit A
[1]
normal blinking
0
1
alteration blinking
[1] Normal blinking is assumed when the multiplex rates 1:3 or 1:4 are selected.
7.10 Display controller
The display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8534 and co-ordinates their effects.
The controller is also responsible for loading display data into the display RAM as required
by the filling order.
7.11 Cascaded operation
In large display configurations, up to 16 PCF8534’s can be distinguished on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable
I2C-bus slave address (SA0). When cascaded PCF8534’s are synchronized they can
share the backplane signals from one of the devices in the cascade. Such an
arrangement is cost-effective in large LCD applications since the backplane outputs of
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Universal LCD driver for low multiplex rates
only one device need to be through-plated to the backplane electrodes of the display. The
other PCF8534’s of the cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Figure 17).
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8534’s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a multiplex mode when PCF8534’s
with different SA0 levels are cascaded). SYNC is organized as an input / output pad; the
output selection being realized as an open-drain driver with an internal pull-up resistor. A
PCF8534 asserts the SYNC line at the onset of its last active backplane signal and
monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is
restored by the first PCF8534 to assert SYNC. The timing relationship between the
backplane waveforms and the SYNC signal for the various drive modes of the PCF8534
are shown in Figure 18.
The contact resistance between the SYNC pads of cascaded devices must be controlled.
If the resistance is too high then the device will not be able to synchronize properly.
Table 18 shows the limiting values for contact resistance.
Table 18. SYNC contact resistance
Number of devices
Maximum contact resistance
2
6000 Ω
2200 Ω
1200 Ω
700 Ω
3 to 5
6 to 10
11 to 16
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
V
DD
LCD
SDA
SCL
60 segment drives
LCD PANEL
SYNC
CLK
PCF8534
OSC
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 V
SS
V
LCD
V
t
DD
r
R
2C
V
V
LCD
DD
B
SDA
SCL
HOST
MICRO-
PROCESSOR/
MICRO-
60 segment drives
SYNC
PCF8534
CONTROLLER
4 backplanes
BP0 to BP3
CLK
OSC
A0 A1 A2 SA0
V
V
SS
SS
MGL754v02
Fig 17. Cascaded PCF8534 configuration
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Preliminary datasheet
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
mgl755
(d) 1 : 4 multiplex drive mode.
Fig 18. Synchronization of the cascade for various PCF8534 drive modes
PCF8534_0
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Preliminary datasheet
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
8. Limiting values
Table 19. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Min
Max
Unit
V
supply voltage
−0.5
+6.5
IDD
supply current
−50
+50
mA
V
VLCD
ILCD
LCD supply voltage
LCD supply current
negative supply current
VSS − 0.5
−50
+7.5
+50
mA
mA
V
ISS
−50
+50
VI(n)
input voltage on pads SDA,
SCL, CLK, SYNC, SA0, OSC
and A0 to A2
VSS − 0.5
VDD + 0.5
VO(n)
output voltage on pads s= to
S59 and BP0 to BP3
VSS − 0.5
VLCD + 0.5
V
II
DC input current
−10
−10
-
+10
+10
400
100
+150
mA
mA
mW
mW
°C
IO
DC output current
PTOT
P / out
TSTG
total power dissipation
power dissipation per output
storage temperature
-
−65
8.1 ESD values
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 2000 V CDM per JESD22-C101.
• Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA.
9. Static characteristics
Table 20. Static characteristics
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = −40 to +85°C; unless otherwise specified
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
1.8
2.5
-
-
5.5
6.5
20
V
VLCD
IDD
LCD supply voltage
supply current
-
μA
μA
μA
[1]
[1]
fCLK = 1536 Hz
fCLK = 1536 Hz
8
24
ILCD
LCD supply current
-
60
Logic
VIL
Low-level input
voltage
VSS
-
-
-
0.3 VDD
V
VIH
High-level input
voltage
0.7 VDD
1
VDD
-
V
IOL1
Low-level output
current on pads CLK
and SYNC
VOL = 0.4 V; VDD = 5 V
mA
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 20. Static characteristics
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = −40 to +85°C; unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOH1
High-level output
current pad CLK
VOH = 4.6 V; VDD = 5 v
−1
-
-
mA
IOL2
IL1
Low-level output
current pad SDA
VOL = 0.4 V; VDD = 5 V
3
-
-
-
mA
leakage current pads V1 = VDD or VSS
SA0, A0 to A2, CLK,
−1
+1
μA
SDA and SCL
IL2
leakage current pad
OSC
V1 = VDD
−1
-
+1
μA
[2]
C1
input capacitance
-
-
7
pF
V
VPOR
power on reset
voltage level
1.0
1.3
1.6
LCD outputs
VBP
DC voltage
component on pads
BP0 to BP3
CBP = 35 nF
CS = 5 nF
−100
−100
-
-
+100
+100
mV
mV
VS
DC voltage
component on pads
S0 to S59
[3]
[3]
RBP
RS
output resistance at
pads BP0 to BP3
VLCD = 5 V
VLCD = 5 V
-
-
1.5
6.0
10
kΩ
kΩ
output resistance at
pads S0 to S59
13.5
[1] LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
[2] Not tested, design spec only.
[3] Outputs measured individually and sequentially.
10. Dynamic characteristics
Table 21. Dynamic characteristics
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = −40 to +85°C; unless otherwise specified
Symbol
Parameter
Conditions
Min
960
797
130
130
-
Typ
Max
Unit
[1]
fCLK(int)
fCLK(ext)
tCLKH
tCLKL
oscillator frequency on pad CLK (internal clock) VDD = 5 V
oscillator frequency on pad CLK (external clock) VDD = 5 V
input CLK HIGH time
1536
3046
Hz
Hz
μs
μs
ns
ns
ns
μs
μs
1536
3046
-
-
input CLK LOW time
-
-
tr
CLK rise time
-
-
tf
CLK fall time
-
-
-
td(p)SYNC
tSYNCL
td(PLCD)
SYNC propagation delay time
SYNC LOW time
-
30
-
-
1
-
driver delays with test loads
VLCD = 5 V
-
-
30
[2]
Timing characteristic: I2C bus
fSCL
tBUF
SCL clock frequency
-
-
-
400
-
kHz
bus free time between a stop and a start
1.3
μs
PCF8534_0
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Preliminary datasheet
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PCF8534
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Universal LCD driver for low multiplex rates
Table 21. Dynamic characteristics
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; TAMB = −40 to +85°C; unless otherwise specified
Symbol
tHD;STA
tSU;STA
tLOW
Parameter
Conditions
Min
0.6
0.6
1.3
0.6
-
Typ
Max
Unit
μs
μs
μs
μs
μs
μs
pF
ns
ns
μs
ns
start condition hold time
set-up time for a repeated start condition
SCL LOW time
-
-
-
-
-
-
-
-
tHIGH
tr
SCL HIGH time
-
SCL and SDA rise time
SCL and SDA fall time
capacitive bus line load
data set-up time
0.3
0.3
400
tf
-
Cb
-
-
tSU;DAT
tHD;DAT
tSU;STO
tSW
100
0
data hold time
-
-
-
-
set up time for stop condition
tolerable spike width on bus
0.6
-
-
50
[1] Typical output duty cycle of 50%.
[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
6.8 Ω
e
SYNC
CLK
V
DD
(2%)
3.3 kΩ
1.5 kΩ
SDA,
SCL
0.5V
V
DD
DD
(2%)
(2%)
1 nF
BP0 to BP3, and
S0 to S59
V
SS
MGS120v02
Fig 19. Test loads
PCF8534_0
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Preliminary datasheet
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
1/ f
CLK
t
t
CLKL
CLKH
0.7V
DD
CLK
0.3V
DD
t
t
r
f
0.7V
DD
SYNC
0.3V
DD
t
t
d(p)(SYNC)
d(p)(SYNC)
t
SYNCL
0.5 V
BP0 to BP3,
and S0 to S59
(V
= 5 V)
DD
0.5 V
t
MGL761v03
PLCD
Fig 20. Driver timing waveforms
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
t
t
SU;DAT
r
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Fig 21. I2C-bus timing waveforms
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
11. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
H
A
E
2
E
A
(A )
3
A
1
w
p
M
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v
M
A
e
w
M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
p
v
w
y
Z
Z
θ
1
2
3
p
E
D
E
max.
7o
0o
0.16 1.5
0.04 1.3
0.27 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.75
0.30
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT315-1
136E15
MS-026
Fig 22. Package outline LQFP80
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
32 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
12. Handling information
V
V
DD
DD
SA0
V
V
V
SS
SS
DD
CLK
OSC
SCL
V
V
SS
DD
V
SS
V
V
SS
SDA
DD
SYNC
V
V
V
SS
SS
DD
A0, A1 A2
V
V
SS
LCD
BP0, BP1,
BP2, BP3
V
V
SS
V
LCD
LCD
S0 to S59
V
V
SS
SS
MGL760v02
Fig 23. Device protection diagram
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
34 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 23. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
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PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
14. Revision history
Table 24. Revision history
Document ID
PCF8534_00.04
Modifications:
Release date
tbd
Data sheet status
Change notice
Supersedes
Preliminary
PCF8534_00.03
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 21: clock oscillator frequency (added external)
PCF8534_00.03
Modifications:
20060829
Objective
PCF8534_00.02
• Table 1:added column for ‘Topside mark’
• Section 8.1: added ESD values.
PCF8534_00.02
Modifications:
20060725
Objective
PCF8534_00.01
first release
• transfer to TDM format
20060628
PCF8534_00.01
Objective
PCF8534_0
© NXP B.V. 2007. All rights reserved.
Preliminary datasheet
Rev. 00.05 — 20 February 2007
37 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
15.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
38 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
Notes
PCF8534_0
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Preliminary datasheet
Rev. 00.05 — 20 February 2007
39 of 40
PCF8534
NXP Semiconductors
Universal LCD driver for low multiplex rates
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
12
Handling information . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Introduction to soldering. . . . . . . . . . . . . . . . . 34
Wave and reflow soldering. . . . . . . . . . . . . . . 34
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 34
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 35
13.1
13.2
13.3
13.4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . 37
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 38
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 38
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6
6.1
6.2
6.3
Functional description . . . . . . . . . . . . . . . . . . . 6
Power-on-reset. . . . . . . . . . . . . . . . . . . . . . . . . 7
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7
LCD drive mode waveforms . . . . . . . . . . . . . . . 9
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Display register. . . . . . . . . . . . . . . . . . . . . . . . 14
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Subaddress counter . . . . . . . . . . . . . . . . . . . . 16
Output bank selector . . . . . . . . . . . . . . . . . . . 16
Input bank selector . . . . . . . . . . . . . . . . . . . . . 17
Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.1
15.2
15.3
15.4
6.4
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 38
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.1
6.4.2
6.4.3
6.4.4
6.5
6.5.1
6.5.2
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
7
Application design-in information . . . . . . . . . 19
Characteristics of the I2C bus. . . . . . . . . . . . . 19
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
START and STOP conditions . . . . . . . . . . . . . 19
System configuration . . . . . . . . . . . . . . . . . . . 19
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCF8534 I2C-bus controller. . . . . . . . . . . . . . 20
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21
Command decoder . . . . . . . . . . . . . . . . . . . . . 23
Display controller . . . . . . . . . . . . . . . . . . . . . . 24
Cascaded operation . . . . . . . . . . . . . . . . . . . . 24
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
8.1
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28
ESD values. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Static characteristics. . . . . . . . . . . . . . . . . . . . 28
Dynamic characteristics . . . . . . . . . . . . . . . . . 29
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32
10
11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 February 2007
Document identifier: PCF8534_0
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