PHD78NQ03LT/T3_技术文档

PHD78NQ03LT

N-channel TrenchMOS logic level FET

Rev. 06 — 11 June 2009

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industrial applications only.

1.2 Features and benefits

Suitable for high frequency

applications due to fast switching

characteristics

Suitable for logic level gate drive

sources

1.3 Applications

Computer motherboards

DC-to-DC convertors

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 175 °C

Min

Typ

Max Unit

V_DS

I_D

-

25

75

V

A

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1; see Figure 3

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

-

107

-

W

Dynamic characteristics

Q_GDgate-drain charge

V_GS= 4.5 V; I_D= 25 A;

V_DS= 12 V; T_j= 25 °C;

see Figure 11; see Figure 12

4

nC

Static characteristics

R_DSon

drain-source

on-state resistance

V_GS= 10 V; I_D= 25 A;

T_j= 25 °C;

-

7.65

9

mΩ

see Figure 9; see Figure 10

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

1

Symbol Description

Simplified outline

Graphic symbol

G

D

S

D

gate

mb

D

2

drain

source

[1]

3

G

mb

mounting base; connected to

drain

mbb076

S

2

1

3

SOT428

(SC-63; DPAK)

[1] It is not possible to make a connection to pin 2.

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PHD78NQ03LT

SC-63;

DPAK

plastic single-ended surface-mounted package (DPAK); 3 leads (one

lead cropped)

SOT428

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

2 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

25

Unit

V

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

-

V_DGR

V_GS

R_GS= 20 kΩ; T_mb≥ 25 °C; T_mb≤ 175 °C

-

25

V

-20

20

V

I_D

V_GS= 5 V; T_mb= 100 °C

-

46.9

57.5

75

A

V_GS= 10 V; T_mb= 100 °C; see Figure 1

A

V_GS= 10 V; T_mb= 25 °C; see Figure 1;

see Figure 3

A

V_GS= 5 V; T_mb= 25 °C

-

66.4

240

107

175

A

I_DM

P_tot

T_stg

T_j

peak drain current

t_p≤ 10 µs; pulsed; T_mb= 25 °C; see Figure 3

-

A

total power dissipation T_mb= 25 °C; see Figure 2

storage temperature

-

W

°C

-55

junction temperature

Source-drain diode

I_S

source current

peak source current

T_mb= 25 °C

-

75

A

I_SM

t_p≤ 10 µs; pulsed; T_mb= 25 °C

240

Avalanches ruggedness

E_DS(AL)Snon-repetitive

V_GS= 10 V; T_j(init)= 25 °C; I_D= 32 A; V_sup≤ 25 V;

-

100

mJ

drain-source avalanche unclamped; R_GS= 50 Ω; t_p= 0.17 ms

energy

003aaa755

03aa16

120

I_der

(%)

P

(%)

der

80

40

0

50

100

150

200

_mb(°C)

0

50

100

150

200

T

mb

(°C)

Fig 1. Normalized continuous drain current as a

function of mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

3 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aaa758

10³

I_D

Limit R_DSon= V_DS/ I_D

(A)

t_p= 10 µs

10²

100

s

μ

DC

10

1

1 ms

10 ms

1

10

10²

V_DS(V)

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

5. Thermal characteristics

Table 5.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from see Figure 4

junction to mounting

base

-

1.4

K/W

R_th(j-a)

thermal resistance from minimum footprint;

junction to ambient

[1]

-

75

50

-

K/W

SOT404 minimum footprint;

[1] Mounted on a printed-circuit board; vertical in still air.

003aaa759

10

Z_th(j-mb)

(K/W)

1

0.5

δ =

0.2

0.1

t_p

δ =

10^-1

P

0.05

T

0.02

single pulse

t

t_p

T

10^-2

10^-5

10^-4

10^-3

10^-2

10^-1

1

t_p(s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

4 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSS

drain-source

breakdown voltage

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

22

25

-

V

-

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

2.2

voltage

see Figure 7; see Figure 8

I_D= 1 mA; V_DS= V_GS; T_j= 175 °C;

see Figure 7; see Figure 8

0.5

1

-

V

I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

see Figure 7; see Figure 8

1.5

2

I_DSS

drain leakage current

gate leakage current

V_DS= 25 V; V_GS= 0 V; T_j= 25 °C

V_DS= 25 V; V_GS= 0 V; T_j= 175 °C

V_GS= 15 V; V_DS= 0 V; T_j= 25 °C

V_GS= -15 V; V_DS= 0 V; T_j= 25 °C

-

1

µA

nA

mΩ

-

500

100

9

I_GSS

10

7.65

R_DSon

drain-source on-state

resistance

V_GS= 10 V; I_D= 25 A; T_j= 25 °C;

see Figure 9; see Figure 10

V_GS= 5 V; I_D= 25 A; T_j= 175 °C;

see Figure 9; see Figure 10

-

18.9

10.5

1

24.3

13.5

-

mΩ

Ω

V_GS= 5 V; I_D= 25 A; T_j= 25 °C;

see Figure 9; see Figure 10

R_G

internal gate resistance f = 1 MHz; T_j= 25 °C

(AC)

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 0 A; V_DS= 0 V; V_GS= 4.5 V;

T_j= 25 °C

-

8.6

11

-

nC

I_D= 25 A; V_DS= 12 V; V_GS= 4.5 V;

T_j= 25 °C; see Figure 11; see Figure 12

Q_GS

gate-source charge

I_D= 25 A; V_DS= 12 V; V_GS= 4.5 V;

T_j= 25 °C; see Figure 12; see Figure 12

-

3.6

1.8

-

nC

Q_GS1

pre-threshold

gate-source charge

Q_GS2

post-threshold

-

1.8

-

nC

gate-source charge

Q_GD

gate-drain charge

-

4

3

-

nC

V

V_GS(pl)

gate-source plateau

voltage

I_D= 25 A; V_DS= 12 V; T_j= 25 °C;

see Figure 11; see Figure 12

C_iss

input capacitance

V_DS= 12 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 13

-

970

-

pF

V_DS= 0 V; V_GS= 0 V; f = 1 MHz;

1460

T_j= 25 °C

C_oss

C_rss

output capacitance

V_DS= 12 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 13

-

415

170

-

pF

reverse transfer

capacitance

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

5 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

Table 6.

Symbol

t_d(on)

t_r

Characteristics …continued

Parameter

Conditions

Min

Typ

13

Max

Unit

ns

turn-on delay time

rise time

V_DS= 12 V; R_L= 0.5 Ω; V_GS= 5 V;

R_G(ext)= 5.6 Ω; T_j= 25 °C

-

46

ns

t_d(off)

t_f

turn-off delay time

fall time

20

ns

15

ns

Source-drain diode

V_SD

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C;

see Figure 14

-

0.78

1.2

V

t_rr

reverse recovery time

recovered charge

I_S= 20 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 25 V; T_j= 25 °C

-

35

20

-

ns

Q_r

nC

003aaa760

003aaa762

80

10 8

6

V_GS(V) =

5

I_D

(A)

4.5

60

25

C

T = 175

j

C

°

4

3.6

3.2

40

20

0

40

20

0

2.8

2.4

0

0.2

0.4

0.6

0.8

1

0

2

4

6

V_DS(V)

V_GS(V)

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

6 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

03aa33

03aa36

2.5

V_GS(th)

(V)

10^-1

I_D

(A)

2

1.5

1

10^-2

10^-3

10^-4

10^-5

10^-6

max

typ

min

typ

max

min

0.5

0

-60

0

60

120

180

0

1

2

3

T ( C)

V_GS(V)

°

j

Fig 7. Gate-source threshold voltage as a function of

junction temperature

Fig 8. Sub-threshold drain current as a function of

gate-source voltage

003aaa761

03af18

30

2

V_GS(V) =

3.6

a

R_DSon

(m

)

Ω

1.5

4

20

10

0

4.5

1

0.5

0

5

6

8

10

-60

0

60

120

180

0

20

40

60

80

I_D(A)

T_j(°C)

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values

Fig 10. Normalized drain-source on-state resistance

factor as a function of junction temperature

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

7 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

003aaa763

10

V

DS

I_D= 25 A

T = 25

V_GS

(V)

C

°

j

I

8

6

4

2

0

D

V

GS(pl)

12 V

V_DD= 19 V

V

GS(th)

V

GS

Q

GS1

GS2

Q

GD

GS

Q

G(tot)

003aaa508

Fig 12. Gate charge waveform definitions

0

10

20

30

Q

_G(nC)

Fig 11. Gate-source voltage as a function of gate

charge; typical values

003aaa765

003aaa764

10⁴

80

I_S

(A)

C

(pF)

60

10³

40

20

0

C_iss

C_oss

T = 25 C

°

j

175

C

°

C_rss

V_DS(V)

10²

10^-1

1

10

10²

0

0.4

0.8

1.2

V_SD(V)

Fig 14. Source current as a function of source-drain

voltage; typical values

Fig 13. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

8 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

7. Package outline

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)

SOT428

y

E

A

1

b

2

E

1

mounting

base

D

2

D

1

H

D

2

L

2

L

1

3

b

1

b

M

c

w

A

e

1

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

y

max

D

min

E

min

L

1

min

2

1

UNIT

A

1

b

c

D

E

e

1

H

D

L

2

w

1

2

1

2.38

2.22

0.93

0.46

0.89

0.71

1.1

0.9

5.46

5.00

0.56

0.20

6.22

5.98

6.73

6.47

10.4

9.6

2.95

2.55

0.9

0.5

4.0

4.45

0.5

mm

2.285 4.57

0.2

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

06-02-14

06-03-16

SOT428

SC-63

TO-252

Fig 15. Package outline SOT428 (DPAK)

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

9 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

Release

date

Data sheet status

Change notice Supersedes

PHD78NQ03LT_6

Modifications:

20090611 Product data sheet

-

PHU_PHD78NQ03LT_5

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

PHU_PHD78NQ03LT_5

(9397 750 15084)

20050727 Product data sheet

20040726 Product data sheet

20020626 Product data

20020322 Product data

20011114 Product data

-

PHP_PHU78NQ03LT_4

PHP_PHB_PHD78NQ03LT-03

PHP_PHB_PHD78NQ03LT-02

PHP_PHB_PHD78NQ03LT-01

-

PHP_PHU78NQ03LT_4

(9397 750 13431)

PHP_PHB_PHD78NQ03LT-03

(9397 750 09667)

PHP_PHB_PHD78NQ03LT-02

(9397 750 09418)

PHP_PHB_PHD78NQ03LT-01

(9397 750 08916)

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

10 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status ^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

Applications — Applications that are described herein for any of these

9.2 Definitions

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PHD78NQ03LT_6

Product data sheet

Rev. 06 — 11 June 2009

11 of 12

PHD78NQ03LT

NXP Semiconductors

N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .11

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 June 2009

Document identifier: PHD78NQ03LT_6


型号：	PHD78NQ03LT/T3
厂家：	NXP
描述：	TRANSISTOR 75 A, 25 V, 0.0135 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252, PLASTIC, SC-63, DPAK-3, FET General Purpose Power 开关脉冲晶体管
文件：	总12页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PHD78NQ03LT/T3 [NXP]

相关型号：

PHD82NQ03LT

PHD83N03LT

PHD87N03LT

PHD95N03LT

PHD96NQ03LT

PHD97NQ03LT

PHD97NQ03LT,118

PHD98N03LT

PHD98N03LT/T3

PHD9NQ20T

PHD9NQ20T,118

PHD9NQ20T/T3