PHK04P02T_10 [NXP]
P-channel vertical D-MOS logic level FET Battery powered applications; P沟道垂直D- MOS逻辑电平FET电池供电的应用
| 型号： | PHK04P02T_10 |
| 厂家： | 
NXP |
| 描述： | P-channel vertical D-MOS logic level FET Battery powered applications |
| 文件： | 总12页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHK04P02T
P-channel vertical D-MOS logic level FET
Rev. 02 — 14 December 2010
Product data sheet
1. Product profile
1.1 General description
Logic level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using vertical D-MOS technology. This product is designed and qualified for use
in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for logic level gate drive
sources
Suitable for very low gate drive
sources voltage
1.3 Applications
Battery powered applications
High-speed digital interfaces
1.4 Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
Min Typ Max Unit
VDS
ID
-
-
-
-
-16
V
A
drain current
Tsp = 25 °C
-4.6
6
Ptot
total power
dissipation
-
-
5
W
Static characteristics
RDSon
drain-source on-state VGS = -2.5 V; ID = -1 A; Tj = 25 °C
-
-
117 150 mΩ
resistance
VGS = -4.5 V; ID = -1 A; Tj = 25 °C
80
120 mΩ
Dynamic characteristics
QGD gate-drain charge
VGS = -4.5 V; ID = -1 A;
VDS = -10 V; Tj = 25 °C
-
1.83
-
nC
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
S
S
S
G
D
D
D
D
source
source
source
gate
8
5
4
D
2
3
4
G
5
drain
1
S
6
drain
SOT96-1 (SO8)
001aaa025
7
drain
8
drain
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
PHK04P02T
SOT96-1
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
-16
-16
8
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 150 °C
RGS = 20 kΩ
-
V
VDGR
VGS
-
V
-8
V
ID
Tsp = 100 °C
Tsp = 25 °C
-
-1.87
-4.66
-26.4
5
A
-
A
IDM
Ptot
peak drain current
Tsp = 25 °C; pulsed
Tsp = 25 °C
-
A
total power dissipation
-
W
W
°C
°C
Tsp = 100 °C
-
2
Tstg
Tj
storage temperature
junction temperature
-55
-55
150
150
Source-drain diode
IS
source current
peak source current
Tsp = 25 °C
-
-
-4.66
-26
A
A
ISM
Tsp = 25 °C; pulsed; tp ≤ 5 s
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
2 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
001aam073
001aam074
100
120
P
(%)
80
tot
I
D
(%)
80
60
40
20
0
40
0
0
40
80
120
160
0
40
80
120
160
T
a
(°C)
T (°C)
a
VGS ≤ -10 V
Fig 1. Normalised power dissipation as a function of
ambient temperature
Fig 2. Normalized continuous drain current as a
function of ambient temperature
001aam075
2
10
I
DM
t
p
= 1 ms
(A)
R
DS(on)
= V / I
DS
D
10 ms
10
100 ms
1
D.C.
−1
10
−2
10
10
−1
2
1
10
10
V
DS
(V)
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
3 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-sp)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to mounted on metal clad substrate
solder point
-
25
-
K/W
001aam076
2
10
Z
th(j-sp)
D = 0.5
0.2
(K/W)
10
0.1
0.05
1
0.02
t
p
P
δ =
−1
T
10
10
10
−2
single pulse
t
t
p
T
−3
−6
−5
−4
−3
−2
−1
10
10
10
10
10
10
1
10
(s)
t
p
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
4 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source breakdown
ID = -10 µA; VGS = 0 V; Tj = 25 °C
-16
-
-
V
voltage
VGS(th)
gate-source threshold voltage
ID = -1 mA; VDS = VGS; Tj = 25 °C
ID = -1 mA; VDS = VGS; Tj = 150 °C
VDS = -13 V; VGS = 0 V; Tj = 25 °C
VDS = -13 V; VGS = 0 V; Tj = 150 °C
VGS = 8 V; VDS = 0 V; Tj = 25 °C
VGS = -8 V; VDS = 0 V; Tj = 25 °C
VGS = -2.5 V; ID = -1 A; Tj = 25 °C
VGS = -2.5 V; ID = -1 A; Tj = 150 °C
VGS = -1.8 V; ID = -0.5 A; Tj = 25 °C
VGS = -4.5 V; ID = -1 A; Tj = 25 °C
-0.4
-0.6
-
-
V
-0.1
-
V
IDSS
drain leakage current
gate leakage current
-
-
-
-
-
-
-
-
-50
-13
10
-100
-100
100
100
150
230
180
120
nA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
IGSS
10
RDSon
drain-source on-state
resistance
117
175
140
80
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
Coss
Crss
td(on)
tr
total gate charge
ID = -1 A; VDS = -10 V; VGS = -4.5 V;
Tj = 25 °C
-
7.2
1.7
1.83
528
200
57
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
S
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
-
-
VDS = -13 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C
-
-
-
VDS = -10 V; RL = 10 Ω; VGS = -8 V;
RG(ext) = 6 Ω; Tj = 25 °C; ID = -1 A
-
2
-
4.5
45
td(off)
tf
turn-off delay time
fall time
-
-
20
gfs
transfer conductance
VDS = -13 V; ID = -1 A; Tj = 25 °C
IS = -0.62 A; VGS = 0 V; Tj = 25 °C
1.5
4.5
Source-drain diode
VSD
trr
source-drain voltage
-
-
-
-0.62 -1.3
V
reverse recovery time
recovered charge
IS = -0.5 A; dIS/dt = -100 A/µs;
VGS = 0 V; VDS = -12.8 V; Tj = 25 °C
75
69
-
-
ns
nC
Qr
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
5 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
001aam077
001aam078
−5
0.7
R
DS(on)
(Ω)
−0.8
−1.0
−1.2
I
D
(A)
−4
0.6
0.5
0.4
0.3
0.2
0.1
0
−0.9
−1.1
−4.5
−2.5
−1.8
V
(V) = −1.3
GS
−1.3
−1.2
−3
−2
−1
0
−1.8
−2.5
−4.5
−1.1
−1.0
−0.9
(V) = −0.8
V
GS
0
−0.5
−1.0
−1.5
−2.0
0
−1
−2
−3
−4
−5
V
DS
(V)
I (A)
D
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
001aam079
001aam080
−5
8
I
D
g
(S)
fs
(A)
−4
T = 25 °C
j
T = 25 °C
j
T = 150 °C
j
6
4
2
0
T = 150 °C
j
−3
−2
−1
0
0
−0.5
−1.0
−1.5
−2.0
0
−0.8
−1.6
−2.4
V
GS
(V)
I (A)
D
VDS > ID x RDSon
VDS > ID x RDSon
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Forward transconductance as a function of
drain current; typical values
001aam081
001aam082
1.6
0.8
a
V
GS(th)
(V)
−2.5 V
1.4
1.2
1.0
0.8
0.6
0.6
0.4
0.2
0
V
GS
= −4.5 V
typical
−1.8 V
minimum
0
50
100
150
0
50
100
150
T (°C)
j
T (°C)
j
ID = 1 mA; VDS = VGS
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 10. Gate-source threshold voltage as a function of
junction temperature
PHK04P02T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
6 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
001aam083
001aam084
−2
3
2
10
D
(A)
10
I
C
iss
−3
−4
−5
−6
−7
10
C
(pF)
C
oss
10
10
10
10
10
C
rss
10
−10
−1
2
−1.0
−0.8
−0.6
−0.4
−0.2
0
−1
−10
−10
V
(V)
V
(V)
GS
DS
VDS = -5 V; Tj = 25 °C
VGS = 0 V; f = 1 MHz
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
001aam085
001aam086
−5
GS
(V)
−4
5
V
IF
(A)
4
−3
−2
−1
0
3
2
1
0
T = 150 °C
T = 25 °C
j
j
0
2
4
6
8
10
(nC)
0
0.4
0.8
1.2
Q
G
VSDS (V)
Tj = 25 °C; ID = -1 A
VGS = 0 V
Fig 13. Gate-source voltage as a function of turn-on
gate charge; typical values
Fig 14. Reverse diode current as a function of reverse
diode voltage; typical values
PHK04P02T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
7 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 15. Package outline SOT96-1 (SO8)
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
8 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
PHK04P02T v.2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20101214
Product data sheet
-
PHK04P02T v.1
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
PHK04P02T v.1
20020501
Product specification
-
-
PHK04P02T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
9 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
9. Legal information
9.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
9.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
PHK04P02T
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
10 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
non-automotive qualified products in automotive equipment or applications.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PHK04P02T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 14 December 2010
11 of 12
PHK04P02T
NXP Semiconductors
P-channel vertical D-MOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .8
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . .9
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .10
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 December 2010
Document identifier: PHK04P02T
相关型号：
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