PHK12NQ03LT [NXP]
N-channel TrenchMOS?? logic level FET; N沟道的TrenchMOS ？逻辑电平FET
| 型号： | PHK12NQ03LT |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS?? logic level FET |
| 文件： | 总12页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
M3D315
Rev. 02 — 02 March 2004
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
1.2 Features
■ Low on-state resistance
■ Fast switching.
1.3 Applications
■ DC-to-DC converters
■ Portable equipment applications.
1.4 Quick reference data
■ VDS ≤ 30 V
■ Ptot ≤ 2.5 W
■ ID ≤ 11.8 A
■ RDSon ≤ 14 mΩ
2. Pinning information
Table 1:
Pin
Pinning - SOT96-1 (SO8), simplified outline and symbol
Description
source (s)
gate (g)
Simplified outline
Symbol
1,2,3
4
d
8
5
5,6,7,8
drain (d)
g
1
4
s
MBB076
Top view
MBK187
SOT96-1 (SO8)
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
SO8
Description
Plastic small outline package; 8 leads
Version
SOT96
PHK12NQ03LT
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
-
gate-source voltage
drain current
-
±20
11.8
35.3
2.5
V
Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 2 and 3
Tamb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 1
-
A
IDM
Ptot
Tstg
Tj
peak drain current
total power dissipation
storage temperature
junction temperature
-
A
-
W
°C
°C
−55
−55
+150
+150
Source-drain diode
IS
source (diode forward) current
Tamb = 25 °C; pulsed; tp ≤ 10 s
-
-
11.8
440
A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 7.7 A;
tp = 2.35 ms; VDD ≤ 30 V; VGS = 10 V;
starting Tj = 25 °C
mJ
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
2 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03aa11
03aa19
120
120
I
der
(%)
P
der
(%)
80
80
40
40
0
0
0
50
100
150
200
( C)
0
50
100
150
200
( C)
T
°
T
°
amb
amb
V
GS ≥ 5 V
Ptot
Pder
=
× 100%
-----------------------
ID
P
°
tot(25 C)
Ider
=
× 100%
-------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of ambient temperature.
Fig 2. Normalized continuous drain current as a
function of ambient temperature.
003aaa160
2
10
I
D
Limit R
= V
/ I
DS D
t
p
= 10 s
µ
DSon
(A)
100
s
µ
10
1 ms
1
10 ms
DC
1 s
-1
10
10 s
-2
10
-1
10
2
10
1
10
V
(V)
DS
Tamb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
3 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
5. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter
Conditions
Min Typ Max Unit
Rth(j-a)
thermal resistance from junction to ambient
mounted on a printed-circuit board;
-
-
50
K/W
minimum footprint; tp ≤ 10 s; Figure 4
5.1 Transient thermal impedance
003aaa161
2
10
Z
th(j-amb)
(K/W)
= 0.5
δ
0.2
10
0.1
0.05
0.02
1
single pulse
-1
10
-4
10
-3
10
-2
10
-1
10
2
10
1
10
t
p
(s)
Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
4 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 250 µA; VGS = 0 V
ID = 250 µA; VDS = VGS; Tj = 25 °C; Figure 9
VDS = 24 V; VGS = 0 V
30
1
-
-
-
V
V
VGS(th)
IDSS
gate-source threshold voltage
drain-source leakage current
2
Tj = 25 °C
-
-
-
-
-
-
-
1
5
µA
µA
Tj = 100 °C
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 4.5 V; ID = 10 A; Figure 8
VGS = 10 V; ID = 12 A; Figure 8
100 nA
14 mΩ
10.5 mΩ
RDSon
drain-source on-state resistance
11
8.9
Dynamic characteristics
gfs
forward transconductance
VDS = 15 V; ID = 10 A;
-
-
-
-
-
-
-
-
-
-
-
34
-
-
-
-
S
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 15 A; VDD = 16 V; VGS = 5 V; Figure 13
17.6
4
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
4.4
VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11
1335 -
391
190
10.6
11.7
37
-
-
-
-
-
-
VDD = 16 V; RD = 10 Ω; VGS = 10 V
td(off)
tf
turn-off delay time
fall time
19
Source-drain (reverse) diode
VSD
trr
source-drain (diode forward) voltage IS = 1 A; VGS = 0 V; Figure 12
-
-
0.7
70
1.0
-
V
reverse recovery time
IS = 2.3 A; dIS/dt = −100 A/µs; VGS = 0 V
ns
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
5 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
003aaa162
003aaa163
16
20
5 V
4 V
V
> I x R
D
DS
DSon
I
I
D
D
(A)
(A)
12
15
10
5
2.8 V
8
4
0
2.5 V
T = 25 C
°
150 C
°
j
V
= 2.2 V
GS
0.8
0
0
1
2
3
4
0
0.2
0.4
0.6
1
V
(V)
GS
V
(V)
DS
Tj = 25 °C
Tj = 25 °C and 150 °C; VDS > ID × RDSon
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
003aaa164
03aa27
2
0.1
2.8 V
V
= 2.5 V
R
GS
DSon
a
(
)
Ω
0.08
0.06
0.04
0.02
0
1.5
1
0.5
0
4 V
5 V
-60
0
60
120
180
0
4
8
12
16
I
D
(A)
°
T ( C)
j
Tj = 25 °C
RDSon
-----------------------------
RDSon(25°C)
a =
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain source on-state resistance
factor as a function of junction temperature.
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
6 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
03aa33
03ai52
-1
-2
-3
-4
-5
-6
2.5
10
V
I
GS(th)
(V)
D
(A)
10
2
1.5
1
max
10
10
10
10
typ
min
typ
max
min
0.5
0
-60
0
60
120
180
0
1
2
3
°
T ( C)
V
(V)
GS
j
ID = 250 µA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
003aaa165
003aaa166
4
10
20
V
= 0 V
GS
I
S
(A)
C
(pF)
15
C
iss
3
10
10
5
C
C
oss
rss
150 C
°
T = 25 C
°
j
2
10
0
-1
10
2
1
10
10
0.4
0.6
0.8
1
V
(V)
V
(V)
SD
DS
VGS = 0 V; f = 1 MHz
Tj = 25 °C and 150 °C; VGS = 0 V
Fig 11. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
Fig 12. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
7 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
003aaa167
10
V
GS
(V)
8
6
4
2
0
0
10
20
30
40
Q
(nC)
G
ID = 15 A; VDD = 16 V
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
8 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 14. SOT96-1 (SO8).
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
9 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
8. Revision history
Table 6:
Revision history
CPCN
Rev Date
Description
02 20040302
-
Product data (9397 750 12955)
Modifications
• Data sheet updated to latest presentation standards.
• Section 1.4 “Quick reference data” correction to ID value.
• Section 4 “Limiting values” ID, IDM, Ptot and IS conditions and values corrected.
• Section 4 “Limiting values” Figure 1, 2 and 3 corrected.
• Section 4 “Limiting values” EDS(AL)S added.
• Section 5 “Thermal characteristics” typ and max values corrected.
• Section 5 “Thermal characteristics” Figure 4 corrected.
• Section 6 “Characteristics” Figure 13 corrected.
01 20020322
-
Product data (9397 750 09405)
9397 750 12955
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 02 March 2004
10 of 12
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
9. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
10. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 12
9397 750 12955
Product data
Rev. 02 — 02 March 2004
PHK12NQ03LT
N-channel TrenchMOS™ logic level FET
Philips Semiconductors
Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
4
5
5.1
6
7
8
9
10
11
12
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 02 March 2004
Document order number: 9397 750 12955
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