PHKD13N03LT,118_技术文档

PHKD13N03LT

SO8

Dual N-channel TrenchMOS logic level FET

Rev. 5 — 27 December 2011

Product data sheet

1. Product profile

1.1 General description

Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industrial applications only.

1.2 Features and benefits

 Low conduction losses due to low

 Suitable for high frequency

applications due to fast switching

characteristics

on-state resistance

 Simple gate drive required due to low

gate charge

1.3 Applications

 DC-to-DC convertors

 Notebook computers

 Portable equipment

 Lithium-ion battery applications

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min

Typ

Max

30

Unit

V

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 150 °C

-

[1]

I_D

T_sp= 25 °C; V_GS= 10 V; see Figure 1;

see Figure 3

10.4

A

P_tot

total power dissipation

T_sp= 25 °C; see Figure 2

-

3.57

20

W

Static characteristics

R_DSon

drain-source on-state resistance V_GS= 10 V; I_D= 8 A; T_j= 25 °C;

see Figure 9; see Figure 10

17

mΩ

Dynamic characteristics

Q_GDgate-drain charge

V_GS= 5 V; I_D= 5 A; V_DS= 15 V;

T_j= 25 °C; see Figure 11

-

3.9

-

nC

[1] Single device conducting.

PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

2. Pinning information

Table 2.

Pinning information

Symbol Description

1

Simplified outline

Graphic symbol

S1

G1

S2

G2

D2

D1

source1

gate1

8

5

4

D1 D1

D2 D2

2

3

source2

gate2

4

5

drain2

drain1

drain

1

6

SOT96-1 (SO8)

S1

G1

S2

G2

7

mbk725

8

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

SO8

Description

plastic small outline package; 8 leads; body width 3.9 mm

Version

PHKD13N03LT

SOT96-1

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

30

Unit

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 150 °C

T_j≥ 25 °C; T_j≤ 150 °C; R_GS= 20 kΩ

-

V

A

V_DGR

V_GS

-

30

-20

20

[1]

I_D

T_sp= 100 °C; V_GS= 10 V; see Figure 1

-

6.6

10.4

T_sp= 25 °C; V_GS= 10 V; see Figure 1;

see Figure 3

[1]

I_DM

P_tot

T_stg

T_j

peak drain current

T_sp= 25 °C; pulsed; t_p≤ 10 µs; see Figure 3

-

42

A

total power dissipation

storage temperature

junction temperature

T_sp= 25 °C; see Figure 2

-

3.57

150

W

°C

-55

Source-drain diode

[1]

I_S

source current

peak source current

T_sp= 25 °C

-

3.2

42

A

I_SM

T_sp= 25 °C; pulsed; t_p≤ 10 µs

[1] Single device conducting.

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Product data sheet

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PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

03aa25

03aa17

120

I

P

der

(%)

80

40

0

50

100

150

200

0

50

100

150

200

T

(°C)

T

(°C)

sp

Fig 1. Normalized continuous drain current as a

function of solder point temperature

Fig 2. Normalized total power dissipation as a

function of solder point temperature

003aag938

10²

I

t =10

s

μ

D

p

Limit R

= V / I

DS D

DSon

(A)

100

s

μ

10

1 ms

10 ms

1

DC

100 ms

10^-1

10^-2

10^-1

1

10

10²

V

(V)

DS

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

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Product data sheet

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PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5.

Symbol

R_th(j-sp)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from junction to

solder point

see Figure 4

-

35

K/W

R_th(j-a)

thermal resistance from junction to

ambient

minimum footprint ; mounted on

a printed-circuit board

-

70

-

K/W

003aaa415

10²

Z_th(j-sp)

(K/W)

δ = 0.5

10

0.2

0.1

0.05

t_p

δ =

0.02

P

1

T

single pulse

t

t_p

T

t_p(s)

10^-1

10^-4

10^-3

10^-2

10^-1

1

10

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration

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Product data sheet

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PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSSdrain-source breakdown

voltage

I_D= 250 µA; V_GS= 0 V; T_j= -55 °C

I_D= 250 µA; V_GS= 0 V; T_j= 25 °C

27

30

-

V

-

V_GS(th)

gate-source threshold voltage I_D= 250 µA; V_DS= V_GS; T_j= -55 °C;

see Figure 8

2.2

I_D= 250 µA; V_DS= V_GS; T_j= 150 °C;

see Figure 8

0.5

1

-

V

I_D= 250 µA; V_DS= V_GS; T_j= 25 °C;

see Figure 8

1.5

2

I_DSS

drain leakage current

gate leakage current

V_DS= 24 V; V_GS= 0 V; T_j= 25 °C

V_DS= 24 V; V_GS= 0 V; T_j= 100 °C

V_GS= 20 V; V_DS= 0 V; T_j= 25 °C

V_GS= -20 V; V_DS= 0 V; T_j= 25 °C

-

1

µA

nA

mΩ

5

I_GSS

100

34

R_DSon

drain-source on-state

resistance

V_GS= 10 V; I_D= 8 A; T_j= 150 °C;

see Figure 9; see Figure 10

V_GS= 4.5 V; I_D= 7 A; T_j= 25 °C;

see Figure 9

-

21

17

26

20

mΩ

V

_GS= 10 V; I_D= 8 A; T_j= 25 °C;

see Figure 9; see Figure 10

Dynamic characteristics

Q_G(tot)

Q_GS

Q_GD

C_iss

C_oss

C_rss

t_d(on)

t_r

total gate charge

I_D= 5 A; V_DS= 15 V; V_GS= 5 V;

T_j= 25 °C; see Figure 11

-

10.7

2.7

3.9

752

200

130

6

-

nC

pF

ns

gate-source charge

gate-drain charge

input capacitance

output capacitance

reverse transfer capacitance

turn-on delay time

rise time

V_DS= 15 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 12

V_DS= 15 V; R_L= 10 Ω; V_GS= 10 V;

R_G(ext)= 6 Ω; T_j= 25 °C; I_D= 1.5 A

7

t_d(off)

t_f

turn-off delay time

fall time

23

11

Source-drain diode

V_SD

source-drain voltage

I_S= 7 A; V_GS= 0 V; T_j= 25 °C;

see Figure 13

-

0.86

1.1

V

t_rr

reverse recovery time

recovered charge

I_S= 7 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 30 V; T_j= 25 °C

-

25

5

-

ns

Q_r

nC

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Product data sheet

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PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

003aaa325

003aaa326

10

VGS (V) =

10 V 5 V

3 V

V

> I × R

D DSon

DS

I

D

2.8 V

(A)

8

6

4

2

0

8

6

4

2

0

2.7 V

2.6 V

2.5 V

Tj = 150 °C

25 °C

2.4 V

2.3 V

0

0.2

0.4

0.6

0.8

V

1

0

1

2

3

(V)

V

(V)

GS

DS

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

003aaa426

03aa33

−1

10

2.5

V_GS(th)

(V)

I

D

(A)

−2

−3

−4

−5

−6

10

2

max

10

1.5

1

typ

min

typ

max

min

0.5

0

1

2

3

-60

0

60

120

180

T ( C)

°

V

(V)

j

GS

Fig 7. Sub-threshold drain current as a function of

gate-source voltage

Fig 8. Gate-source threshold voltage as a function of

junction temperature

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Product data sheet

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NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

003aaa327

03aa27

80

2

2.5 V

2.6 V

2.8 V

R

DSon

a

(mΩ)

60

1.5

40

20

0

1

3 V

4 V

5 V

10 V

0.5

0

V

(V) =

GS

0

2

4

6

8

10

−60

0

60

120

180

T ( C)

°

j

I

(A)

D

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values

Fig 10. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aaa330

003aaa328

4

5

10

V

GS

(V)

C

(pF)

4

3

2

1

0

3

10

C

iss

C

oss

C

rss

2

10

−1

0

5

10

15

10

1

10

102

Q

(nC)

V

(V)

DS

G

Fig 11. Gate-source voltage as a function of gate

charge; typical values

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

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Product data sheet

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PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

003aaa329

5

4

3

2

1

0

I

S

(A)

T = 25 °C

150 °C

j

0.2

0.4

0.6

0.8

1

V

(V)

SD

Fig 13. Source current as a function of source-drain voltage; typical values

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Product data sheet

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Dual N-channel TrenchMOS logic level FET

7. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

v

c

y

H

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 14. Package outline SOT96-1 (SO8)

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Product data sheet

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Dual N-channel TrenchMOS logic level FET

8. Revision history

Table 7.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PHKD13N03LT v.5

Modifications:

20111227

Product data sheet

-

PHKD13N03LT v.4

• Various changes to content.

20111122 Product data sheet

PHKD13N03LT v.4

-

PHKD13N03LT v.3

PHKD13N03LT

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Product data sheet

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Dual N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

Document status ^{[1] [2]}

Product status ^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

Right to make changes — NXP Semiconductors reserves the right to make

9.2 Definitions

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Preview — The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

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Product data sheet

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11 of 13

PHKD13N03LT

NXP Semiconductors

Dual N-channel TrenchMOS logic level FET

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

9.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Export control — This document as well as the item(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,

FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,

ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,

QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,

TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

non-automotive qualified products in automotive equipment or applications.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Product data sheet

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PHKD13N03LT

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Dual N-channel TrenchMOS logic level FET

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .12

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 27 December 2011

Document identifier: PHKD13N03LT


型号：	PHKD13N03LT,118
厂家：	NXP
描述：	PHKD13N03LT - Dual N-channel TrenchMOS logic level FET SOIC 8-Pin 开关光电二极管晶体管
文件：	总13页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PHKD13N03LT,118 [NXP]

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