PHP2N50E [NXP]
PowerMOS transistors Avalanche energy rated; 功率MOS晶体管的额定雪崩能量
| 型号： | PHP2N50E |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistors Avalanche energy rated |
| 文件： | 总10页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• Repetitive Avalanche Rated
• Fast switching
VDSS = 500 V
ID = 2 A
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
g
RDS(ON) ≤ 5 Ω
s
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies,
T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching
applications.
The PHP2N50E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB2N50E is supplied in the SOT404 surface mounting package.
The PHD2N50E is supplied in the SOT428 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
SOT428
PIN
1
DESCRIPTION
tab
tab
tab
gate
2
drain1
source
3
2
2
tab drain
1 2 3
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Tj = 25 ˚C to 150˚C
-
500
500
± 30
2
V
V
Drain-gate voltage
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
-
Gate-source voltage
Continuous drain current
-
V
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
-
A
-
1.3
8
A
IDM
PD
Tj, Tstg
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
-
-
A
Tmb = 25 ˚C
50
150
W
˚C
- 55
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
December 1998
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
EAS
Non-repetitive avalanche
energy
Unclamped inductive load, IAS = 1.26 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
-
82
mJ
V
DD ≤ 50 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:17
EAR
Repetitive avalanche energy2 IAR = 2 A; tp = 2.5 µs; Tj prior to
-
-
3.3
2
mJ
A
avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V;
refer to fig:18
IAS, IAR
Repetitive and non-repetitive
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
-
2.5
K/W
Rth j-a
Thermal resistance junction SOT78 package, in free air
-
-
60
50
-
-
K/W
K/W
to ambient
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
2 pulse width and repetition rate limited by Tj max.
December 1998
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA
VDS = VGS; ID = 0.25 mA
500
-
-
-
-
V
voltage
∆V(BR)DSS / Drain-source breakdown
0.1
%/K
∆Tj
voltage temperature
coefficient
RDS(ON)
VGS(TO)
gfs
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current VDS = 500 V; VGS = 0 V
VDS = 400 V; VGS = 0 V; Tj = 125 ˚C
Gate-source leakage current VGS = ±30 V; VDS = 0 V
VGS = 10 V; ID = 1 A
VDS = VGS; ID = 0.25 mA
VDS = 30 V; ID = 1 A
-
2.0
0.5
-
3.1
3.0
1.3
1
30
10
5
4.0
-
25
250
200
Ω
V
S
IDSS
µA
µA
nA
-
IGSS
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 2 A; VDD = 400 V; VGS = 10 V
-
-
-
20
2
12
25
3
15
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 250 V; RD = 120 Ω;
RG = 24 Ω
-
-
-
-
10
20
60
20
-
-
-
-
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
-
3.5
4.5
-
-
nH
nH
Ls
Internal source inductance
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
236
40
22
-
-
-
pF
pF
pF
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Tmb = 25˚C
-
-
-
-
-
-
2
A
A
V
ISM
VSD
Pulsed source current (body Tmb = 25˚C
diode)
8
Diode forward voltage
IS = 2 A; VGS = 0 V
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS = 2 A; VGS = 0 V; dI/dt = 100 A/µs
-
-
300
2.1
-
-
ns
µC
December 1998
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
Normalised Power Derating
PD%
Zth j-mb / (K/W)
10
120
110
100
90
80
70
60
50
40
30
20
10
0
D=
0.5
1
0.2
0.1
0.05
0.1
0.02
t
p
t
p
P
D
D =
T
0
t
T
0.01
0
20
40
60
80
Tmb /
100
120
140
10us
1ms
t / s
0.1s
10ms
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID, Drain current (Amps)
120
110
100
90
80
70
60
50
40
30
20
10
0
6
5
4
3
2
1
0
Tj = 25 C
20 V
10 V
7 V
6.5 V
6 V
5.5 V
VGS = 5 V
0
20
40
60
80
Tmb /
100
120
140
0
5
10
15
20
25
30
VDS, Drain-Source voltage (Volts)
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
Drain current, ID (Amps)
Tmb = 25 C
Drain-Source on resistance, RDS(ON) (Ohms)
10
1
10
8
5V 5.5 V
6 V
Tj = 25 C
tp =
10 us
6.5 V
7 V
100us
6
1 ms
10 V
DC
10 ms
100ms
VGS = 20 V
4
0.1
0.01
2
0
10
100
Drain-source voltage, VDS (Volts)
1000
0
1
2
3
4
5
Drain current, ID (Amps)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
December 1998
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
VGS(TO) / V
Drain current, ID (A)
6
max.
VDS > ID x RDS(on)max
4
5
typ.
3
4
3
2
min.
2
1
0
1
150 C
Tj = 25 C
0
-60 -40 -20
0
20
40
Tj /
60
C
80 100 120 140
0
2
4
6
8
10
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
SUB-THRESHOLD CONDUCTION
ID / A
Transconductance, gfs (S)
VDS > ID x RDS(on)max
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
2.5
2
Tj = 25 C
2 %
typ
98 %
1.5
1
150 C
0.5
0
0
1
2
3
4
0
1
2
3
4
5
6
Drain current, ID (A)
VGS / V
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
Capacitances, Ciss, Coss, Crss (pF)
1000
100
10
2
1
0
Ciss
Coss
Crss
1
-60 -40 -20
0
20 40 60 80 100 120 140
Tj /
1
10
100
1000
C
Drain-source voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1998
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
Gate-Source voltage, VGS (Volts)
20
Source-drain diode current, IF(A)
VGS = 0 V
10
8
ID = 2 A
300 V
200 V
VDD = 400 V
15
10
5
150 C
Tj = 25 C
6
4
2
0
0
0
10
20
Gate charge, Qg (nC)
30
40
0
0.5
1
1.5
Source-Drain voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
Switching times, td(on), tr, td(off), tf (ns)
1000
100
10
VDD = 250V
RD = 120 Ohms
Tj = 25 C
Non-repetitive Avalanche current, IAS (A)
Tj prior to avalanche = 25 C
10
1
td(off)
125 C
VDS
tr
tf
0.1
0.01
tp
ID
td(on)
PHP2N50E
1E-06
1E-05
1E-04
1E-03
1E-02
1
0
20
40
60
80
100
Avalanche time, tp (s)
Gate resistance, RG (Ohms)
Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG)
Fig.17. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
1.15
Maximum Repetitive Avalanche Current, IAR (A)
10
V(BR)DSS @ 25 C
1.1
Tj prior to avalanche = 25 C
1
1.05
1
0.1
125 C
0.95
0.9
0.01
PHP2N50E
1E-03 1E-02
0.001
1E-06
1E-05
1E-04
0.85
-100
-50
0
50
100
150
Avalanche time, tp (s)
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
Fig.18. Maximum permissible repetitive avalanche
current (IAR) versus avalanche time (tp)
December 1998
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
December 1998
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
4.5 max
1.4 max
10.3 max
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.20. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.21. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
December 1998
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane
1.1
2.38 max
0.93 max
5.4
6.73 max
tab
4 min
6.22 max
0.5 min
10.4 max
4.6
0.5
2
0.3
0.5
3
1
0.8 max
(x2)
2.285 (x2)
Fig.22. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.23. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
December 1998
9
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1998
10
Rev 1.200
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