PSMN041-80YLX [NXP]
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56 SOIC 4-Pin;型号: | PSMN041-80YLX |
厂家: | NXP |
描述: | N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56 SOIC 4-Pin |
文件: | 总13页 (文件大小:349K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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5
K
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
A
P
F
L
1 May 2013
Product data sheet
1. General description
Logic level gate drive N-channel enhancement mode Field-Effect Transistor (FET) in
LFPAK56 package. This product has been designed and qualified for use in a wide range
of industrial, communications and domestic equipment.
2. Features and benefits
High efficiency due to low switching and conduction losses
Suitable for logic level gate drive
LFPAK56 package is footprint compatible with other Power-SO8 types
Qualified to 175 °C
•
•
•
•
3. Applications
DC-to-DC converters
Load switch
TV power supplies
•
•
•
4. Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
80
Unit
V
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 25 °C; VGS = 10 V; Fig. 1
-
-
-
-
-
-
25
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 2
64
W
Static characteristics
RDSon drain-source on-state
resistance
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
-
32.8
-
41
mΩ
mΩ
VGS = 10 V; ID = 5 A; Tj = 175 °C;
Fig. 13; Fig. 12
103
Dynamic characteristics
QGD
gate-drain charge
total gate charge
VGS = 10 V; ID = 5 A; VDS = 64 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
4.3
-
-
nC
nC
QG(tot)
21.9
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NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
Symbol
Avalanche ruggedness
EDS(AL)S non-repetitive drain-
Parameter
Conditions
Min
Typ
Max
Unit
VGS = 10 V; Tj(init) = 25 °C; ID = 25 A;
Vsup ≤ 80 V; RGS = 50 Ω; unclamped;
Fig. 3
-
-
23.9
mJ
source avalanche
energy
5. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
mb
D
S
1
S
S
S
G
D
source
source
source
gate
2
G
3
mbb076
4
1
2 3 4
mb
mounting base; connected to
drain
LFPAK56; Power-
SO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN041-80YL
LFPAK56;
Plastic single-ended surface-mounted package (LFPAK56;
Power-SO8); 4 leads
SOT669
Power-SO8
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN041-80YL
04180
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
80
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
V
V
V
A
VDGR
VGS
-
80
-20
-
20
ID
VGS = 10 V; Tmb = 100 °C; Fig. 1
18
PSMN041-80YL
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Product data sheet
1 May 2013
2 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Min
Max
25
Unit
A
VGS = 10 V; Tmb = 25 °C; Fig. 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
Tmb = 25 °C; Fig. 2
-
IDM
peak drain current
-
100
64
A
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
peak soldering temperature
-
W
-55
-55
-
175
175
260
°C
°C
°C
Tsld(M)
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
54
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
100
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 25 A;
Vsup ≤ 80 V; RGS = 50 Ω; unclamped;
Fig. 3
-
23.9
mJ
003aak757
03aa16
30
25
20
15
10
5
120
I
D
(A)
P
der
(%)
80
40
0
0
0
25
50
75 100 125 150 175 200
T (°C)
0
50
100
150
200
j
T
(°C)
mb
Fig. 1. Continuous drain current as a function of
mounting base temperature
Fig. 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN041-80YL
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Product data sheet
1 May 2013
3 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
003aak759
2
10
I
AL
(A)
10
(1)
(2)
1
-1
10
-3
-2
-1
10
10
10
1
AL
10
t
(ms)
Fig. 3. Avalanche rating; avalanche current as a function of avalanche time
003aak758
3
10
I
D
(A)
Limit R
= V / I
DS
DSon
D
2
10
t
= 10 us
p
10
100 us
DC
1
1 ms
10 ms
100 ms
-1
10
-2
10
2
3
1
10
10
10
V
(V)
DS
Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
K/W
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
2.13
2.33
PSMN041-80YL
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© NXP B.V. 2013. All rights reserved
Product data sheet
1 May 2013
4 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
003aai358
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
t
p
-1
P
10
10
δ =
T
0.02
single shot
t
t
p
T
-2
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
(s)
p
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
72
80
0.5
-
-
-
-
-
-
V
V
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 175 °C;
voltage
Fig. 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 10
-
-
2.45
2.1
V
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
Fig. 10; Fig. 11
1.4
1.7
IDSS
drain leakage current
gate leakage current
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 175 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 5 A; Tj = 25 °C; Fig. 12
-
-
-
-
-
-
0.02
1
µA
µA
nA
-
500
100
100
41
IGSS
-
-
nA
RDSon
drain-source on-state
resistance
32.8
-
mΩ
mΩ
VGS = 5 V; ID = 5 A; Tj = 175 °C;
Fig. 13; Fig. 12
113
VGS = 10 V; ID = 5 A; Tj = 175 °C;
Fig. 13; Fig. 12
-
-
103
mΩ
VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12
f = 1 MHz
-
-
35.7
2.02
45
-
mΩ
Ω
RG
gate resistance
PSMN041-80YL
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Product data sheet
1 May 2013
5 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
QG(tot)
total gate charge
ID = 5 A; VDS = 64 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
21.9
11.9
-
-
nC
nC
ID = 5 A; VDS = 64 V; VGS = 5 V;
Tj = 25 °C; Fig. 14; Fig. 15
QGS
gate-source charge
ID = 5 A; VDS = 64 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
2.5
1.7
-
-
nC
nC
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
-
0.8
-
nC
QGD
gate-drain charge
-
-
4.3
2.4
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 5 A; VDS = 64 V; Tj = 25 °C;
Fig. 14; Fig. 15
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
1180
99
-
-
-
pF
pF
pF
reverse transfer
capacitance
54
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 60 V; RL = 10 Ω; VGS = 5 V;
RG(ext) = 5 Ω; Tj = 25 °C
-
-
-
-
8.6
-
-
-
-
ns
ns
ns
ns
11.2
16.1
10.5
turn-off delay time
fall time
Source-drain diode
VSD source-drain voltage
trr
IS = 5 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
-
0.8
21.3
22
1.2
V
reverse recovery time IS = 5 A; dIS/dt = 100 A/µs; VGS = 0 V;
-
-
ns
nC
VDS = 25 V; Tj = 25 °C
recovered charge
Qr
PSMN041-80YL
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Product data sheet
1 May 2013
6 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
003aaj100
003aaj099
10 V
100
50
R
I
DSon
D
(A)
4.5 V
3.5 V
= 3 V
80
60
40
20
0
40
V
GS
30
20
10
0
2.8 V
2.6 V
2.4 V
0
2
4
6
8
GS
10
0
1
2
3
DS
4
V
(V)
V
(V)
Tj = 25 °C; tp = 300 μs
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
003aak760
003aaj102
60
40
g
fs
I
D
(S)
(A)
50
32
40
30
20
10
0
24
16
8
175°C
T = 25°C
j
0
0
5
10
15
20
25
(A)
30
0
0.5
1
1.5
2
2.5
3
V
3.5
(V)
4
I
D
GS
Fig. 8. Forward transconductance as a function of
drain current; typical values
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
PSMN041-80YL
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Product data sheet
1 May 2013
7 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
003aah026
003aah025
3
10-1
VGS(th)
ID
(V)
2.5
(A)
10-2
max
2
min
typ
max
10-3
10-4
10-5
10-6
typ
1.5
min
1
0.5
0
-60
0
60
120
180
0
1
2
3
T ( C)
VGS (V)
°
j
Fig. 10. Gate-source threshold voltage as a function of Fig. 11. Sub-threshold drain current as a function of
junction temperature
gate-source voltage
003aaj105
003aaj818
100
3
R
DSon
2.6 V
2.8 V
a
2.4
1.8
1.2
0.6
0
80
60
40
20
3 V
3.5 V
4.5 V
V
= 10 V
GS
-60
0
60
120
180
0
5
10
15
20
(A)
25
Tj °C)
(
I
D
Tj = 25 °C; tp = 300 μs
Fig. 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig. 12. Drain-source on-state resistance as a function
of drain current; typical values
PSMN041-80YL
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Product data sheet
1 May 2013
8 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
003aaj107
10
V
V
DS
GS
(V)
I
D
8
V
GS(pl)
6
V
GS(th)
GS
V
= 14 V
GS
64 V
V
4
2
0
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig. 14. Gate charge waveform definitions
0
5
10
15
20
(nC)
25
Q
G
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aaj109
003aaj108
4
100
10
I
C
S
(A)
(pF)
80
C
iss
3
10
60
40
C
C
oss
2
10
20
175°C
rss
T = 25°C
j
0
10
-1
2
0
0.25
0.5
0.75
1
1.25
(V)
1.5
10
1
10
10
V
V
(V)
SD
DS
Fig. 17. Source-drain (diode forward) current as a
function of source-drain (diode forward)
voltage; typical values
Fig. 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN041-80YL
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Product data sheet
1 May 2013
9 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
11. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
SOT669
A
2
E
A
C
c
E
b
2
1
2
b
3
L
1
mounting
base
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
A
c
b
1/2 e
A
(A )
3
C
A
1
q
L
detail X
y
C
θ
8
0
0
5 mm
°
°
scale
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
(1)
Unit
A
A
A
A
b
b
b
b
4
c
c
2
D
D
1
E
E
e
H
L
L
L
2
w
y
1
2
3
2
3
1
1
max 1.20 0.15 1.10
nom
min 1.01 0.00 0.95
0.50 4.41 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3
6.2 0.85 1.3 1.3
5.8 0.40 0.8 0.8
0.1
0.25
1.27
0.25
mm
0.35 3.62 2.0 0.7 0.19 0.24 3.80
4.8 3.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
sot669_po
References
Outline
version
European
projection
Issue date
11-03-25
IEC
JEDEC
JEITA
SOT669
MO-235
13-02-27
Fig. 18. Package outline LFPAK56; Power-SO8 (SOT669)
PSMN041-80YL
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Product data sheet
1 May 2013
10 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
Product
Definition
status [1][2] status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
12.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
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associated with their applications and products.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
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damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
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Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
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responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
PSMN041-80YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
1 May 2013
11 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN041-80YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
1 May 2013
12 / 13
NXP Semiconductors
PSMN041-80YL
N-channel 80 V 41 mΩ logic level MOSFET in LFPAK56
13. Contents
1
General description ............................................... 1
Features and benefits ............................................1
Applications ........................................................... 1
Quick reference data ............................................. 1
Pinning information ...............................................2
Ordering information .............................................2
Marking ...................................................................2
Limiting values .......................................................2
Thermal characteristics .........................................4
Characteristics .......................................................5
Package outline ................................................... 10
2
3
4
5
6
7
8
9
10
11
12
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
12.1
12.2
12.3
12.4
© NXP B.V. 2013. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 May 2013
PSMN041-80YL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
1 May 2013
13 / 13
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