SAA7105E/V1/S1,557_技术文档

SAA7104E; SAA7105E

Digital video encoder

Rev. 02 — 23 December 2005

Product data sheet

1. General description

The SAA7104E; SAA7105E is an advanced next-generation video encoder which

converts PC graphics data at maximum 1280 × 1024 resolution (optionally 1920 × 1080

interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and

anti-ﬂicker ﬁlter (maximum 5 lines) ensures properly sized and ﬂicker-free TV display as

CVBS or S-video output.

Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals

together with a TTL composite sync to feed SCART connectors.

When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the

RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor

at maximum 1280 × 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port

can provide Y, P_Band P_Rsignals for HDTV monitors.

The device includes a sync/clock generator and on-chip DACs.

All inputs intended to interface to the host graphics controller are designed for low-voltage

signals between down to 1.1 V and up to 3.6 V.

2. Features

■ Digital PAL/NTSC encoder with integrated high quality scaler and anti-ﬂicker ﬁlter for

TV output from a PC

■ Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller

■ 27 MHz crystal-stable subcarrier generation

■ Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip

or from external source

■ Programmable assignment of clock edge to bytes (in double edged mode)

■ Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as

reference clock for the VGC, as well

■ PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)

■ Hot-plug detection through dedicated interrupt pin

■ Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 × 1024

graphics data at 60 Hz or 50 Hz frame rate

■ Supported VGA resolutions for HDTV output up to 1920 × 1080 interlaced graphics

data at 60 Hz or 50 Hz frame rate

■ Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,

C_B), VBS (GREEN, CVBS) and C (RED, C_R) (signals in parenthesis are optional); all at

10-bit resolution

■ Non-Interlaced (NI) C_B-Y-C_Ror RGB input at maximum 4 : 4 : 4 sampling

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

■ Downscaling and upscaling from 50 % to 400 %

■ Optional interlaced C_B-Y-C_Rinput of Digital Versatile Disc (DVD) signals

■ Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with

maximum 85 MHz)

■ 3 bytes × 256 bytes RGB Look-Up Table (LUT)

■ Support for hardware cursor

■ HDTV up to 1920 × 1080 interlaced and 1280 × 720 progressive, including 3-level

sync pulses

■ Programmable border color of underscan area

■ Programmable 5 line anti-ﬂicker ﬁlter

■ On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)

■ Fast I²C-bus control port (400 kHz)

■ Encoder can be master or slave

■ Adjustable output levels for the DACs

■ Programmable horizontal and vertical input synchronization phase

■ Programmable horizontal sync output phase

■ Internal Color Bar Generator (CBG)

■ Optional support of various Vertical Blanking Interval (VBI) data insertion

■ Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03

(525p) as option; this applies to the SAA7104E only

■ Optional cross-color reduction for PAL and NTSC CVBS outputs

■ Power-save modes

■ Joint Test Action Group (JTAG) Boundary Scan Test (BST)

■ Monolithic CMOS 3.3 V device, 5 V tolerant I/Os

3. Quick reference data

Table 1:

Quick reference data

Symbol

V_DDA

V_DDD

I_DDA

Parameter

Conditions

Min

3.15

1

Typ

3.3

Max

3.45

115

200

Unit

V

analog supply voltage

digital supply voltage

analog supply current

digital supply current

input signal voltage levels

3.3

V

110

175

mA

I_DDD

1

V_i

TTL compatible

V_o(p-p)

analog CVBS output signal

voltage for a 100/100 color

bar at 75/2 Ω load

-

1.23

-

V

(peak-to-peak value)

R_L

load resistance

-

37.5

-

Ω

ILE_lf(DAC)

low frequency integral

linearity error of DACs

±3

LSB

DLE_lf(DAC)

T_amb

low frequency differential

linearity error of DACs

-

±1

LSB

ambient temperature

0

70

°C

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

2 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

4. Ordering information

Table 2:

Ordering information

Type number Package

Name

Description

Version

SAA7104E

SAA7105E

LBGA156

plastic low proﬁle ball grid array package;

156 balls; body 15 × 15 × 1.05 mm

SOT700-1

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

3 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

6. Pinning information

6.1 Pinning

ball A1

index area

1

2 3 4 5 6 7 8 9 10 11 12 13 14

A

B

C

D

E

F

G

H

J

SAA7104E

SAA7105E

K

L

M

N

P

001aad370

Transparent top view

Fig 2. Pin conﬁguration

Table 3:

A2

Pin allocation table

Symbol

A3

A5

A7

A9

B1

B3

B5

B7

B9

C2

C4

C6

C8

D1

D3

D5

D7

D9

E2

E4

Symbol

PD4

PD7

A4

TRST

XTALI

A6

XTALO

V_SSA2

DUMP

A8

RSET

A10

B2

V_DDA1

PD9

PD8

PD5

B4

PD6

TDI

B6

V_DDA2, V_DDA4

V_SSA1

DUMP

B8

V_DDA1

C1

C3

C5

C7

C9

D2

D4

D6

D8

E1

PD11

PD10

TTX_SRES

TTXRQ_XCLKO2

V_SSD1, V_SSD2, V_SSD3, V_SSD4

GREEN_VBS_CVBS

V_DDA1

BLUE_CB_CVBS

RED_CR_C_CVBS

TDO

RESET

TMS

V_DDD2, V_DDD3, V_DDD4

V_DDA3

V_SSD1, V_SSD2, V_SSD3, V_SSD4

VSM

HSM_CSYNC

TCK

V_DDA1

SCL

E3

HSVGC

V_SSD1, V_SSD2, V_SSD3, V_SSD4

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

5 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 3:

E12

F2

Pin allocation table…continued

Symbol

F1

Symbol

VSVGC

PD3

reserved

PIXCLKI

V_DDD1

FSVGC

CBO

F3

F4

F12

G2

G4

H2

TVD

G1

SDA

G3

PIXCLKO

PD1

H1

PD2

H3

PD0

6.2 Pin description

Table 4:

Symbol

PD7

Pin description

A2

Type^[1]Description

I

pixel data 7^[2]; MSB with C_B-Y-C_R4 : 2 : 2

PD4

A3

I

pixel data 4^[2]; MSB − 3 with C_B-Y-C_R4 : 2 : 2

[5]

TRST

XTALI

XTALO

DUMP

A4

I/pu

I

test reset input for BST; active LOW^[3]

,

^[4]and

A5

crystal oscillator input

A6

O

crystal oscillator output

A7, B7

O

DAC reference pin; connected via 12 Ω resistor to

analog ground

V_SSA2

RSET

A8

A9

S

analog ground 2

O

DAC reference pin; connected via 1 kΩ resistor to

analog ground (do not use capacitor in parallel with

1 kΩ resistor)

V_DDA1

A10, B9,

C9, D9

S

analog supply voltage 1 (3.3 V for DACs)

PD9

B1

B2

B3

B4

B5

B6

B8

C1

C2

C3

C4

I

pixel data 9^[2]

pixel data 8^[2]

PD8

I

PD5

I

pixel data 5^[2]; MSB − 2 with C_B-Y-C_R4 : 2 : 2

pixel data 6^[2]; MSB − 1 with C_B-Y-C_R4 : 2 : 2

test data input for BST^[3]

analog supply voltage 2 (3.3 V for DACs)

analog supply voltage 4 (3.3 V)

analog ground 1

PD6

I

TDI

I

V_DDA2

S

I

V_DDA4

V_SSA1

PD11

pixel data 11^[2]

pixel data 10^[2]

PD10

I

TTX_SRES

TTXRQ_XCLKO2

I

teletext input or sync reset input

O

teletext request output or 13.5 MHz clock output of

the crystal oscillator^[6]

V_SSD1

C5, D5, E4 S

digital ground 1

V_SSD2

digital ground 2

V_SSD3

digital ground 3

V_SSD4

digital ground 4

BLUE_CB_CVBS

C6

O

analog output of BLUE or C_Bor CVBS signal

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

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SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 4:

Symbol

Pin description…continued

Type^[1]Description

GREEN_VBS_CVBS C7

RED_CR_C_CVBS C8

O

I

analog output of GREEN or VBS or CVBS signal

analog output of RED or C_Ror C or CVBS signal

test data output for BST^[3]

TDO

D1

D2

D3

D4

D6

D7

RESET

TMS

reset input; active LOW

test mode select input for BST^[3]

I/pu

S

V_DDD2

V_DDD3

V_DDD4

V_DDA3

VSM

digital supply voltage 2 (3.3 V for I/Os)

digital supply voltage 3 (3.3 V for core)

digital supply voltage 4 (3.3 V for core)

analog supply voltage 3 (3.3 V for oscillator)

S

O

vertical synchronization output to monitor

(non-interlaced auxiliary RGB)

HSM_CSYNC

D8

O

horizontal synchronization output to monitor

(non-interlaced auxiliary RGB) or composite sync for

RGB-SCART

TCK

E1

E2

E3

I/pu

I(/O)

I/O

test clock input for BST^[3]

serial clock input (I²C-bus) with inactive output path

SCL

HSVGC

horizontal synchronization output to VGC (optional

input)^[6]

reserved

VSVGC

E12

F1

-

to be reserved for future applications

I/O

vertical synchronization output to VGC (optional

input)^[6]

PIXCLKI

PD3

F2

F3

F4

I

pixel clock input (looped through)

pixel data 3^[2]; MSB − 4 with C_B-Y-C_R4 : 2 : 2

I

V_DDD1

S

digital supply voltage 1 for pins PD11 to PD0,

PIXCLKI, PIXCLKO, FSVGC, VSVGC, HSVGC, CBO

and TVD

TVD

F12

G1

O

interrupt if TV is detected at DAC output

FSVGC

I/O

frame synchronization output to Video Graphics

Controller (VGC) (optional input)^[6]

SDA

G2

G3

G4

H1

H2

H3

I/O

serial data input/output (I²C-bus)

composite blanking output to VGC; active LOW^[6]

CBO

I/O

PIXCLKO

PD2

O

I

pixel clock output to VGC

pixel data 2^[2]; MSB − 5 with C_B-Y-C_R4 : 2 : 2

pixel data 1^[2]; MSB − 6 with C_B-Y-C_R4 : 2 : 2

pixel data 0^[2]; MSB − 7 with C_B-Y-C_R4 : 2 : 2

PD1

I

PD0

I

[1] Pin type: I = input, O = output, S = supply, pu = pull-up.

[2] See Table 12 to Table 18 for pin assignment.

[3] In accordance with the ‘IEEE1149.1’ standard the pins TDI, TMS, TCK and TRST are input pins with an

internal pull-up resistor and TDO is a 3-state output pin.

[4] For board design without boundary scan implementation connect TRST to ground.

[5] This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port

(TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.

[6] Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see Section 7.1.

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

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SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

7. Functional description

The digital video encoder encodes digital luminance and color difference signals

(C_B-Y-C_R) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or

C_R-Y-C_Bsignals. NTSC M, PAL B/G and sub-standards are supported.

The SAA7104E; SAA7105E can be directly connected to a PC video graphics controller

with a maximum resolution of 1280 × 1024 (progressive) or 1920 × 1080 (interlaced) at a

50 Hz or 60 Hz frame rate. A programmable scaler scales the computer graphics picture

so that it will ﬁt into a standard TV screen with an adjustable underscan area.

Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-ﬂicker ﬁlter for

a ﬂicker-free display at a very high sharpness.

Besides the most common 16-bit 4 : 2 : 2 C_B-Y-C_Rinput format (using 8 pins with double

edge clocking), other C_B-Y-C_Rand RGB formats are also supported;

see Table 12 to Table 18.

A complete 3 bytes × 256 bytes Look-Up Table (LUT), which can be used, for example, as

a separate gamma corrector, is located in the RGB domain; it can be loaded either

through the video input port Pixel Data (PD) or via the I²C-bus.

The SAA7104E; SAA7105E supports a 32-bit × 32-bit × 2-bit hardware cursor, the pattern

of which can also be loaded through the video input port or via the I²C-bus.

It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the

anti-ﬂicker ﬁlter, and in most cases the scaler, will simply be bypassed.

Besides the applications for video output, the SAA7104E; SAA7105E can also be used for

generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed

to the DACs. This may be of interest for example, when the graphics controller provides a

second graphics window at its video output port.

The basic encoder function consists of subcarrier generation, color modulation and

insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz

(independent of the actual pixel clock used at the input side), corresponding to an internal

4 : 2 : 2 bandwidth in the luminance/color difference domain. Luminance and

chrominance signals are ﬁltered in accordance with the standard requirements of

‘RS-170-A’ and ‘ITU-R BT.470-3’.

For ease of analog post ﬁltering the signals are twice oversampled to 27 MHz before

digital-to-analog conversion.

The total ﬁlter transfer characteristics (scaler and anti-ﬂicker ﬁlter are not taken into

account) are illustrated in Figure 6 to Figure 11. All three DACs are realized with full 10-bit

resolution. The C_R-Y-C_Bto RGB dematrix can be bypassed (optionally) in order to provide

the upsampled C_R-Y-C_Binput signals.

The 8-bit multiplexed C_B-Y-C_Rformats are ‘ITU-R BT.656’ (D1 format) compatible, but the

SAV and EAV codes can be decoded optionally, when the device is operated in Slave

mode. For assignment of the input data to the rising or falling clock edge

see Table 12 to Table 18.

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Rev. 02 — 23 December 2005

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SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

In order to display interlaced RGB signals through a euro-connector TV set, a separate

digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced

up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing

of a TV set.

The SAA7104E; SAA7105E synthesizes all necessary internal signals, color subcarrier

frequency and synchronization signals from that clock.

Wide screen signalling data can be loaded via the I²C-bus and is inserted into line 23 for

standards using a 50 Hz ﬁeld rate.

VPS data for program dependent automatic start and stop of such featured VCRs is

loadable via the I²C-bus.

The IC also contains closed caption and extended data services encoding (line 21), and

supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate

(see Figure 15). It is also possible to load data for the copy generation management

system into line 20 of every ﬁeld (525/60 line counting).

A number of possibilities are provided for setting different video parameters such as:

• Black and blanking level control

• Color subcarrier frequency

• Variable burst amplitude etc.

7.1 Reset conditions

To activate the reset a pulse at least of 2 crystal clocks duration is required.

During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC,

CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set

to 3-state. A reset also forces the I²C-bus interface to abort any running bus transfer and

sets it into receive condition.

After reset, the state of the I/Os and other functions is deﬁned by the strapping pins until

an I²C-bus access redeﬁnes the corresponding registers; see Table 5.

Table 5:

Strapping pins

Tied

Preset

FSVGC

LOW

NTSC M encoding, PIXCLK ﬁts to 640 × 480 graphics input

PAL B/G encoding, PIXCLK ﬁts to 640 × 480 graphics input

4 : 2 : 2 Y-C_B-C_Rgraphics input (format 0)

4 : 4 : 4 RGB graphics input (format 3)

input demultiplex phase: LSB = LOW

input demultiplex phase: LSB = HIGH

input demultiplex phase: MSB = LOW

input demultiplex phase: MSB = HIGH

HIGH

VSVGC

CBO

LOW

HIGH

LOW

HIGH

HSVGC

LOW

HIGH

TTXRQ_XCLKO2 LOW

slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar

is active)

HIGH

master (FSVGC, VSVGC and HSVGC are outputs)

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Rev. 02 — 23 December 2005

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SAA7104E; SAA7105E

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Digital video encoder

7.2 Input formatter

The input formatter converts all accepted PD input data formats, either RGB or Y-C_B-C_R,

to a common internal RGB or Y-C_B-C_Rdata stream.

When double-edge clocking is used, the data is internally split into portions PPD1 and

PPD2. The clock edge assignment must be set according to the I²C-bus control bits SLOT

and EDGE for correct operation.

If Y-C_B-C_Ris being applied as a 27 MB/s data stream, the output of the input formatter can

be used directly to feed the video encoder block.

The horizontal upscaling is supported via the input formatter. According to the

programming of the pixel clock dividers (see Section 7.10), it will sample up the data

stream to 1 ×, 2 × or 4 × the input data rate. An optional interpolation ﬁlter is available. The

clock domain transition is handled by a 4 entries wide FIFO which gets initialized every

ﬁeld or explicitly at request. A bypass for the FIFO is available, especially for high input

data rates.

7.3 RGB LUT

The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus

it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the

event that the indexed color data is applied, the RAMs are addressed in parallel.

The LUTs can either be loaded by an I²C-bus write access or can be part of the pixel data

input through the PD port. In the latter case, 256 bytes × 3 bytes for the R, G and B LUT

are expected at the beginning of the input video line, two lines before the line that has

been deﬁned as ﬁrst active line, until the middle of the line immediately preceding the ﬁrst

active line. The ﬁrst 3 bytes represent the ﬁrst RGB LUT data, and so on.

7.4 Cursor insertion

A 32 dots × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be

uploaded by an I²C-bus write access to speciﬁc registers or in the pixel data input through

the PD port. In the latter case, the 256 bytes deﬁning the cursor bit map (2 bits per pixel)

are expected immediately following the last RGB LUT data in the line preceding the ﬁrst

active line.

The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these

bits depends on the CMODE I²C-bus register as described in Table 8. Transparent means

that the input pixels are passed through, the ‘cursor colors’ can be programmed in

separate registers.

The bit map is stored with 4 pixels per byte, aligned to the least signiﬁcant bit. So the ﬁrst

pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The ﬁrst index is the

column, followed by the row; index 0,0 is the upper left corner.

Table 6:

7

Layout of a byte in the cursor bit map

6

5

4

3

2

1

0

pixel n + 3

pixel n + 2

pixel n + 1

pixel n

D1

D0

D1

D0

D1

D0

D1

D0

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Philips Semiconductors

Digital video encoder

For each direction, there are 2 registers controlling the position of the cursor, one controls

the position of the ‘hot spot’, the other register controls the insertion position. The hot spot

is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position

registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner.

While it is not possible to move the hot spot beyond the left respectively upper screen

border this is perfectly legal for the right respectively lower border. It should be noted that

the cursor position is described relative to the input resolution.

Table 7:

Cursor bit map

7

Byte

0

6

5

4

3

2

1

0

row 0 column 3

row 0 column 7

row 0 column 11

...

row 0 column 2

row 0 column 6

row 0 column 10

...

row 0 column 1

row 0 column 5

row 0 column 9

...

row 0 column 0

row 0 column 4

row 0 column 8

...

1

2

...

6

row 0 column 27

row 0 column 31

...

row 0 column 26

row 0 column 30

...

row 0 column 25

row 0 column 29

...

row 0 column 24

row 0 column 28

...

7

...

254

255

row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24

row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28

Table 8:

Cursor modes

Cursor pattern

Cursor mode

CMODE = 0

CMODE = 1

00

01

10

11

second cursor color

ﬁrst cursor color

transparent

second cursor color

ﬁrst cursor color

transparent

inverted input

auxiliary cursor color

7.5 RGB Y-C_B-C_Rmatrix

RGB input signals to be encoded to PAL or NTSC are converted to the Y-C_B-C_Rcolor

space in this block. The color difference signals are fed through low-pass ﬁlters and

formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing.

A gain adjust option corrects the level swing of the graphics world (black-to-white as

0 to 255) to the required range of 16 to 235.

The matrix and formatting blocks can be bypassed for Y-C_B-C_Rgraphics input.

When the auxiliary VGA mode is selected, the output of the cursor insertion block is

immediately directed to the triple DAC.

7.6 Horizontal scaler

The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines

compensate the color phase offset automatically.

The scaler starts processing after a programmable horizontal offset and continues with a

number of input pixels. Each input pixel is a programmable fraction of the current output

pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1.

SAA7104E_SAA7105E_2

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SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

If the SAA7104E; SAA7105E input data is in accordance with ‘ITU-R BT.656’, the scaler

enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1.

With higher values, upscaling will occur.

The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after

800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.

7.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the

vertical scaler.

Besides the entire input frame, it receives the ﬁrst and last lines of the border to allow

anti-ﬂicker ﬁltering.

The circuit generates the interlaced output ﬁelds by scaling down the input frames with

different offsets for odd and even ﬁelds. Increasing the YSKIP setting reduces the

anti-ﬂicker function. A YSKIP value of 4095 switches it off; see Table 78.

An additional, programmable vertical ﬁlter supports the anti-ﬂicker function. This ﬁlter is

not available at upscaling factors of more than 2.

The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions

of the offset registers are not sufﬁcient, so the weighting factors for the ﬁrst lines can also

be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.

Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The

maximum factor depends on the setting of the anti-ﬂicker function and can be derived from

the formulae given in Section 7.20.

An additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is

required for the old VGA modes like 320 × 240.

7.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock

domain. The write clock is PIXCLK and the read clock is XTAL. An underﬂow or overﬂow

condition can be detected via the I²C-bus read access.

In order to avoid underﬂows and overﬂows, it is essential that the frequency of the

synthesized PIXCLK matches to the input graphics resolution and the desired scaling

factor.

7.9 Border generator

When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on

a TV screen, it is desired in many cases not to lose picture information due to the inherent

overscanning of a TV set. The desired amount of underscan area, which is achieved

through appropriate scaling in the vertical and horizontal direction, can be ﬁlled in the

border generator with an arbitrary true color tint.

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7.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz crystal oscillator, which can operate

with either a fundamental wave crystal or a 3rd-harmonic crystal.

The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and

the I²C-bus control block. It also usually supplies the triple DAC, with the exception of the

auxiliary VGA or HDTV mode, where the triple DAC is clocked by the pixel clock

(PIXCLK).

The DTO can be programmed to synthesize all relevant pixel clock frequencies between

circa 40 MHz and 85 MHz. Two programmable dividers provide the actual clock to be

used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8.

For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.

The internal clock can be switched completely to the pixel clock input. In this event, the

input FIFO is useless and will be bypassed.

The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock

dividers get re-initialized every ﬁeld. Optionally, the DTO can be cleared with each V-sync.

At proper programming, this will make the pixel clock frequency a precise multiple of the

vertical and horizontal frequencies. This is required for some graphic controllers.

7.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking

ﬁlter for all relevant synthesized pixel clock frequencies.

7.12 Encoder

7.12.1 Video path

The encoder generates luminance and color subcarrier output signals from the Y,

C_Band C_Rbaseband signals, which are suitable for use as CVBS or separate Yand C

signals.

Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer

graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656

style signal.

Luminance is modiﬁed in gain and in offset (the offset is programmable in a certain range

to enable different black level set-ups). A blanking level can be set after insertion of a ﬁxed

synchronization pulse tip level, in accordance with standard composite synchronization

schemes. Other manipulations used for the Macrovision anti-taping process, such as

additional insertion of AGC super-white pulses (programmable in height), are supported

by the SAA7104E only.

To enable easy analog post ﬁltering, luminance is interpolated from a 13.5 MHz data rate

to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer

characteristics of the luminance interpolation ﬁlter are illustrated in Figure 8 and Figure 9.

Appropriate transients at start/end of active video and for synchronization pulses are

ensured.

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Chrominance is modiﬁed in gain (programmable separately for C_Band C_R), and a

standard dependent burst is inserted, before baseband color signals are interpolated from

a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be

bypassed, thus providing a higher color bandwidth, which can be used for the Yand C

output. The transfer characteristics of the chrominance interpolation ﬁlter are illustrated in

Figure 6 and Figure 7.

The amplitude (beginning and ending) of the inserted burst, is programmable in a certain

range that is suitable for standard signals and for special effects. After the succeeding

quadrature modulator, color is provided on the subcarrier in 10-bit resolution.

The numeric ratio between the Yand C outputs is in accordance with the standards.

7.12.2 Teletext insertion and encoding (not simultaneously with real-time control)

Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock.

At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided

after a programmable delay at input pin TTX_SRES.

Phase variant interpolation is achieved on this bitstream in the internal teletext encoder,

providing sufﬁcient small phase jitter on the output text lines.

TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source,

indicating the insertion period of bitstream at lines which can be selected independently

for both ﬁelds. The internal insertion window for text is set to 360 (PAL WST),

296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol

and timing are illustrated in Figure 15.

Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.

7.12.3 Video Programming System (VPS) encoding

Five bytes of VPS information can be loaded via the I²C-bus and will be encoded in the

appropriate format into line 16.

7.12.4 Closed caption encoder

Using this circuit, data in accordance with the speciﬁcation of closed caption or extended

data service, delivered by the control interface, can be encoded (line 21). Two dedicated

pairs of bytes (two bytes per ﬁeld), each pair preceded by run-in clocks and framing code,

are possible.

The actual line number in which data is to be encoded, can be modiﬁed in a certain range.

The data clock frequency is in accordance with the deﬁnition for NTSC M standard

32 times horizontal line frequency.

Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the

DACs corresponds to approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz ﬁeld frequencies at 32 times the

horizontal line frequency.

7.12.5 Anti-taping (SAA7104E only)

For more information contact your nearest Philips Semiconductors sales ofﬁce.

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7.13 RGB processor

This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be

fed to a SCART plug.

Before Y, C_Band C_Rsignals are de-matrixed, individual gain adjustment for Y and color

difference signals and 2 times oversampling for luminance and 4 times oversampling for

color difference signals is performed. The transfer curves of luminance and color

difference components of RGB are illustrated in Figure 10 and Figure 11.

7.14 Triple DAC

Both Yand C signals are converted from digital-to-analog in a 10-bit resolution at the

output of the video encoder. Yand C signals are also combined into a 10-bit CVBS signal.

The CVBS output signal occurs with the same processing delay as the Y, C and optional

RGB or C_R-Y-C_Boutputs. Absolute amplitude at the input of the DAC for CVBS is reduced

by ¹⁵

⁄₁₆with respect to Yand C DACs to make maximum use of the conversion ranges.

RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing

a 10-bit resolution.

The reference currents of all three DACs can be adjusted individually in order to adapt for

different output signals. In addition, all reference currents can be adjusted commonly to

compensate for small tolerances of the on-chip band gap reference voltage.

Alternatively, all currents can be switched off to reduce power dissipation.

All three outputs can be used to sense for an external load (usually 75 Ω) during a

pre-deﬁned output. A ﬂag in the I²C-bus status byte reﬂects whether a load is applied or

not. In addition, an automatic sense mode can be activated which indicates a 75 Ω load at

any of the three outputs at the dedicated interrupt pin TVD.

If the SAA7104E; SAA7105E is required to drive a second (auxiliary) VGA monitor or an

HDTV set, the DACs receive the signal coming from the HD data path. In this event, the

DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in

the video encoder.

7.15 HD data path

This data path allows the SAA7104E; SAA7105E to be used with VGA or HDTV monitors.

It receives its data directly from the cursor generator and supports RGB and Y-P_B-P_R

output formats (RGB not with Y-P_B-P_Rinput formats). No scaling is done in this mode.

A gain adjustment either leads the full level swing to the digital-to-analog converters or

reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the

signal as it is required for display units expecting signals with sync pulses, either regular or

3-level syncs.

7.16 Timing generator

The synchronization of the SAA7104E; SAA7105E is able to operate in two modes; Slave

mode and Master mode.

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In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync),

VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can

be programmed. The frame sync signal is only necessary when the input signal is

interlaced, in other cases it may be omitted. If the frame sync signal is present, it is

possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS

bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the

pins to output mode.

Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data

stream via PD7 to PD0.

Only vertical frequencies of 50 Hz and 60 Hz are allowed with the SAA7104E;

SAA7105E. In Slave mode, it is not possible to lock the encoders color carrier to the line

frequency with the PHRES bits.

In the (more common) Master mode, the time base of the circuit is continuously

free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC,

a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these

signals are deﬁned in the PIXCLK domain. The duration of HSVGC and VSVGC are ﬁxed,

they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and

the polarities can be programmed.

The input line length can be programmed. The ﬁeld length is always derived from the ﬁeld

length of the encoder and the pixel clock frequency that is being used.

CBO acts as a data request signal. The circuit accepts input data at a programmable

number of clocks after CBO goes active. This signal is programmable and it is possible to

adjust the following (see Figure 13 and Figure 14):

• The horizontal offset

• The length of the active part of the line

• The distance from active start to ﬁrst expected data

• The vertical offset separately for odd and even ﬁelds

• The number of lines per input ﬁeld

In most cases, the vertical offsets for odd and even ﬁelds are equal. If they are not, then

the even ﬁeld will start later. The SAA7104E; SAA7105E will also request the ﬁrst input

lines in the even ﬁeld, the total number of requested lines will increase by the difference of

the offsets.

As stated above, the circuit can be programmed to accept the look-up and cursor data in

the ﬁrst 2 lines of each ﬁeld. The timing generator provides normal data request pulses for

these lines; the duration is the same as for regular lines. The additional request pulses will

be suppressed with LUTL set to logic 0; see Table 103. The other vertical timings do not

change in this case, so the ﬁrst active line can be number 2, counted from 0.

7.17 Pattern generator for HD sync pulses

The pattern generator provides appropriate synchronization patterns for the video data

path in auxiliary monitor or HDTV mode. It provides maximum ﬂexibility in terms of raster

generation for all interlaced and non-interlaced computer graphics or ATSC formats. The

sync engine is capable of providing a combination of event-value pairs which can be used

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to insert certain values in the outgoing data stream at speciﬁed times. It can also be used

to generate digital signals associated with time events. These can be used as digital

horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM.

The picture position is adjustable through the programmable relationship between the

sync pulses and the video contents.

The generation of embedded analog sync pulses is bound to a number of events which

can be deﬁned for a line. Several of these line timing deﬁnitions can exist in parallel. For

the ﬁnal sync raster composition a certain sequence of lines with different sync event

properties has to be deﬁned. The sequence speciﬁes a series of line types and the

number of occurrences of this speciﬁc line type. Once the sequence has been completed,

it restarts from the beginning. All pulse shapes are ﬁltered internally in order to avoid

ringing after analog post ﬁlters.

The sequence of the generated pulse stream must ﬁt precisely to the incoming data

stream in terms of the total number of pixels per line and lines per frame.

The sync engines ﬂexibility is achieved by using a sequence of linked lists carrying the

properties for the image, the lines as well as fractions of lines. Figure 3 illustrates the

context between the various tables.

4-bit line type index

10-bit line count

line

count

pointer

LINE COUNT ARRAY

16 entries

line type pointer

3

pattern pointer

LINE TYPE ARRAY

15 entries

3

event type pointer

10-bit duration

4-bit value index

10-bit duration

4-bit value index

LINE PATTERN ARRAY

7 entries

8 + 2-bit value

VALUE ARRAY

8 entries

line pattern pointer

mhc573

Fig 3. Context between the pattern generator tables for DH sync pulses

The ﬁrst table serves as an array to hold the correct sequence of lines that compose the

synchronization raster; it can contain up to 16 entries. Each entry holds a 4-bit index to

the next table and a 10-bit counter value which speciﬁes how often this particular line is

invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use

two table entries.

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The 4-bit index in the line count array points to the line type array. It holds up to 15 entries

(index 0 is not used), index 1 points to the ﬁrst entry, index 2 to the second entry of the line

type array etc.

Each entry of the line type array can hold up to 8 index pointers to another table. These

indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync,

a blank, and an active portion followed by another blank portion, occupying four entries in

one table line.

Each index of this table points to a particular line of the next table in the linked list. This

table is called the line pattern array and each of the up to seven entries stores up to four

pairs of a duration in pixel clock cycles and an index to a value table. The table entries are

used to deﬁne portions of a line representing a certain value for a certain number of clock

cycles.

The value speciﬁed in this table is actually another 3-bit index into a value array which can

hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into

the G or Y signal, only; if bit 4 = 0, the associated value is inserted into all three signals.

Two additional bits of the entries in the value array (LSBs of the second byte) determine if

the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs.

To ease the trigger set-up for the sync generation module, a set of registers is provided to

set up the screen raster which is deﬁned as width and height. A trigger position can be

speciﬁed as an x, y co-ordinate within the overall dimensions of the screen raster. If the

x, y counter matches the speciﬁed co-ordinates, a trigger pulse is generated which

pre-loads the tables with their initial values.

The listing in Table 9 outlines an example on how to set up the sync tables for a 1080i HD

raster.

Important note:

Due to a problem in the programming interface, writing to the line pattern array

(address D2) might destroy the data of the line type array (address D1). A work around is

to write the line pattern array data before writing the line type array. Reading of the arrays

is possible but all address pointers must be initialized before the next write operation.

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Table 9:

Example for set-up of the sync tables

Comment

Sequence

Write to subaddress D0h

00

points to ﬁrst entry of line count array (index 0)

05 20

generate 5 lines of line type index 2 (this is the second entry of the line type array); will be the

ﬁrst vertical raster pulse

01 40

generate 1 line of line type index 4; will be sync-black-sync-black sequence after the ﬁrst vertical

pulse

0E 60

1C 12

02 60

01 50

generate 14 lines of line type index 6; will be the following lines with sync-black sequence

generate 540 lines of line type index 1; will be lines with sync and active video

generate 2 lines of line type index 6; will be the following lines with sync-black sequence

generate 1 line of line type index 5; will be the following line (line 563) with

sync-black-sync-black-null sequence (null is equivalent to sync tip)

04 20

01 30

0F 60

1C 12

02 60

generate 4 lines of line type index 2; will be the second vertical raster pulse

generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence

generate 15 lines of line type index 6; will be the following lines with sync-black sequence

generate 540 lines of line type index 1; will be lines with sync and active video

generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now,

1125 lines are deﬁned

Write to subaddress D2h (insertion is done into all three analog output signals)

00 points to ﬁrst entry of line pattern array (index 1)

6F 33 2B 30 00 00 00 00 880 × value(3) + 44 × value(3); (subtract 1 from real duration)

6F 43 2B 30 00 00 00 00 880 × value(4) + 44 × value(3)

3B 30 BF 03 BF 03 2B 30 60 × value(3) + 960 × value(0) + 960 × value(0) + 44 × value(3)

2B 10 2B 20 57 30 00 00 44 × value(1) + 44 × value(2) + 88 × value(3)

3B 30 BF 33 BF 33 2B 30 60 × value(3) + 960 × value(3) + 960 × value(3) + 44 × value(3)

Write to subaddress D1h

00

points to ﬁrst entry of line type array (index 1)

34 00 00 00

24 24 00 00

24 14 00 00

14 14 00 00

14 24 00 00

54 00 00 00

use pattern entries 4 and 3 in this sequence (for sync and active video)

use pattern entries 4, 2, 4 and 2 in this sequence (for 2 × sync-black-null-black)

use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null)

use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black)

use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null)

use pattern entries 4 and 5 in this sequence (for sync-black)

Write to subaddress D3h (no signals are directed to pins HSM_CSYNC and VSM)

00

points to ﬁrst entry of value array (index 0)

black level, to be added during active video

sync level LOW (minimum output voltage)

sync level HIGH (3-level sync)

CC 00

80 00

0A 00

CC 00

black level (needed elsewhere)

80 00

null (identical to sync level LOW)

Write to subaddress DCh

0B

insertion is active, gain for signal is adapted accordingly

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7.18 I²C-bus interface

The I²C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses

and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an

auto-increment function. All registers are write and read, except two read only status

bytes.

The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and

control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is

assigned to one address. Thus a write access needs the LUT address and three data

bytes following subaddress FFh. For further write access auto-incrementing of the LUT

address is performed. The cursor bit map access is similar to the LUT access but contains

only a single byte per address.

The I²C-bus slave address is deﬁned as 88h.

7.19 Power-down modes

In order to reduce the power consumption, the SAA7104E; SAA7105E supports

2 Power-down modes, accessible via the I²C-bus. The analog Power-down mode

(DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer.

The digital Power-down mode (DOWND = 1) turns off all internal clocks and sets the

digital outputs to LOW except the I²C-bus interface. The IC keeps its programming and

can still be accessed in this mode, however not all registers can be read or written to.

Reading or writing to the look-up tables, the cursor and the HD sync generator require a

valid pixel clock. The typical supply current in full power-down is approximately 5 mA.

Because the analog Power-down mode turns off the pixel clock synthesizer, there are

limitations in some applications. If there is no pixel clock, the IC is not able to set its

outputs to LOW. So, in most cases, DOWNA and DOWND should be set to logic 1

simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.

7.20 Programming the SAA7104E; SAA7105E

The SAA7104E; SAA7105E needs to provide a continuous data stream at its analog

outputs as well as receive a continuous stream of data from its data source. Because

there is no frame memory isolating the data streams, restrictions apply to the input frame

timings.

Input and output processing of the SAA7104E; SAA7105E are only coupled through the

vertical frequencies. In Master mode, the encoder provides a vertical sync and an

odd/even pulse to the input processing. In Slave mode, the encoder receives them.

The parameters of the input ﬁeld are mainly given by the memory capacity of the

SAA7104E; SAA7105E. The rule is that the scaler and thus the input processing needs to

provide the video data in the same time frames as the encoder reads them. Therefore, the

vertical active video times (and the vertical frequencies) need to be the same.

The second rule is that there has to be data in the buffer FIFO when the encoder enters

the active video area. Therefore, the vertical offset in the input path needs to be a bit

shorter than the offset of the encoder.

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The following Sections give the set of equations required to program the IC for the most

common application: A post processor in Master mode with non-interlaced video input

data.

Some variables are deﬁned below:

• InPix: the number of active pixels per input line

• InPpl: the length of the entire input line in pixel clocks

• InLin: the number of active lines per input ﬁeld/frame

• TPclk: the pixel clock period

• RiePclk: the ratio of internal to external pixel clock

• OutPix: the number of active pixels per output line

• OutLin: the number of active lines per output ﬁeld

• TXclk: the encoder clock period (37.037 ns)

7.20.1 TV display window

At 60 Hz, the ﬁrst visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the

index is 284, 702 pixels can be visible.

The output lines should be centred on the screen. It should be noted that the encoder has

2 clocks per pixel; see Table 47.

ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz);

ADWHE = ADWHS + OutPix × 2 (all frequencies)

For vertical, the procedure is the same. At 60 Hz, the ﬁrst line with video information is

number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 55

to Table 57.

240 – OutLin

-------------------------------

2

287 – OutLin

-------------------------------

2

FAL = 19 +

(60 Hz); FAL = 23 +

(50 Hz);

LAL = FAL + OutLin (all frequencies)

Most TV sets use overscan, and not all pixels respectively lines are visible. There is no

standard for the factor, it is highly recommended to make the number of output pixels and

lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output

pixels per line.

7.20.2 Input frame and pixel clock

The total number of pixel clocks per line and the input horizontal offset need to be chosen

next. The only constraint is that the horizontal blanking has at least 10 clock pulses.

The required pixel clock frequency can be determined in the following way: Due to the

limited internal FIFO size, the input path has to provide all pixels in the same time frame

as the encoders vertical active time. The scaler also has to process the ﬁrst and last

border lines for the anti-ﬂicker function. Thus:

262.5 × 1716 × TXclk

TPclk =

(60 Hz)

-----------------------------------------------------------------------------------

InLin + 2

InPpl × integer

× 262.5

----------------------

OutLin

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312.5 × 1728 × TXclk

TPclk =

(50 Hz) and for the pixel clock generator

-----------------------------------------------------------------------------------

InLin + 2

InPpl × integer

× 312.5

----------------------

OutLin

TXclk

20 + PCLE

PCL =

× 2

(all frequencies); see Table 59 and Table 60. The divider PCLE

--------------

TPclk

should be set according to Table 60. PCLI may be set to a lower or the same value.

Setting a lower value means that the internal pixel clock is higher and the data get

sampled up. The difference may be 1 at 640 × 480 pixels resolution and 2 at resolutions

with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum

factor of 2 respectively 4 (this is the parameter RiePclk).

logRiePclk

PCLI = PCLE –

(all frequencies)

--------------------------

log2

The equations ensure that the last line of the ﬁeld has the full number of clock cycles.

Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure

that there is not even a fraction of a clock left at the end of the ﬁeld.

7.20.3 Horizontal scaler

XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulﬁlled.

Values given by the VESA display timings are preferred.

HLEN = InPpl × RiePclk − 1

InPix

2

XPIX =

XINC =

× RiePclk

------------

OutPix

4096

×

---------------- ------------------

InPix RiePclk

XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.

7.20.4 Vertical scaler

The input vertical offset can be taken from the assumption that the scaler should just have

ﬁnished writing the ﬁrst line when the encoder starts reading it:

FAL × 1716 × TXclk

---------------------------------------------------

InPpl × TPclk

FAL × 1728 × TXclk

---------------------------------------------------

InPpl × TPclk

YOFS =

– 2.5 (60 Hz) YOFS =

– 2.5 (50 Hz)

In most cases the vertical offsets will be the same for odd and even ﬁelds. The results

should be rounded down.

YPIX = InLin

YSKIP deﬁnes the anti-ﬂicker function. 0 means maximum ﬂicker reduction but minimum

vertical bandwidth, 4095 gives no ﬂicker reduction and maximum bandwidth. Note that the

maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to

fulﬁl this requirement.

OutLin

----------------------

InLin + 2

YSKIP

----------------

4095

YINC =

× 1 +

× 4096

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YINC

--------------

2

YIWGTO =

+ 2048

YINC – YSKIP

-------------------------------------

2

YIWGTE =

When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not

be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added

and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE

positive.

It should be noted that these equations assume that the input is non-interlaced but the

output is interlaced. If the input is interlaced, the initial weighting factors need to be

adapted to obtain the proper phase offsets in the output frame.

If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may

be set to logic 1. This extends the maximum vertical scaling factor by a factor of 2. Only

the parameter YINC is affected, it needs to be divided by two to get the same effect.

There are restrictions in this mode:

• The vertical ﬁlter YFILT is not available in this mode; the circuit will ignore this value

• The horizontal blanking needs to be long enough to transfer an output line between

2 memory locations. This is 710 internal pixel clocks.

Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is

also limited to less than 1.5. In this case a normal blanking length is sufﬁcient.

7.21 Input levels and formats

The SAA7104E; SAA7105E accepts digital Y, C_B, C_Ror RGB data with levels (digital

codes) in accordance with ‘ITU-R BT.601’. An optional gain adjustment also allows to

accept data with the full level swing of 0 to 255.

For C and CVBS outputs, deviating amplitudes of the color difference signals can be

compensated for by independent gain control setting, while gain for luminance is set to

predeﬁned values, distinguishable for 7.5 IRE set-up or without set-up.

The RGB, respectively C_R-Y-C_Bpath features an individual gain setting for luminance

(GY) and color difference signals (GCD). Reference levels are measured with a color bar,

100 % white, 100 % amplitude and 100 % saturation.

The SAA7104E; SAA7105E has special input cells for the VGC port. They operate at a

wider supply voltage range and have a strict input threshold at ¹⁄₂V_DDD. To achieve full

speed of these cells, the EIDIV bit needs to be set to logic 1. Note that the impedance of

these cells is approximately 6 kΩ. This may cause trouble with the bootstrapping pins of

some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is

regular in this mode.

SAA7104E_SAA7105E_2

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23 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 10: ‘ITU-R BT.601’ signal component levels

Color

Signals^[1]

Y

C_B

C_R

R

G

B

White

Yellow

Cyan

235

210

170

145

106

81

128

16

128

146

16

235

16

235

16

235

16

166

54

235

16

Green

Magenta

Red

34

16

202

90

222

240

110

128

235

16

235

16

Blue

41

240

128

16

235

16

Black

16

[1] Transformation:

R = Y + 1.3707 × (C_R− 128)

G = Y − 0.3365 × (C_B− 128) − 0.6982 × (C_R− 128)

B = Y + 1.7324 × (C_B− 128).

Table 11: Usage of bits SLOT and EDGE

Data slot control (example for format 0)

SLOT

EDGE

1st data

2nd data

0

1

0

1

0

1

at rising edge G3/Y3

at falling edge G3/Y3

at rising edge R7/C_R7

at falling edge R7/C_R7

at rising edge R7/C_R7

at falling edge G3/Y3

at rising edge G3/Y3

Table 12: Pin assignment for input format 0

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/C_B-Y-C_R

Falling clock edge

G3/Y3

Rising clock edge

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

R2/C_R2

R1/C_R1

R0/C_R0

G7/Y7

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2/Y2

G1/Y1

G0/Y0

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

B2/C_B2

B1/C_B1

B0/C_B0

G6/Y6

G5/Y5

G4/Y4

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SAA7104E; SAA7105E

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Digital video encoder

Table 13: Pin assignment for input format 1

5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB

Falling clock edge

Rising clock edge

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2

G1

G0

B4

B3

B2

B1

B0

X

R4

R3

R2

R1

R0

G4

G3

Table 14: Pin assignment for input format 2

5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB

Falling clock edge

Rising clock edge

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G2

G1

G0

B4

B3

B2

B1

B0

R4

R3

R2

R1

R0

G5

G4

G3

Table 15: Pin assignment for input format 3

8 + 8 + 8-bit 4 : 2 : 2 non-interlaced C_B-Y-C_R

Falling clock

edge n

Rising clock

edge n

Falling clock

Rising clock

edge n + 1

C_R7(0)

C_R6(0)

C_R5(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

C_B7(0)

C_B6(0)

C_B5(0)

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y7(0)

Y6(0)

Y5(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

Y7(1)

Y6(1)

Y5(1)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

Table 16: Pin assignment for input format 4

8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656, 27 MHz clock)

Rising clock

edge n

Rising clock

edge n + 1

Rising clock

edge n + 2

Rising clock

edge n + 3

PD7

PD6

PD5

C_B7(0)

C_B6(0)

C_B5(0)

Y7(0)

Y6(0)

Y5(0)

C_R7(0)

C_R6(0)

C_R5(0)

Y7(1)

Y6(1)

Y5(1)

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Digital video encoder

Table 16: Pin assignment for input format 4…continued

8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656, 27 MHz clock)

Rising clock

edge n

Rising clock

edge n + 1

Rising clock

edge n + 2

Rising clock

edge n + 3

PD4

PD3

PD2

PD1

PD0

C_B4(0)

C_B3(0)

C_B2(0)

C_B1(0)

C_B0(0)

Y4(0)

Y3(0)

Y2(0)

Y1(0)

Y0(0)

C_R4(0)

C_R3(0)

C_R2(0)

C_R1(0)

C_R0(0)

Y4(1)

Y3(1)

Y2(1)

Y1(1)

Y0(1)

Table 17: Pin assignment for input format 5^[1]

8-bit non-interlaced index color

Falling clock edge

Rising clock edge

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

X

INDEX7

INDEX6

INDEX5

INDEX4

INDEX3

INDEX2

INDEX1

INDEX0

[1] X = don’t care.

Table 18: Pin assignment for input format 6

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB/C_B-Y-C_R

Falling clock edge

G4/Y4

Rising clock edge

R7/C_R7

R6/C_R6

R5/C_R5

R4/C_R4

R3/C_R3

G7/Y7

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

G3/Y3

G2/Y2

B7/C_B7

B6/C_B6

B5/C_B5

B4/C_B4

B3/C_B3

G0/Y0

G6/Y6

G5/Y5

R2/C_R2

R1/C_R1

R0/C_R0

G1/Y1

B2/C_B2

B1/C_B1

B0/C_B0

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Digital video encoder

8.2 I²C-bus format

S

1000 1000

A

SUBADDRESS

A

DATA 0

A

............

DATA n

A

P

001aad411

a. to control registers

1000 1000

A

D0h

A

RAM ADDRESS

A

DATA 00

A

DATA 01

A

............ DATA n

A

P

001aad412

b. to the HD line count array (subaddress D0h)

1000 1000

A

FEh

A

RAM ADDRESS

A

DATA 0

A

............

DATA n

A

P

001aad413

c. to cursor bit map (subaddress FEh)

1000 1000

A

FFh

A

RAM ADDRESS

A

DATA 0R

A

DATA 0G

A

DATA 0B

A

............

P

001aad414

d. to color look-up table (subaddress FFh)

See Table 20 for explanations.

Fig 4. I²C-bus write access

S

1000 1000

A

SUBADDRESS

A

Sr 1000 1001

A

DATA 0

Am ............ DATA n Am

P

001aad415

a. to control registers

FEh

S

1000 1000

A

RAM ADDRESS

A

Sr 1000 1001

A

DATA 0 Am .......... DATA n Am

P

or

FFh

001aad416

b. to cursor bit map or color LUT

See Table 20 for explanations.

Fig 5. I²C-bus read access

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Digital video encoder

Table 20: Explanations of Figure 4 and Figure 5

Code

Description

S

START condition

Sr

repeated START condition

slave address

1000 100X^[1]

A

acknowledge generated by the slave

acknowledge generated by the master

subaddress byte

Am

SUBADDRESS^[2]

DATA

data byte

--------

continued data bytes and acknowledges

STOP condition

P

RAM ADDRESS

start address for RAM access

[1] X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.

[2] If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

8.3 Slave receiver

Table 21: Common DAC adjust ﬁne register, subaddress 16h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 4 -

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

3 to 0 DACF[3:0] R/W

DAC ﬁne output voltage adjustment, 1 % steps for all DACs

0111 7 %

0110 6 %

0101 5 %

0100 4 %

0011 3 %

0010 2 %

0001 1 %

0000* 0 %

1000 0 %

1001 −1 %

1010 −2 %

1011 −3 %

1100 −4 %

1101 −5 %

1110 −6 %

1111 −7 %

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Digital video encoder

Table 22: RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description

Subaddress Bit

Symbol

Description

17h to 19h

7 to 5 -

must be programmed with logic 0 to ensure compatibility to

future enhancements

17h

4 to 0 RDACC[4:0] output level coarse adjustment for RED DAC; default after

reset is 1Bh for output of C signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

18h

19h

4 to 0 GDACC[4:0] output level coarse adjustment for GREEN DAC; default after

reset is 1Bh for output of VBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

4 to 0 BDACC[4:0] output level coarse adjustment for BLUE DAC; default after

reset is 1Fh for output of CVBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

Table 23: MSM threshold, subaddress 1Ah, bit description

Bit Symbol Description

7 to 0 MSMT[7:0] monitor sense mode threshold for DAC output voltage, should be set to 70h

Table 24: Monitor sense mode register, subaddress 1Bh, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

MSM

MSA

R/W

monitor sense mode

0*

1

off; RCOMP, GCOMP and BCOMP bits are not valid

on

6

5

automatic monitor sense mode

off; RCOMP, GCOMP and BCOMP bits are not valid

on if MSM = 0

0*

1

MSOE

R/W

0

pin TVD is active

1*

0

pin TVD is 3-state

4 and 3 -

must be programmed with logic 0 to ensure compatibility to

future enhancements

2

1

0

RCOMP R

check comparator at DAC on pin RED_CR_C_CVBS

active, output is loaded

0

1

inactive, output is not loaded

GCOMP R

check comparator at DAC on pin GREEN_VBS_CVBS

active, output is loaded

0

1

inactive, output is not loaded

BCOMP

R

check comparator at DAC on pin BLUE_CB_CVBS

active, output is loaded

0

1

inactive, output is not loaded

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Digital video encoder

Table 25: Wide screen signal registers, subaddresses 26h and 27h, bit description

Legend: * = default value after reset.

Subaddress Bit

Symbol

Access Value Description

27h

7

6

WSSON

R/W

0*

1

wide screen signalling output is disabled

wide screen signalling output is enabled

-

0

must be programmed with logic 0 to ensure

compatibility to future enhancements

5 to 3 WSS[13:11] R/W

2 to 0 WSS[10:8] R/W

-

wide screen signalling bits, reserved

wide screen signalling bits, subtitles

26h

7 to 4 WSS[7:4]

R/W

wide screen signalling bits, enhanced

services

3 to 0 WSS[3:0]

R/W

-

wide screen signalling bits, aspect ratio

Table 26: Real-time control and burst start register, subaddress 28h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 and 6 -

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0

BS[5:0] R/W

starting point of burst in clock cycles

21h* PAL: BS = 33; strapping pin FSVGC tied to HIGH

19h* NTSC: BS = 25; strapping pin FSVGC tied to LOW

Table 27: Sync reset enable and burst end register, subaddress 29h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

SRES

R/W

0*

1

pin TTX_SRES accepts a teletext bit stream (TTX)

pin TTX_SRES accepts a sync reset input (SRES); a HIGH

impulse resets synchronization of the encoder (ﬁrst ﬁeld, ﬁrst

line)

6

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0

BE[5:0] R/W

ending point of burst in clock cycles

1Dh* PAL: BE = 29; strapping pin FSVGC tied to HIGH

1Dh* NTSC: BE = 29; strapping pin FSVGC tied to LOW

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Digital video encoder

Table 28: Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit

description

Legend: * = default value after reset.

Subaddress Bit

Symbol

Access Value Description

2Ch

7

CGEN

R/W

copy generation data output

0*

1

disabled

enabled

6 to 4 -

R/W

0

must be programmed with logic 0 to ensure

compatibility to future enhancements

3 to 0 CG[19:16] R/W

7 to 0 CG[15:8]

-

LSBs of the respective bytes are encoded

immediately after run-in, the MSBs of the

respective bytes have to carry the CRCC bits,

in accordance with the deﬁnition of copy

generation management system encoding

format.

2Bh

2Ah

7 to 0 CG[7:0]

Table 29: Output port control register, subaddress 2Dh, bit description

Legend: * = default value after reset.

Bit Symbol

Access Value Description

R/W pin GREEN_VBS_CVBS provides a

7

VBSEN

0

component GREEN signal (CVBSEN1 = 0) or CVBS signal

(CVBSEN1 = 1)

1*

luminance (VBS) signal

6

5

4

3

CVBSEN1 R/W

CVBSEN0 R/W

pin GREEN_VBS_CVBS provides a

component GREEN (G) or luminance (VBS) signal

CVBS signal

0*

1

pin BLUE_CB_CVBS provides a

component BLUE (B) or color difference BLUE (C_B) signal

CVBS signal

0

1*

CEN

R/W

pin RED_CR_C_CVBS provides a

component RED (R) or color difference RED (C_R) signal

chrominance signal (C) as modulated subcarrier for S-video

encoder

0

1*

ENCOFF R/W

0*

1

active

bypass, DACs are provided with RGB signal after cursor

insertion block

2

1

0

CLK2EN

R/W

pin TTXRQ_XCLKO2 provides

teletext request signal (TTXRQ)

buffered crystal clock divided by two (13.5 MHz)

pin RED_CR_C_CVBS provides a

signal according to CEN

0

1*

CVBSEN2 R/W

0*

1

CVBS signal

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

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Digital video encoder

Table 30: Input path control register, subaddress 37h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

6

YUPSC R/W

vertical scaler

0*

1

normal operation

upscaling is enabled

5 and 4 YFIL[1:0] R/W

vertical interpolation ﬁlter control; the ﬁlter is not available if

YUPSC = 1

00*

01

no ﬁlter active

ﬁlter is inserted before vertical scaling

10

ﬁlter is inserted after vertical scaling; YSKIP should be

logic 0

11

0

reserved

3

2

-

R/W

must be programmed with logic 0 to ensure compatibility to

future enhancements

CZOOM R/W

cursor generator

0*

1

normal operation

cursor will be zoomed by a factor of 2 in both directions

expected input level swing is

16 to 235 (8-bit RGB)

1

0

IGAIN

XINT

R/W

0*

1

0 to 255 (8-bit RGB)

interpolation ﬁlter for horizontal upscaling

not active

0*

1

active

Table 31: Gain luminance for RGB register, subaddress 38h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 to 5

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

4 to 0

GY[4:0] R/W

-

Gain luminance of RGB (C_R, Yand C_B) output, ranging from

(1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂). Suggested nominal value = 0,

depending on external application.

Table 32: Gain color difference for RGB register, subaddress 39h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 to 5

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

4 to 0

GCD[4:0] R/W

-

Gain color difference of RGB (C_R, Yand C_B) output, ranging

from (1 − ¹⁶⁄₃₂) to (1 + ¹⁵⁄₃₂). Suggested nominal value = 0,

depending on external application.

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Digital video encoder

Table 33: Input port control 1 register, subaddress 3Ah, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7

CBENB R/W

0

1

0

data from input ports is encoded

color bar with ﬁxed colors is encoded

6

5

-

R/W

must be programmed with logic 0 to ensure compatibility to

future enhancements

SYNTV

in Slave mode

0*

1

the encoder is only synchronized at the beginning of an odd

ﬁeld

the encoder receives a vertical sync signal

horizontal and vertical trigger

taken from FSVGC or both VSVGC and HSVGC

decoded out of ‘ITU-R BT.656’ compatible data at PD port

Y-C_B-C_Rto RGB dematrix

4

3

2

SYMP

R/W

0*

1

DEMOFF R/W

CSYNC R/W

0*

1

active

bypassed

pin HSM_CSYNC provides

0

1

horizontal sync for non-interlaced VGA components output

(at PIXCLK)

composite sync for interlaced components output (at XTAL

clock)

1

0

Y2C

R/W

input luminance data

0

twos complement from PD input port

straight binary from PD input port

input color difference data

1*

UV2C

0

twos complement from PD input port

straight binary from PD input port

1*

Table 34: VPS enable, input control 2, subaddress 54h, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

VPSEN R/W video programming system data insertion

7

0*

1

is disabled

in line 16 is enabled

6

5

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

GPVAL R/W

if GPEN = 1, pin VSM provides

LOW level

0

1

HIGH level

4

GPEN R/W

pin VSM provides

0*

1

vertical sync for a monitor

constant signal according to GPVAL

3 and 2 -

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

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Digital video encoder

Table 34: VPS enable, input control 2, subaddress 54h, bit description…continued

Legend: * = default value after reset.

Bit

Symbol Access Value Description

EDGE R/W input data is sampled with

1

0

inverse clock edges

1*

0*

1

the clock edges speciﬁed in Table 12 to Table 18

normal assignment of the input data to the clock edge

0

SLOT

R/W

correct time misalignment due to inverted assignment of input

data to the clock edge

Table 35: VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit

description^[1]

Subaddress Bit

Symbol

Access Value Description

55h

56h

7 to 0 VPS5[7:0] R/W

7 to 0 VPS11[7:0] R/W

-

ﬁfth byte of video programming system data

eleventh byte of video programming system

data

57h

58h

59h

7 to 0 VPS12[7:0] R/W

7 to 0 VPS13[7:0] R/W

7 to 0 VPS14[7:0] R/W

-

twelfth byte of video programming system

data

thirteenth byte of video programming system

data

fourteenth byte of video programming system

data

[1] In line 16; LSB ﬁrst; all other bytes are not relevant for VPS.

Table 36: Chrominance phase register, subaddress 5Ah, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0

CHPS[7:0] R/W

00h* phase of encoded color subcarrier (including burst) relative

to horizontal sync; can be adjusted in steps of

360/256 degrees

6Bh

16h

25h

46h

PAL B/G and data from input ports in Master mode

PAL B/G and data from look-up table

NTSC M and data from input ports in Master mode

NTSC M and data from look-up table

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

39 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 37: Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description

Subaddress Bit

Symbol

Conditions

Remarks

5Bh

5Dh

7 to 0

GAINU[8:0]^[1]

white-to-black = 92.5 IRE

GAINU = 0

GAINU = −2.17 × nominal to +2.16 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

GAINU = −2.05 × nominal to +2.04 × nominal

output subcarrier of U contribution = 0

output subcarrier of U contribution = nominal

7

GAINU = 118 (76h)

white-to-black = 100 IRE

GAINU = 0

GAINU = 125 (7Dh)

6

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

5 to 0

BLCKL[5:0]^[2]

white-to-sync = 140 IRE^[3]recommended value: BLCKL = 58 (3Ah)

BLCKL = 0^[3]

output black level = 29 IRE

BLCKL = 63 (3Fh)^[3]

output black level = 49 IRE

white-to-sync = 143 IRE^[4]recommended value: BLCKL = 51 (33h)

BLCKL = 0^[4]

BLCKL = 63 (3Fh)^[4]

output black level = 27 IRE

output black level = 47 IRE

[1] Variable gain for C_Bsignal; input representation in accordance with ‘ITU-R BT.601’.

[2] Variable black level; input representation in accordance with ‘ITU-R BT.601’.

[3] Output black level/IRE = BLCKL × 2/6.29 + 28.9.

[4] Output black level/IRE = BLCKL × 2/6.18 + 26.5.

Table 38: Gain V and gain V MSB, blanking level registers, subaddresses 5Ch and 5Eh, bit description

Subaddress Bit

Symbol

Conditions

Remarks

5Ch

5Eh

7 to 0

GAINV[8:0]^[1]

white-to-black = 92.5 IRE

GAINV = 0

GAINV = −1.55 × nominal to +1.55 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

GAINV = −1.46 × nominal to +1.46 × nominal

output subcarrier of V contribution = 0

output subcarrier of V contribution = nominal

7

GAINV = 165 (A5h)

white-to-black = 100 IRE

GAINV = 0

GAINV = 175 (AFh)

6

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

5 to 0

BLNNL[5:0]^[2]

white-to-sync = 140 IRE^[3]recommended value: BLNNL = 46 (2Eh)

BLNNL = 0^[3]

output blanking level = 25 IRE

BLNNL = 63 (3Fh)^[3]

output blanking level = 45 IRE

white-to-sync = 143 IRE^[4]recommended value: BLNNL = 53 (35h)

BLNNL = 0^[4]

BLNNL = 63 (3Fh)^[4]

output blanking level = 26 IRE

output blanking level = 46 IRE

[1] Variable gain for C_Rsignal; input representation in accordance with ‘ITU-R BT.601’.

[2] Variable blanking level.

[3] Output black level/IRE = BLNNL × 2/6.29 + 25.4.

[4] Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35h.

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

40 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 39: CCR and blanking level VBI register, subaddress 5Fh, bit description

Bit Symbol Access Value Description

7 and 6 CCRS[1:0] R/W

select cross-color reduction ﬁlter in luminance; for overall

transfer characteristic of luminance see Figure 8

00

01

10

11

-

no cross-color reduction

cross-color reduction #1 active

cross-color reduction #2 active

cross-color reduction #3 active

5 to 0

BLNVB[5:0] R/W

variable blanking level during vertical blanking interval is

typically identical to value of BLNNL

Table 40: Standard control register, subaddress 61h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

DOWND

R/W

digital core

0*

1

in normal operational mode

in Sleep mode and is reactivated with an I²C-bus address

DACs

6

5

4

DOWNA

INPI

0*

1

in normal operational mode

in Power-down mode

PAL switch

0*

1

phase is nominal

is inverted compared to nominal if RTCE = 1

luminance gain for white − black

100 IRE

YGS

0

1

0

92.5 IRE including 7.5 IRE set-up of black

3

2

-

R/W

must be programmed with logic 0 to ensure compatibility

to future enhancements

SCBW

bandwidth for chrominance encoding (for overall transfer

characteristic of chrominance in baseband representation

see Figure 6 and Figure 7)

0

enlarged

1*

standard

1

0

PAL

R/W

encoding

0

1

NTSC (non-alternating V component)

PAL (alternating V component)

FISE

total pixel clocks per line

0

1

864

858

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

41 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 41: Burst amplitude register, subaddress 62h, bit description

Legend: * = default value after reset, ^ = recommended value.

Bit

Symbol Access Value Description

7

RTCE

R/W

real-time control

0*

1

no real-time control of generated subcarrier frequency

real-time control of generated subcarrier frequency through a

Philips video decoder; for a speciﬁcation of the RTC protocol

see document ‘RTC Functional Description’, available on

request

6 to 0 BSTA[6:0] R/W

amplitude of color burst; input representation in accordance

with ‘ITU-R BT.601’

3Fh

white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding;

(63)^ BSTA = 0 to 2.02 × nominal

2Dh white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding;

(45)^ BSTA = 0 to 2.82 × nominal

43h

white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding;

(67)^ BSTA = 0 to 1.90 × nominal

2Fh white-to-black = 100 IRE; burst = 43 IRE; PAL encoding;

(47)*^ BSTA = 0 to 3.02 × nominal

Table 42: Subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description

Subaddress Bit Symbol Access Value Description

66h

65h

64h

63h

7 to 0 FSC[31:24] R/W

7 to 0 FSC[23:16] R/W

7 to 0 FSC[15:08] R/W

7 to 0 FSC[07:00] R/W

-

f_fsc= subcarrier frequency (in multiples of line

frequency); f_llc= clock frequency (in multiples

of line frequency); FSC[31:24] = most

signiﬁcant byte; FSC[07:00] = least signiﬁcant

byte^[1]

f

32

fsc

[1] FSC = round

× 2

---------

f

llc

Examples:

a) NTSC M: f_fsc= 227.5, f_llc= 1716 → FSC = 569408543 (21F0 7C1Fh).

b) PAL B/G: f_fsc= 283.7516, f_llc= 1728 → FSC = 705268427 (2A09 8ACBh).

Table 43: Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit

description^[1]

Subaddress Bit

Symbol

Access Value Description

67h

68h

69h

6Ah

7 to 0 L21O[07:00] R/W

7 to 0 L21O[17:10] R/W

7 to 0 L21E[07:00] R/W

7 to 0 L21E[17:10] R/W

-

ﬁrst byte of captioning data, odd ﬁeld

second byte of captioning data, odd ﬁeld

ﬁrst byte of extended data, even ﬁeld

second byte of extended data, even ﬁeld

[1] LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the

respective bytes have to carry the parity bit, in accordance with the deﬁnition of line 21 encoding format.

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

42 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 44: Trigger control registers, subaddresses 6Ch and 6Dh, bit description

Legend: * = default value after reset.

Subaddress Bit Symbol

Access Value Description

6Ch

6Dh

7 to 0 HTRIG[7:0] R/W

7 to 5 HTRIG[10:8] R/W

4 to 0 VTRIG[4:0] R/W

00h* sets the horizontal trigger phase related to

chip-internal horizontal input^[1]

0h*

00h* sets the vertical trigger phase related to

chip-internal vertical input^[2]

[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of

all internally generated timing signals.

[2] Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;

variation range of VTRIG = 0 to 31 (1Fh).

Table 45: Multi control register, subaddress 6Eh, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

NVTRIG

R/W

values of the VTRIG register are

0

positive

1

negative

6

BLCKON

0*

1

encoder in normal operation mode

output signal is forced to blanking level

5 and 4 PHRES[1:0] R/W

selects the phase reset mode of the color subcarrier

generator

00

01

10

11

no subcarrier reset

subcarrier reset every two lines

subcarrier reset every eight ﬁelds

subcarrier reset every four ﬁelds

3 and 2 LDEL[1:0]

R/W

selects the delay on luminance path with reference to

chrominance path

00*

01

10

11

no luminance delay

1 LLC luminance delay

2 LLC luminance delay

3 LLC luminance delay

ﬁeld length control

1 and 0 FLC[1:0]

00*

01

10

11

interlaced 312.5 lines/ﬁeld at 50 Hz, 262.5 lines/ﬁeld at

60 Hz

non-interlaced 312 lines/ﬁeld at 50 Hz, 262 lines/ﬁeld at

60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at

60 Hz

non-interlaced 313 lines/ﬁeld at 50 Hz, 263 lines/ﬁeld at

60 Hz

SAA7104E_SAA7105E_2

Product data sheet

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43 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 46: Closed caption, teletext enable register, subaddress 6Fh, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 and 6 CCEN[1:0] R/W

enables individual line 21 encoding

line 21 encoding off

00*

01

10

11

enables encoding in ﬁeld 1 (odd)

enables encoding in ﬁeld 2 (even)

enables encoding in both ﬁelds

teletext insertion

5

TTXEN

R/W

0*

1

-

disabled

enabled

4 to 0

SCCLN[4:0] R/W

selects the actual line, where closed caption or extended

data are encoded; line = (SCCLN + 4) for M-systems;

line = (SCCLN + 1) for other systems

Table 47: Active Display Window Horizontal (ADWH) start and end registers,

subaddresses 70h to 72h, bit description

Subaddress Bit

Symbol

Access Value Description

70h

71h

72h

7 to 0 ADWHS[7:0] R/W

-

active display window horizontal start;

deﬁnes the start of the active TV display

portion after the border color ^[1]

7 to 0 ADWHE[7:0] R/W

-

active display window horizontal end;

deﬁnes the end of the active TV display

portion before the border color^[1]

7

-

R/W

0

-

must be programmed with logic 0 to ensure

compatibility to future enhancements

6 to 4 ADWHE[10:8] R/W

active display window horizontal end;

deﬁnes the end of the active TV display

portion before the border color^[1]

3

-

R/W

0

-

must be programmed with logic 0 to ensure

compatibility to future enhancements

2 to 0 ADWHS[10:8] R/W

active display window horizontal start;

deﬁnes the start of the active TV display

portion after the border color ^[1]

[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.

Table 48: TTX request horizontal start register, subaddress 73h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0

TTXHS[7:0] R/W

start of signal TTXRQ on pin TTXRQ_XCLKO2

(CLK2EN = 0); see Figure 15

42h* if strapped to PAL

54h* if strapped to NTSC

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

44 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 49: TTX request horizontal delay register, subaddress 74h, bit description

Legend: * = default value after reset and minimum value.

Bit

Symbol

Access Value Description

7 to 4 -

R/W

0h

must be programmed with logic 0 to ensure compatibility

to future enhancements

3 to 0 TTXHD[3:0] R/W

2h*

indicates the delay in clock cycles between rising edge of

TTXRQ output signal on pin TTXRQ_XCLKO2

(CLK2EN = 0) and valid data at pin TTX_SRES

Table 50: CSYNC advance register, subaddress 75h, bit description

Bit Symbol Access Value Description

7 to 3 CSYNCA[4:0] R/W

-

advanced composite sync against RGB output from

0 XTAL clocks to 31 XTAL clocks

2 to 0 -

R/W

000

must be programmed with logic 0 to ensure compatibility

to future enhancements

Table 51: TTX odd request vertical start register, subaddress 76h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXOVS[7:0] R/W

with TTXOVS8 (see Table 57) ﬁrst line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

odd ﬁeld, line = (TTXOVS + 4) for M-systems and

line = (TTXOVS + 1) for other systems

05h* if strapped to PAL

06h* if strapped to NTSC

Table 52: TTX odd request vertical end register, subaddress 77h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXOVE[7:0] R/W

with TTXOVE8 (see Table 57) last line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

odd ﬁeld, line = (TTXOVE + 3) for M-systems and

line = TTXOVE for other systems

16h* if strapped to PAL

10h* if strapped to NTSC

Table 53: TTX even request vertical start register, subaddress 78h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXEVS[7:0] R/W

with TTXEVS8 (see Table 57) ﬁrst line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

even ﬁeld, line = (TTXEVS + 4) for M-systems and

line = (TTXEVS + 1) for other systems

04h* if strapped to PAL

05h* if strapped to NTSC

SAA7104E_SAA7105E_2

Product data sheet

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45 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 54: TTX even request vertical end register, subaddress 79h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7 to 0 TTXEVE[7:0] R/W

with TTXEVE8 (see Table 57) last line of occurrence of

signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in

even ﬁeld, line = (TTXEVE + 3) for M-systems and

line = TTXEVE for other systems

16h* if strapped to PAL

10h* if strapped to NTSC

Table 55: First active line register, subaddress 7Ah, bit description

Bit Symbol Access Value Description

7 to 0 FAL[7:0] R/W with FAL8 (see Table 57) ﬁrst active line = (FAL + 4) for

M-systems and (FAL + 1) for other systems, measured in

lines

00h

coincides with the ﬁrst ﬁeld synchronization pulse

Table 56: Last active line register, subaddress 7Bh, bit description

Bit Symbol Access Value Description

7 to 0 LAL[7:0] R/W with LAL8 (see Table 57) last active line = (LAL + 3) for

M-systems and LAL for other system, measured in lines

00h

coincides with the ﬁrst ﬁeld synchronization pulse

Table 57: TTX mode, MSB vertical register, subaddress 7Ch, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

TTX60

R/W

0*

1

enables NABTS (FISE = 1) or European TTX (FISE = 0)

enables world standard teletext 60 Hz (FISE = 1)

see Table 56

6

5

LAL8

R/W

TTXO

teletext protocol selected (see Figure 15)

0*

1

new teletext protocol selected; at each rising edge of

TTXRQ a single teletext bit is requested

old teletext protocol selected; the encoder provides a

window of TTXRQ going HIGH; the length of the window

depends on the chosen teletext standard

4

3

2

1

0

FAL8

R/W

see Table 55

see Table 54

see Table 52

see Table 53

see Table 51

TTXEVE8

TTXOVE8

TTXEVS8

TTXOVS8

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

46 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 58: Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description^[1]

Subaddress Bit Symbol Access Value Description

7Eh

7Fh

7 to 0 LINE[12:5] R/W

7 to 0 LINE[20:13] R/W

-

individual lines in both ﬁelds (PAL counting)

can be disabled for insertion of teletext by the

respective bits, disabled line = LINExx (50 Hz

ﬁeld rate)

[1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.

Table 59: Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description

Subaddress Bit

Symbol

Access Value

Description

81h

82h

83h

7 to 0 PCL[07:00] R/W

7 to 0 PCL[15:08]

deﬁnes the frequency of the synthesized

pixel clock PIXCLKO;

PCL

7 to 0 PCL[23:16]

;

× 8

XTAL

f

=

× f

----------

24

PIXCLK

2

f_XTAL= 27 MHz nominal

20 F63Bh 640 × 480 to NTSC M

1B 5A73h 640 × 480 to PAL B/G (as by strapping

pins)

Table 60: Pixel clock control register, subaddress 84h, bit description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

DCLK

R/W

0*

1

set to logic 1

6

5

4

PCLSY

IFRA

pixel clock generator

0*

1

runs free

gets synchronized with the vertical sync

input FIFO gets reset

R/W

0

explicitly at falling edge

every ﬁeld

1*

IFBP

input FIFO

0

active

1*

bypassed

3 and 2 PCLE[1:0] R/W

controls the divider for the external pixel clock

divider ratio for PIXCLK output is 1

divider ratio for PIXCLK output is 2

divider ratio for PIXCLK output is 4

divider ratio for PIXCLK output is 8

controls the divider for the internal pixel clock

divider ratio for internal PIXCLK is 1

divider ratio for internal PIXCLK is 2

divider ratio for internal PIXCLK is 4

not allowed

00

01*

10

11

1 and 0 PCLI[1:0] R/W

00

01*

10

11

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

47 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 61: FIFO control register, subaddress 85h, bit description

Legend: * = default value after reset, ^ = nominal value.

Bit

Symbol Access Value Description

7

EIDIV

-

R/W

0*

DVO compliant signals are applied

1

non-DVO compliant signals are applied

6 to 4

3 to 0

000

must be programmed with logic 0 to ensure compatibility to

future enhancements

FILI[3:0] R/W

8h*^ threshold for FIFO internal transfers

Table 62: Horizontal offset register, subaddress 90h, bit description

Bit

Symbol

Description

7 to 0

XOFS[7:0]

with XOFS[9:8] (see Table 66) horizontal offset; deﬁnes the number of

PIXCLKs from horizontal sync (HSVGC) output to composite blanking

(CBO) output

Table 63: Pixel number register, subaddress 91h, bit description

Bit

Symbol

Description

7 to 0

XPIX[7:0]

with XPIX[9:8] (see Table 66) pixel in X direction; deﬁnes half the number

of active pixels per input line (identical to the length of CBO pulses)

Table 64: Vertical offset odd register, subaddress 92h, bit description

Bit

Symbol

Description

7 to 0

YOFSO[7:0] with YOFSO[9:8] (see Table 66) vertical offset in odd ﬁeld; deﬁnes (in the

odd ﬁeld) the number of lines from VSVGC to ﬁrst line with active CBO; if

no LUT data is requested, the ﬁrst active CBO will be output at

YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme

vertical downscaling and interlacing

Table 65: Vertical offset even register, subaddress 93h, bit description

Bit

Symbol

Description

7 to 0

YOFSE[7:0] with YOFSE[9:8] (see Table 66) vertical offset in even ﬁeld; deﬁnes (in the

even ﬁeld) the number of lines from VSVGC to ﬁrst line with active CBO; if

no LUT data is requested, the ﬁrst active CBO will be output at

YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme

vertical downscaling and interlacing

Table 66: MSBs register, subaddress 94h, bit description

Bit Symbol Description

7 and 6 YOFSE[9:8] see Table 65

5 and 4 YOFSO[9:8] see Table 64

3 and 2 XPIX[9:8]

1 and 0 XOFS[9:8]

see Table 63

see Table 62

Table 67: Line number register, subaddress 95h, bit description

Bit

Symbol

Description

7 to 0

YPIX[7:0]

with YPIX[9:8] (see Table 68) deﬁnes the number of requested input lines

from the feeding device; number of requested

lines = YPIX + YOFSE − YOFSO

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

48 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 68: Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description

Bit

Symbol Access Value Description

7

EFS

R/W

in Slave mode frame sync signal at pin FSVGC

ignored

0

1

accepted

6

5

PCBN

SLAVE

polarity of CBO signal

0

1

normal (HIGH during active video)

inverted (LOW during active video)

from the SAA7104E; SAA7105E the timing to the graphics

controller is

0

1

master

slave

4

3

2

ILC

YFIL

-

R/W

if hardware cursor insertion is active

set LOW for non-interlaced input signals

set HIGH for interlaced input signals

luminance sharpness booster

disabled

0

1

0

1

0

enabled

must be programmed with logic 0 to ensure compatibility to

future enhancements

1 and 0 YPIX[9:8]

see Table 67

Table 69: Sync control register, subaddress 97h, bit description

Bit

Symbol Access Value Description

7

HFS

R/W

horizontal sync is derived from

0

1

input signal (Save mode) at pin HSVGC

a frame sync signal (Slave mode) at pin FSVGC (only if EFS

is set HIGH)

6

VFS

R/W

vertical sync (ﬁeld sync) is derived from

input signal (Slave mode) at pin VSVGC

0

1

a frame sync signal (Slave mode) at pin FSVGC (only if EFS

is set HIGH)

5

4

OFS

PFS

R/W

pin FSVGC is

input

0

1

active output

polarity of signal at pin FSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

3

OVS

R/W

pin VSVGC is

input

0

1

active output

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

49 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 69: Sync control register, subaddress 97h, bit description…continued

Bit

Symbol Access Value Description

2

PVS

R/W

polarity of signal at pin VSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

1

0

OHS

PHS

R/W

pin HSVGC is

input

0

1

active output

polarity of signal at pin HSVGC in output mode (Master

mode) is

0

1

active HIGH; rising edge of the input signal is used in Slave

mode

active LOW; falling edge of the input signal is used in Slave

mode

Table 70: Line length register, subaddress 98h, bit description

Bit Symbol Description

7 to 0 HLEN[7:0] with HLEN[11:8] (see Table 71) horizontal length;

number of PIXCLKs

HLEN =

– 1

-------------------------------------------------

line

Table 71: Input delay, MSB line length register, subaddress 99h, bit description

Bit

Symbol

Description

7 to 4 IDEL[3:0]

input delay; deﬁnes the distance in PIXCLKs between the active edge of

CBO and the ﬁrst received valid pixel

3 to 0 HLEN[11:8] see Table 70

Table 72: Horizontal increment register, subaddress 9Ah, bit description

Bit

Symbol

Description

7 to 0 XINC[7:0]

with XINC[11:8] (see Table 74) incremental fraction of the horizontal scaling

number of output pixels

--------------------------------------------------------

line

engine; XINC =

× 4096

---------------------------------------------------------

number of input pixels

-----------------------------------------------------

line

Table 73: Vertical increment register, subaddress 9Bh, bit description

Bit

Symbol

Description

7 to 0 YINC[7:0]

with YINC[11:8] (see Table 74) incremental fraction of the vertical scaling

number of active output lines

number of active input lines

engine; YINC =

× 4096

---------------------------------------------------------------------

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Product data sheet

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50 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 74: MSBs vertical and horizontal increment register, subaddress 9Ch, bit description

Bit

Symbol

Description

see Table 73

see Table 72

7 to 4

3 to 0

YINC[11:8]

XINC[11:8]

Table 75: Weighting factor odd register, subaddress 9Dh, bit description

Bit

Symbol

Description

7 to 0

YIWGTO[7:0] with YIWGTO[11:8] (see Table 77) weighting factor for the ﬁrst line

YINC

2

of the odd ﬁeld; YIWGTO =

+ 2048

--------------

Table 76: Weighting factor even, subaddress 9Eh, bit description

Bit

Symbol

Description

7 to 0

YIWGTE[7:0] with YIWGTE[11:8] (see Table 77) weighting factor for the ﬁrst line

YINC – YSKIP

of the even ﬁeld; YIWGTE =

-------------------------------------

2

Table 77: Weighting factor MSB register, subaddress 9Fh, bit description

Bit

Symbol

Description

7 to 4

3 to 0

YIWGTE[11:8] see Table 76

YIWGTO[11:8] see Table 75

Table 78: Vertical line skip register, subaddress A0h, bit description

Bit

Symbol

Access Value Description

R/W with YSKIP[11:8] (see Table 79) vertical line skip;

deﬁnes the effectiveness of the anti-ﬂicker ﬁlter

000h most effective

FFFh anti-ﬂicker ﬁlter switched off

7 to 0

YSKIP[7:0]

Table 79: Blank enable for NI-bypass, vertical line skip MSB register, subaddress A1h, bit

description

Legend: * = default value after reset.

Bit

Symbol

Access Value Description

7

BLEN

R/W

for non-interlaced graphics in bypass mode

0*

no internal blanking

1

forced internal blanking

6 to 4

3 to 0

-

R/W

000

must be programmed with logic 0 to ensure

compatibility to future enhancements

YSKIP[11:8]

see Table 78

Table 80: Border color Y register, subaddress A2h, bit description

Bit

Symbol

Description

7 to 0

BCY[7:0]

luminance portion of border color in underscan area

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Digital video encoder

Table 81: Border color U register, subaddress A3h, bit description

Bit

Symbol

Description

color difference portion of border color in underscan area

7 to 0

BCU[7:0]

Table 82: Border color V register, subaddress A4h, bit description

Bit

Symbol

Description

7 to 0

BCV[7:0]

color difference portion of border color in underscan area

Table 83: Subaddress D0h

Data byte

Description

HLCA

RAM start address for the HD sync line count array; the byte following subaddress

D0 points to the ﬁrst cell to be loaded with the next transmitted byte; succeeding cells

are loaded by auto-incrementing until stop condition. Each line count array entry

consists of 2 bytes; see Table 84. The array has 15 entries.

HLC

HLT

HD line counter. The system will repeat the pattern described in ‘HLT’ HLC times and

then start with the next entry in line count array.

HD line type pointer. If not 0, the value points into the line type array, index HLT − 1

with the description of the current line. 0 means the entry is not used.

Table 84: Layout of the data bytes in the line count array

Byte

Description

0

1

HLC7

HLT3

HLC6

HLT2

HLC5

HLT1

HLC4

HLT0

HLC3

0

HLC2

0

HLC1

HLC9

HLC0

HLC8

Table 85: Subaddress D1h

Data byte

Description

HLTA

RAM start address for the HD sync line type array; the byte following subaddress D1

points to the ﬁrst cell to be loaded with the next transmitted byte; succeeding cells

are loaded by auto-incrementing until stop condition. Each line type array entry

consists of 4 bytes; see Table 86. The array has 15 entries.

HLP

HD line type; if not 0, the value points into the line pattern array. The index used is

HLP − 1. It consists of value-duration pairs. Each entry consists of 8 pointers, used

from index 0 to 7. The value 0 means that the entry is not used.

Table 86: Layout of the data bytes in the line type array

Byte

Description

0

1

2

3

0

HLP12

HLP11

HLP31

HLP51

HLP71

HLP10

HLP30

HLP50

HLP70

0

HLP02

HLP22

HLP42

HLP62

HLP01

HLP21

HLP41

HLP61

HLP00

HLP20

HLP40

HLP60

HLP32

HLP52

HLP72

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Digital video encoder

Table 87: Subaddress D2h

Data byte

Description

HLPA

RAM start address for the HD sync line pattern array; the byte following

subaddress D2 points to the ﬁrst cell to be loaded with the next transmitted byte;

succeeding cells are loaded by auto-incrementing until stop condition. Each line

pattern array entry consists of 4 value-duration pairs occupying 2 bytes;

see Table 88. The array has 7 entries.

HPD

HPV

HD pattern duration. The value deﬁnes the time in pixel clocks (HPD + 1) the

corresponding value HPV is added to the HD output signal. If 0, this entry will be

skipped.

HD pattern value pointer. This gives the index in the HD value array containing the

level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value

will only be inserted into the Y/GREEN channel of the HD data path, the other

channels remain unchanged.

Table 88: Layout of the data bytes in the line pattern array

Byte

Description

0

1

2

3

4

5

6

7

HPD07

HPV03

HPD17

HPV13

HPD27

HPV23

HPD37

HPV33

HPD06

HPD05

HPV01

HPD14

HPV11

HPD25

HPV21

HPD35

HPV31

HPD04

HPV00

HPD14

HPV10

HPD24

HPV20

HPD34

HPV30

HPD03

HPD02

HPD01

HPD09

HPD11

HPD19

HPD21

HPD29

HPD31

HPD39

HPD00

HPD08

HPD10

HPD18

HPD20

HPD28

HPD30

HPD38

HPV02

HPD16

HPV12

HPD26

HPV22

HPD36

HPV32

0

HPD13

HPD12

0

HPD23

HPD22

0

HPD33

0

HPD32

0

Table 89: Subaddress D3h

Data byte

Description

HPVA

RAM start address for the HD sync value array; the byte following subaddress D3

points to the ﬁrst cell to be loaded with the next transmitted byte; succeeding cells

are loaded by auto-incrementing until stop condition. Each line pattern array entry

consists of 2 bytes. The array has 8 entries.

HPVE

HHS

HVS

HD pattern value entry. The HD path will insert a level of (HPV + 52) × 0.66 IRE into

the data path. The value is signed 8-bits wide; see Table 90.

HD horizontal sync. If the HD engine is active, this value will be provided at

pin HSM_CSYNC; see Table 90.

HD vertical sync. If the HD engine is active, this value will be provided at pin VSM;

see Table 90.

Table 90: Layout of the data bytes in the value array

Byte

Description

0

1

HPVE7 HPVE6 HPVE5 HPVE4 HPVE3 HPVE2 HPVE1 HPVE0

0

HVS

HHS

Table 91: HD sync trigger state 1 register, subaddress D4h, bit description

Bit Symbol Description

7 to 0 HLCT[7:0] with HLCT[9:8] (see Table 92) state of the HD line counter after trigger (counts

backwards)

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Digital video encoder

Table 92: HD sync trigger state 2 register, subaddress D5h, bit description

Bit

Symbol

Description

7 to 4

HLCPT[3:0] state of the HD line type pointer after trigger

3 and 2 HLPPT[1:0] state of the HD pattern pointer after trigger

1 and 0 HLCT[9:8] see Table 91

Table 93: HD sync trigger state 3 register, subaddress D6h, bit description

Bit

Symbol

Description

7 to 0

HDCT[7:0] with HDCT[9:8] (see Table 94) state of the HD duration counter after trigger

(counts backwards)

Table 94: HD sync trigger state 4 register, subaddress D7h, bit description

Bit

Symbol

Description

7

-

must be programmed with logic 0 to ensure compatibility to future

enhancements

6 to 4

HEPT[2:0] state of the HD event type pointer in the line type array after trigger

3 and 2 -

must be programmed with logic 0 to ensure compatibility to future

enhancements

1 and 0 HDCT[9:8] see Table 93

Table 95: HD sync trigger phase x registers, subaddresses D8h and D9h, bit description

Subaddress Bit

Symbol

Description

D9h

7 to 4 -

must be programmed with logic 0 to ensure compatibility to

future enhancements

3 to 0 HTX[11:8] horizontal trigger phase for the HD sync engine in pixel clocks

7 to 0 HTX[7:0]

D8h

Table 96: HD sync trigger phase y registers, subaddresses DAh and DBh, bit description

Subaddress Bit Symbol Description

must be programmed with logic 0 to ensure compatibility to

future enhancements

1 and 0 HTY[9:8] vertical trigger phase for the HD sync engine in input lines

7 to 0 HTY[7:0]

DBh

DAh

7 to 2

-

Table 97: HD output control register, subaddress DCh, bit description

Legend: * = default value after reset.

Bit

Symbol Access Value Description

7 to 4

-

R/W

0

must be programmed with logic 0 to ensure compatibility to

future enhancements

3

2

HDSYE R/W

HD sync engine

0*

1

off

active

HDTC

R/W

HD output path processes

0*

1

RGB

YUV

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Philips Semiconductors

Digital video encoder

Table 97: HD output control register, subaddress DCh, bit description…continued

Legend: * = default value after reset.

Bit

Symbol Access Value Description

1

HDGY R/W

0*

gain in the HD output path is reduced, insertion of sync pulses

is possible

1

full level swing at the input causes full level swing at the DACs

in HD mode

0

HDIP

R/W

interpolator for the color difference signal in the HD output

path

0*

1

active

off

Table 98: Cursor color 1 R, G and B registers, subaddresses F0h to F2h, bit description

Subaddress Bit Symbol Description

F0h

F1h

F2h

7 to 0

CC1R[7:0] RED portion of ﬁrst cursor color

CC1G[7:0] GREEN portion of ﬁrst cursor color

CC1B[7:0] BLUE portion of ﬁrst cursor color

7 to 0

Table 99: Cursor color 2 R, G and B registers, subaddresses F3h to F5h, bit description

Subaddress Bit Symbol Description

F3h

F4h

F5h

7 to 0

CC2R[7:0] RED portion of second cursor color

CC2G[7:0] GREEN portion of second cursor color

CC2B[7:0] BLUE portion of second cursor color

7 to 0

Table 100: Auxiliary cursor color R, G and B registers, subaddresses F6h to F8h, bit

description

Subaddress Bit

Symbol

Description

F6h

F7h

F8h

7 to 0

AUXR[7:0] RED portion of auxiliary cursor color

AUXG[7:0] GREEN portion of auxiliary cursor color

AUXB[7:0] BLUE portion of auxiliary cursor color

7 to 0

Table 101: Horizontal cursor position and horizontal hot spot, MSB XCP registers,

subaddresses F9h and FAh, bit description

Subaddress Bit

Symbol

Description

FAh

F9h

7 to 3

XHS[4:0] horizontal hot spot of cursor

XCP[10:8] horizontal cursor position

XCP[7:0]

2 to 0

7 to 0

Table 102: Vertical cursor position and vertical hot spot, MSB YCP registers, subaddresses

FBh and FCh, bit description

Subaddress Bit

Symbol

YHS[4:0] vertical hot spot of cursor

must be programmed with logic 0 to ensure compatibility to

future enhancements

1 and 0 YCP[9:8] vertical cursor position

Description

FCh

7 to 3

2

-

FBh

7 to 0

YCP[7:0]

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Digital video encoder

Table 103: Input path control register, subaddress FDh, bit description

Bit

Symbol Access Value Description

7

LUTOFF R/W

color look-up table

0

1

active

bypassed

6

5

CMODE R/W

cursor mode

0

1

cursor mode; input color will be inverted

auxiliary cursor color will be inserted

LUT loading via input data stream

inactive

LUTL

R/W

0

1

color and cursor LUTs are loaded

input format

4 to 2 IF[2:0]

000

001

010

011

100

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R

5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB

5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB

8 + 8 + 8-bit 4 : 2 : 2 non-interlaced C_B-Y-C_R

8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R(ITU-R BT.656,

27 MHz clock) (in subaddresses 91h and 94h set

XPIX = number of active pixels/line)

101

110

8-bit non-interlaced index color

8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R(special

bit ordering)

1

0

MATOFF R/W

DFOFF R/W

RGB to C_R-Y-C_Bmatrix

0

1

active

bypassed

down formatter

0

1

(4 : 4 : 4 to 4 : 2 : 2) in input path is active

bypassed

Table 104: Cursor bit map register, subaddress FEh, bit description

Data byte

Description

CURSA

RAM start address for cursor bit map; the byte following subaddress FEh points to

the ﬁrst cell to be loaded with the next transmitted byte; succeeding cells are loaded

by auto-incrementing until stop condition

Table 105: Color look-up table register, subaddress FFh, bit description

Data byte

Description

COLSA

RAM start address for color LUT; the byte following subaddress FFh points to the

ﬁrst cell to be loaded with the next transmitted byte; succeeding cells are loaded by

auto-incrementing until stop condition

In subaddresses 5Bh, 5Ch, 5Dh, 5Eh, 62h and D3h all IRE values are rounded up.

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Digital video encoder

8.4 Slave transmitter

Table 106: Status byte register, subaddress 00h, bit description

Bit Symbol Access Value Description

7 to 5 VER[2:0] R

101

version identiﬁcation of the device: it will be changed with all

versions of the IC that have different programming models;

current version is 101 binary

4

3

CCRDO

CCRDE

R

1

0

1

0

set immediately after the closed caption bytes of the odd ﬁeld

have been encoded

reset after information has been written to the

subaddresses 67h and 68h

set immediately after the closed caption bytes of the even ﬁeld

have been encoded

reset after information has been written to the

subaddresses 69h and 6Ah

2

1

-

R

0

1

-

FSEQ

during ﬁrst ﬁeld of a sequence (repetition rate:

NTSC = 4 ﬁelds, PAL = 8 ﬁelds)

0

1

0

not ﬁrst ﬁeld of a sequence

during even ﬁeld

0

O_E

R

during odd ﬁeld

Table 107: Slave transmitter (slave address 89h)

Register

function

Subaddress Data byte

D7 D6

VER2 VER1 VER0 CCRDO CCRDE 0

D5

D4

D3

D2

D1

D0

Status byte 00h

FSEQ O_E

Chip ID

1Ch

CID7

0

CID6

0

CID5

0

CID4

0

CID3

0

CID2 CID1

CID0

FIFO status 80h

0

OVFL UDFL

Table 108: Chip ID register, subaddress 1Ch, bit description

Bit Symbol Access Value Description

7 to 0 CID[7:0] R

chip ID

04h

05h

SAA7104E

SAA7105E

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Digital video encoder

Table 109: FIFO status register, subaddress 80h, bit description

Bit Symbol Access Value Description

7 to 4 -

R

0h

0

-

3

2

1

IFERR

normal FIFO state

1

input FIFO overﬂow/underﬂow has occurred

normal FIFO state

BFERR

OVFL

R

0

1

buffer FIFO overﬂow, only if YUPSC = 1

no FIFO overﬂow

0

1

FIFO overﬂow has occurred; this bit is reset after this

subaddress has been read

0

UDFL

R

0

1

no FIFO underﬂow

FIFO underﬂow has occurred; this bit is reset after this

subaddress has been read

mbe737

6

G

(dB)

v

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

(1)

(2)

0

2

4

6

8

10

12

14

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig 6. Chrominance transfer characteristic 1

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Digital video encoder

mbe735

2

G

v

(dB)

0

(1)

(2)

−2

−4

−6

0

0.4

0.8

1.2

1.6

f (MHz)

(1) SCBW = 1.

(2) SCBW = 0.

Fig 7. Chrominance transfer characteristic 2

mgd672

6

(4)

G

(dB)

v

0

(2)

(3)

−6

(1)

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

(1) CCRS[1:0] = 01.

(2) CCRS[1:0] = 10.

(3) CCRS[1:0] = 11.

(4) CCRS[1:0] = 00.

Fig 8. Luminance transfer characteristic 1 (excluding scaler)

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Digital video encoder

mbe736

1

0

G

v

(dB)

(1)

−1

−2

−3

−4

−5

0

2

4

6

f (MHz)

(1) CCRS[1:0] = 00

Fig 9. Luminance transfer characteristic 2 (excluding scaler)

mgb708

6

G

(dB)

v

0

−6

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

Fig 10. Luminance transfer characteristic in RGB (excluding scaler)

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Digital video encoder

mgb706

6

0

G

v

(dB)

−6

−12

−18

−24

−30

−36

−42

−48

−54

0

2

4

6

8

10

12

14

f (MHz)

Fig 11. Color difference transfer characteristic in RGB (excluding scaler)

9. Limiting values

Table 110: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected

together and grounded (0 V); all supply pins connected together.

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DDD

V_DDA

V_i(A)

digital supply voltage

−0.5 +4.6

analog supply voltage

V

input voltage at analog inputs

V

V_i(n)

input voltage at pins XTALI, SDA

and SCL

−0.5 V_DDD+ 0.5 V

V_i(D)

input voltage at digital inputs or outputs in 3-state

−0.5 +4.6

−0.5 +5.5

V

I/O pins

[1]

outputs in 3-state

V

∆V_SS

voltage difference between

-

100

mV

V_SSA(n)and V_SSD(n)

T_stg

storage temperature

−65

+150

70

°C

V

T_amb

V_esd

ambient temperature

0

-

[2]

[3]

electrostatic discharge voltage

human body model

machine model

±2000

±200

-

V

[1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < V_DDD< 3.6 V.

[2] Class 2 according to JESD22-A114-B.

[3] Class B according to EIA/JESD22-A115-A.

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Digital video encoder

10. Thermal characteristics

Table 111: Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction to ambient in free air

38^[1]

K/W

[1] The overall R_th(j-a)value can vary depending on the board layout. To minimize the effective R_th(j-a)all power and ground pins must be

connected to the power and ground layers directly. An ample copper area directly under the SAA7104E; SAA7105E with a number of

through-hole plating, connected to the ground layer (four-layer board: second layer), can also reduce the effective R_th(j-a). Please do not

use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is

recommended.

11. Characteristics

Table 112: Characteristics

T_amb= 0 °C to 70 °C (typical values excluded); unless otherwise speciﬁed.

Symbol

Supplies

V_DDA

Parameter

Conditions

Min

Typ

Max

Unit

analog supply voltage

digital supply voltage

3.15

1.045

1.425

1.71

2.375

3.135

1

3.3

1.1

1.5

1.8

2.5

3.3

110

175

3.45

1.155

1.575

1.89

2.625

3.465

115

V

V_DDD2

V_DDD3

V_DDD4

V_DDD1

V

digital supply voltage

(DVO)

V

[1]

[2]

I_DDA

I_DDD

Inputs

V_IL

analog supply current

digital supply current

mA

1

200

[3]

LOW-level input voltage V_DDD1= 1.1 V, 1.5 V, 1.8 V or 2.5 V

V_DDD1= 3.3 V

−0.1

−0.5

-

+0.2

+0.8

V

pins RESET, TMS, TCK, TRST and

TDI

[3]

V_IH

HIGH-level input voltage V_DDD1= 1.1 V, 1.5 V, 1.8 V or 2.5 V

V_DDD1= 3.3 V

V

2

_DDD1− 0.2 -

V_DDD1+ 0.1

V_DDD1+ 0.3

V_DDD2+ 0.3

V

-

pins RESET, TMS, TCK, TRST and

TDI

I_LI

C_i

input leakage current

-

10

µA

pF

input capacitance

clocks

data

I/Os at high-impedance

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Digital video encoder

Table 112: Characteristics…continued

T_amb= 0 °C to 70 °C (typical values excluded); unless otherwise speciﬁed.

Symbol

Outputs

V_OL

Parameter

Conditions

Min

Typ

Max

Unit

[3]

LOW-level output

voltage

V_DDD1= 1.1 V, 1.5 V, 1.8 V or 2.5 V

V_DDD1= 3.3 V

0

-

0.1

0.4

V

pins TDO, TTXRQ_XCLKO2, VSM

and HSM_CSYNC

[3]

V_OH

HIGH-level output

voltage

V_DDD1= 1.1 V, 1.5 V, 1.8 V or 2.5 V

V_DDD1= 3.3 V

V

_DDD1− 0.1 -

V_DDD1

V_DDD2

V

2.4

-

pins TDO, TTXRQ_XCLKO2, VSM

and HSM_CSYNC

I²C-bus; pins SDA and SCL

V_IL

V_IH

I_i

LOW-level input voltage

−0.5

-

0.3V_DDD2

V_DDD2+ 0.3

+10

V

HIGH-level input voltage

input current

0.7V_DDD2

V

V_i= LOW or HIGH

I_OL= 3 mA

−10

µA

V

V_OL

LOW-level output

voltage (pin SDA)

-

0.4

I_o

output current

during acknowledge

3

-

mA

Clock timing; pins PIXCLKI and PIXCLKO

[4]

[5]

T_PIXCLK

t_d(CLKD)

cycle time

12

-

ns

delay from PIXCLKO to

PIXCLKI

[4]

δ

duty factor

t_HIGH/T_PIXCLK

40

-

50

-

60

%

ns

t_HIGH/T_CLKO2; output

60

[4]

t_r

rise time

fall time

1.5

t_f

-

Input timing

t_SU;DAT

input data set-up time

input data hold time

pins PD11 to PD0

2

-

ns

[6]

pins HSVGC, VSVGC and FSVGC

pins PD11 to PD0

2

t_HD;DAT

0.9

1.5

pins HSVGC, VSVGC and FSVGC

Crystal oscillator

f_nom

nominal frequency

-

27

-

MHz

[7]

∆f/f_nom

permissible deviation of

nominal frequency

−50 × 10⁻⁶

+50 × 10⁻⁶

Crystal speciﬁcation

T_amb

C_L

ambient temperature

0

-

70

-

°C

pF

Ω

load capacitance

series resistance

8

-

R_S

-

80

1.8

C₁

motional capacitance

(typical)

1.2

1.5

fF

C₀

parallel capacitance

(typical)

2.8

3.5

4.2

pF

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

63 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

Table 112: Characteristics…continued

T_amb= 0 °C to 70 °C (typical values excluded); unless otherwise speciﬁed.

Symbol Parameter Conditions

Data and reference signal output timing

Min

Typ

Max

Unit

C_o(L)

output load capacitance

8

-

40

-

pF

ns

t_o(h)(gfx)

output hold time to

graphics controller

pins HSVGC, VSVGC, FSVGC and

CBO

1.5

t_o(d)(gfx)

t_o(h)

output delay time to

graphics controller

pins HSVGC, VSVGC, FSVGC and

CBO

-

10

-

ns

output hold time

pins TDO, TTXRQ_XCLKO2, VSM

and HSM_CSYNC

3

-

t_o(d)

output delay time

pins TDO, TTXRQ_XCLKO2, VSM

and HSM_CSYNC

25

CVBS and RGB outputs

V_o(CVBS)(p-p)output voltage CVBS

(peak-to-peak value)

see Table 113

-

1.23

1

-

V

V_o(VBS)(p-p)output voltage VBS

(S-video)

(peak-to-peak value)

V_o(C)(p-p)

output voltage C

(S-video)

(peak-to-peak value)

see Table 113

-

0.89

-

V

V_o(RGB)(p-p)output voltage R, G, B

(peak-to-peak value)

-

0.7

2

-

V

∆V_o

inequality of output

signal voltages

%

R_o(L)

B_DAC

output load resistance

-

37.5

170

-

Ω

[8]

output signal bandwidth −3 dB

MHz

of DACs

ILE_lf(DAC)

low frequency integral

linearity error of DACs

-

±3

±1

LSB

DLE_lf(DAC)

low frequency

differential linearity error

of DACs

[1] Minimum value for I²C-bus bit DOWNA = 1.

[2] Minimum value for I²C-bus bit DOWND = 1.

[3] Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being inputs or outputs directly

connected to a graphics controller. Input sensitivity is ¹⁄₂V_DDD2+ 100 mV for HIGH and ¹⁄₂V_DDD2− 100 mV for LOW. The reference

voltage ¹⁄₂V_DDD2is generated on chip.

[4] The data is for both input and output direction.

[5] This parameter is arbitrary, if PIXCLKI is looped through the VGC.

[6] Tested with programming IFBP = 1.

[7] If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and

line/ﬁeld frequency.

1

[8]

B

=

with R_L= 37.5 Ω and C_ext= 20 pF (typical).

---------------------------------------------

–3 dB

2πR (C + 5 pF)

L

ext

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

64 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

T

PIXCLK

t

HIGH

V

OH

0.5V

PIXCLKO

DDD1

V

OL

t

r

t

f

d(CLKD)

V

IH

PIXCLKI

0.5V

V

IL

t

HD;DAT

t

SU;DAT

V

IH

IL

PDn

t

o(d)

t

o(h)

V

OH

OL

any output

mhc567

Fig 12. Input/output timing speciﬁcation

HSVGC

CBO

PD

XOFS

IDEL

XPIX

HLEN

mhb905

Fig 13. Horizontal input timing

HSVGC

VSVGC

CBO

YOFS

YPIX

mhb906

Fig 14. Vertical input timing

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

65 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

11.1 Teletext timing

Time t_FDis the time needed to interpolate input data TTX and insert it into the CVBS and

VBS output signal, such that it appears at t_TTX= 9.78 µs (PAL) or t_TTX= 10.5 µs (NTSC)

after the leading edge of the horizontal synchronization pulse.

Time t_PDis the pipeline delay time introduced by the source that is gated by

TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register

TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit

must be provided by the source.

Since the beginning of the pulses representing the TTXRQ signal and the delay between

the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS

and TTXHD), the TTX data is always inserted at the correct position after the leading edge

of the outgoing horizontal synchronization pulse.

Time t_i(TTXW)is the internally used insertion window for TTX data; it has a constant length

that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbit/s (PAL),

296 teletext bits at a text data rate of 5.7272 Mbit/s (world standard TTX) or 288 teletext

bits at a text data rate of 5.7272 Mbit/s (NABTS). The insertion window is not opened if

the control bit TTXEN is zero.

Using appropriate programming, all suitable lines of the odd ﬁeld (TTXOVS and TTXOVE)

plus all suitable lines of the even ﬁeld (TTXEVS and TTXEVE) can be used for teletext

insertion.

It is essential to note that the two pins used for teletext insertion must be

conﬁgured for this purpose by the correct I²C-bus register settings.

CVBS/Y

t

TTX

i(TTXW)

text bit #:

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

TTX_SRES

t

FD

PD

TTXRQ_XCLKO2

mhb891

Fig 15. Teletext timing

SAA7104E_SAA7105E_2

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Rev. 02 — 23 December 2005

66 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

12. Application information

DVO

supply

+3.3 V digital

supply

+3.3 V analog

supply

AGND

0.1 µF

1 nF

DGND

AGND

10 pF

use one capacitor

0.1 µH

for each V

27 MHz

DDD

DDA

V

DDD1

V

to V

DDD4

V

to V

DDA3

XTALI

XTALO

DDD2

DDA1

VSM, HSM_CSYNC

GREEN_VBS_CVBS

FLTR0

U

75 Ω

Y

AGND

RED_CR_C_CVBS

FLTR1

AGND

SAA7104E

SAA7105E

digital

inputs

and

75 Ω

C

outputs

AGND

BLUE_CB_CVBS

FLTR2

AGND

75 Ω

CVBS

AGND

DUMP

AGND

V

to V

V

SSA

RSET

SSD1

SSD4

1 kΩ

12 Ω

mhc574

DGND

AGND

Fig 16. Application circuit

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

67 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

C16

120 pF

L2

L3

2.7 µH

C10

C13

390 pF

560 pF

AGND

JP11

JP12

FIN

FOUT

FILTER 1

= byp.

ll act.

mhb912

Fig 17. FLTR0, FLTR1 and FLTR2 of Figure 16

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

68 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

SAA7104E

SAA7105E

A5

SAA7104E

SAA7105E

A6

XTALO

A5

A6

XTALO

XTALI

27.00 MHz

39 pF

4.7 µH

18 pF

39 pF

1 nF

001aad417

001aad418

a. With 3rd harmonic quartz.

Crystal load = 8 pF.

b. With fundamental quartz.

Crystal load = 20 pF.

SAA7104E

SAA7105E

A5

SAA7104E

SAA7105E

A5

A6

XTALI

XTALO

XTALI

XTALO

R

s

n.c.

27.00 MHz

clock

001aad419

001aad420

c. With direct clock.

d. With fundamental quartz and restricted drive level.

When P_driveof the internal oscillator is too high, a

resistance R_scan be placed in series with the

oscillator output XTALO.

Note: The decreased crystal amplitude results in a

lower drive level but on the other hand the jitter

performance will decrease.

Fig 18. Oscillator application

12.1 Reconstruction ﬁlter

Figure 17 shows a possible reconstruction ﬁlter for the digital-to-analog converters. Due to

its cut-off frequency of 6 MHz, it is not suitable for HDTV applications.

12.2 Analog output voltages

The analog output voltages are dependent on the total load (typical value 37.5 Ω), the

digital gain parameters and the I²C-bus settings of the DAC reference currents (analog

settings).

The digital output signals in front of the DACs under nominal (nominal here stands for the

settings given in Table 37 to Table 41 for example a standard PAL or NTSC signal)

conditions occupy different conversion ranges, as indicated in Table 113 for a ¹⁰⁰

bar signal.

⁄₁₀₀color

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

69 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

By setting the reference currents of the DACs as shown in Table 113, standard compliant

amplitudes can be achieved for all signal combinations; it is assumed that in

subaddress 16h, parameter DACF = 0000b, that means the ﬁne adjustment for all DACs

in common is set to 0 %.

If S-video output is desired, the adjustment for the C (chrominance subcarrier) output

should be identical to the one for VBS (luminance plus sync) output.

Table 113: Digital output signals conversion range

Set/out

CVBS, sync tip-to-white

see Table 37 to Table 41

1014

VBS, sync tip-to-white

see Table 37 to Table 41

881

RGB, black-to-white

see Table 31 and Table 32

876

Digital settings

Digital output

Analog settings

Analog output

e.g. B DAC = 1Fh

1.23 V (p-p)

e.g. G DAC = 1Bh

1.00 V (p-p)

e.g. R DAC = G DAC = B DAC = 0Bh

0.70 V (p-p)

12.3 Suggestions for a board layout

Use separate ground planes for analog and digital ground. Connect these planes only at

one point directly under the device, by using a 0 Ω resistor directly at the supply stage.

Use separate supply lines for the analog and digital supply. Place the supply decoupling

capacitors close to the supply pins.

Use L_bead(ferrite coil) in each digital supply line close to the decoupling capacitors to

minimize radiation energy (EMC).

Place the analog coupling (clamp) capacitors close to the analog input pins. Place the

analog termination resistors close to the coupling capacitors.

Be careful of hidden layout capacitors around the crystal application.

Use serial resistors in clock, sync and data lines, to avoid clock or data reﬂection effects

and to soften data energy.

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

70 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

13. Test information

13.1 Boundary scan test

The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary

scan testing which allows board testing without special hardware (nails). The SAA7104E;

SAA7105E follows the ‘IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan

Architecture’ set by the Joint Test Action Group (JTAG) chaired by Philips.

The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST),

Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and

IDCODE are all supported; see Table 114. Details about the JTAG BST-TEST can be

found in the speciﬁcation ‘IEEE Std. 1149.1’. A ﬁle containing the detailed Boundary Scan

Description Language (BSDL) of the SAA7104E; SAA7105E is available on request.

Table 114: BST instructions supported by the SAA7104E; SAA7105E

Instruction Description

BYPASS

EXTEST

SAMPLE

This mandatory instruction provides a minimum length serial path (1 bit) between

TDI and TDO when no test operation of the component is required.

This mandatory instruction allows testing of off-chip circuitry and board level

interconnections.

This mandatory instruction can be used to take a sample of the inputs during

normal operation of the component. It can also be used to preload data values into

the latched outputs of the boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This

instruction addresses the bypass register while the boundary scan register is in

external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer,

part number and version number.

13.1.1 Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state

(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces

the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard speciﬁes that the TAP controller will be forced

asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.

13.1.2 Device identiﬁcation codes

A device identiﬁcation register is speciﬁed in ‘IEEE Std. 1149.1b-1994’. It is a 32-bit

register which contains ﬁelds for the speciﬁcation of the IC manufacturer, the IC part

number and the IC version number. Its biggest advantage is the possibility to check for the

correct ICs mounted after production and to determine the version number of the ICs

during ﬁeld service.

When the IDCODE instruction is loaded into the BST instruction register, the identiﬁcation

register will be connected between pins TDI and TDO of the IC. The identiﬁcation register

will load a component speciﬁc code during the CAPTURE_DATA_REGISTER state of the

TAP controller, this code can subsequently be shifted out. At board level this code can be

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

71 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

used to verify component manufacturer, type and version number. The device

identiﬁcation register contains 32 bits, numbered 31 to 0, where bit 31 is the most

signiﬁcant bit (nearest to TDI) and bit 0 is the least signiﬁcant bit (nearest to TDO);

see Figure 19.

MSB

31

LSB

28 27

12 11

1

0

TDI

TDO

0101

1

0111 0001 0000 0100

16-bit part number

000 0001 0101

4-bit

version

code

11-bit manufacturer

identification

mhc568

a. SAA7104E.

MSB

31

LSB

28 27

12 11

1

0

TDI

TDO

0101

1

0111 0001 0000 0101

16-bit part number

000 0001 0101

4-bit

version

code

11-bit manufacturer

identification

mhc569

b. SAA7105E.

Fig 19. 32 bits of identiﬁcation code

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

72 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

14. Package outline

LBGA156: plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm

SOT700-1

A

B

D

ball A1

index area

A

2

A

1

E

detail X

C

e

1

y

1/2 e

v M

b

C

A

B

C

1

e

w M

P

N

L

e

M

K

H

F

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

2

4

6

8

10

12

14

X

5

10 mm

0

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

2

y

D

E

v

w

y

1

2

1

max.

0.45 1.20 0.55 15.2 15.2

0.35 0.95 0.45 14.8 14.8

mm 1.65

0.12 0.35

1

13

0.25

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

01-05-11

01-11-06

SOT700-1

- - -

MO-192

- - -

Fig 20. Package outline SOT700-1 (LBGA156)

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

73 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

15. Soldering

15.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

15.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

15.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

74 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

15.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

15.5 Package related soldering information

Table 115: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

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Product data sheet

Rev. 02 — 23 December 2005

75 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

16. Revision history

Table 116: Revision history

Document ID

Release date Data sheet status Change notice Doc. number Supersedes

Product data sheet CPCN SAA7104E_SAA7105E_1

200505019

SAA7104E_SAA7105E_2 20051223

-

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors

• Table 4: updated description for pin E2

• Package outline changed from SOT472-1 to SOT700-1

SAA7104E_SAA7105E_1 20040304

Product

speciﬁcation

-

9397 750

11436

-

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

76 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

17. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Right to make changes — Philips Semiconductors reserves the right to

18. Deﬁnitions

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

ICs with Macrovision copyright protection technology — This product

incorporates copyright protection technology that is protected by method

claims of certain U.S. patents and other intellectual property rights owned by

Macrovision Corporation and other rights owners. Use of this copyright

protection technology must be authorized by Macrovision Corporation and is

intended for home and other limited viewing uses only, unless otherwise

authorized by Macrovision Corporation. Reverse engineering or disassembly

is prohibited.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Disclaimers

20. Trademarks

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

SAA7104E_SAA7105E_2

Product data sheet

Rev. 02 — 23 December 2005

77 of 78

SAA7104E; SAA7105E

Philips Semiconductors

Digital video encoder

22. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

10

Thermal characteristics . . . . . . . . . . . . . . . . . 62

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62

Teletext timing . . . . . . . . . . . . . . . . . . . . . . . . 66

11

11.1

12

Application information . . . . . . . . . . . . . . . . . 67

Reconstruction ﬁlter . . . . . . . . . . . . . . . . . . . . 69

Analog output voltages. . . . . . . . . . . . . . . . . . 69

Suggestions for a board layout. . . . . . . . . . . . 70

12.1

12.2

12.3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

13

13.1

13.1.1

13.1.2

Test information. . . . . . . . . . . . . . . . . . . . . . . . 71

Boundary scan test . . . . . . . . . . . . . . . . . . . . 71

Initialization of boundary scan circuit . . . . . . . 71

Device identiﬁcation codes. . . . . . . . . . . . . . . 71

7

7.1

7.2

7.3

7.4

7.5

7.6

7.7

Functional description . . . . . . . . . . . . . . . . . . . 8

Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . 9

Input formatter . . . . . . . . . . . . . . . . . . . . . . . . 10

RGB LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Cursor insertion . . . . . . . . . . . . . . . . . . . . . . . 10

RGB Y-C_B-C_Rmatrix. . . . . . . . . . . . . . . . . . . . 11

Horizontal scaler. . . . . . . . . . . . . . . . . . . . . . . 11

Vertical scaler and anti-ﬂicker ﬁlter . . . . . . . . . 12

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Border generator. . . . . . . . . . . . . . . . . . . . . . . 12

Oscillator and Discrete Time Oscillator (DTO) 13

Low-pass Clock Generation Circuit (CGC) . . . 13

Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Video path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Teletext insertion and encoding (not

simultaneously with real-time control). . . . . . . 14

Video Programming System (VPS) encoding. 14

Closed caption encoder . . . . . . . . . . . . . . . . . 14

Anti-taping (SAA7104E only) . . . . . . . . . . . . . 14

RGB processor . . . . . . . . . . . . . . . . . . . . . . . . 15

Triple DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

HD data path. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Timing generator. . . . . . . . . . . . . . . . . . . . . . . 15

Pattern generator for HD sync pulses. . . . . . . 16

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 20

Power-down modes . . . . . . . . . . . . . . . . . . . . 20

Programming the SAA7104E; SAA7105E . . . 20

TV display window . . . . . . . . . . . . . . . . . . . . . 21

Input frame and pixel clock . . . . . . . . . . . . . . . 21

Horizontal scaler. . . . . . . . . . . . . . . . . . . . . . . 22

Vertical scaler . . . . . . . . . . . . . . . . . . . . . . . . . 22

Input levels and formats . . . . . . . . . . . . . . . . . 23

14

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 73

15

15.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 74

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 74

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 75

Package related soldering information. . . . . . 75

15.2

15.3

15.4

15.5

7.8

7.9

7.10

7.11

7.12

7.12.1

7.12.2

16

17

18

19

20

21

Revision history . . . . . . . . . . . . . . . . . . . . . . . 76

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 77

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Contact information . . . . . . . . . . . . . . . . . . . . 77

7.12.3

7.12.4

7.12.5

7.13

7.14

7.15

7.16

7.17

7.18

7.19

7.20

7.20.1

7.20.2

7.20.3

7.20.4

7.21

8

Register description . . . . . . . . . . . . . . . . . . . . 27

Bit allocation map . . . . . . . . . . . . . . . . . . . . . . 27

I²C-bus format. . . . . . . . . . . . . . . . . . . . . . . . . 32

Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . 33

Slave transmitter. . . . . . . . . . . . . . . . . . . . . . . 57

8.1

8.2

8.3

8.4

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 61

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 23 December 2005

Document number: SAA7104E_SAA7105E_2

Published in The Netherlands


型号：	SAA7105E/V1/S1,557
厂家：	NXP
描述：	IC COLOR SIGNAL ENCODER, PBGA156, 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156, Color Signal Converter 编码器商用集成电路
文件：	总78页 (文件大小：331K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAA7105E/V1/S1,557 [NXP]

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