SAA7165 [NXP]
Digital Video Encoder EURO-DENC2; 数字视频编码器EURO- DENC2
| 型号： | SAA7165 |
| 厂家： | 
NXP |
| 描述： | Digital Video Encoder EURO-DENC2 |
| 文件： | 总45页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7182A; SAA7183A
Digital Video Encoder
(EURO-DENC2)
1996 Oct 02
Preliminary specification
Supersedes data of 1996 Sep 11
File under Integrated Circuits, IC22
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
FEATURES
• Monolithic CMOS 3.3 V device with 5 V input stages
• Digital PAL/NTSC/SECAM encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. “(CCIR 656)” or
Y and Cb, Cr on 16 lines
This applies to SAA7183A only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
• Three DACs for CVBS, Y and C operating at 27 MHz
with 10 bit resolution
• Three DACs for RGB operating at 27 MHz with 9 bit
resolution, RGB sync on CVBS and Y
• Analog multiplexing between internal RGB and external
RGB on-chip
• Controlled rise/fall times of output syncs and blanking
• Down-mode of DACs
• CVBS, Y, C and RGB output simultaneously
• Closed captioning and teletext encoding including
sequencer and filter
• PQFP80 or PLCC84 package.
• Line 23 wide screen signalling encoding
• On-chip Cr, Y, Cb to RGB dematrix, including gain
adjustment for Y and Cr, Cb, optionally to be by-passed
for Cr, Y, Cb output on RGB DACs
GENERAL DESCRIPTION
The SAA7182A; SAA7183A encodes digital YUV video
data to an NTSC, PAL, SECAM CVBS or S-Video signal
and also RGB.
• Fast I2C-bus control port (400 kHz)
• Encoder can be master or slave
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
• Programmable horizontal and vertical input
synchronization phase
• Programmable horizontal sync output phase
• Internal Colour Bar Generator (CBG)
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
• Overlay with Look-Up Tables (LUTs) 8 × 3 bytes
• Macrovision Pay-per-View copy protection system as
option, also used for RGB output.
The circuit is compatible to the DIG-TV2 chip family.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
plastic leaded chip carrier; 84 leads
VERSION
SAA7182AWP;
SAA7183AWP
PLCC84
QFP80
SOT189-2
SOT318-2
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
1996 Oct 02
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
3.3 V analog supply voltage
MIN.
3.1
TYP.
3.3
MAX.
3.5
UNIT
VDDA3
VDDD3
VDDD5
IDDA
V
3.3 V digital supply voltage
5 V digital supply voltage
analog supply current
3.0
4.75
−
3.3
5.0
−
3.6
5.25
110
80
V
V
mA
mA
mA
IDDD3
IDDD5
Vi
3.3 V digital supply current
5 V digital supply current
input signal voltage levels
−
−
−
−
10
TTL compatible
Vo(p-p)
analog output signal voltages Y, C, CVBS and RGB without load
(peak-to-peak value)
−
1.4
−
V
RL
load resistance
75
−
−
−
−
−
300
±2
Ω
ILE
LF integral linearity error
LF differential linearity error
operating ambient temperature
LSB
LSB
°C
DLE
Tamb
−
±1
0
+70
1996 Oct 02
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
BLOCK DIAGRAM
RTCI
RCV1 TTXRQ XTALO LLC
RCV2
V
to V
DDA9
DDA4
TESTB
RESET SDA SCL SA
CREF XTALI
CDIR
1
84 83
4
75
44 48
37 50 35 36 20 47 45
63, 64,
68, 70,
72, 74
2
I C-bus
8
control
2
I C-BUS
SECAM
SYNC
INTERFACE
PROCESSOR
CLOCK
2
I C-bus
control
2
8
I C-bus
8
clock
and timing
10 to 13
16 to 19
control
DP0
to
DP7
DbDr
8
Y
Y
73
71
69
25 to 28
31 to 34
8
CVBS
Y
MP7
to
MP0
D
OUTPUT
INTERFACE
DATA
ENCODER
CbCr
C
MANAGER
A
CHROMA
OVL2
to
OVL0
6 to 8
3
V
9
SSA1
2
2
52, 67, 76
I C-bus
I C-bus
control
KEY
to
8
8
internal
control bus
control
2
V
SSA3
I C-bus
control
53
65
62
TESTC
SELI
2
21
I C-bus
8
TTX
RI
SAA7182A
SAA7183A
control
3
61
58
55
RED
D
Y
RGB
PROCESSOR
GREEN
BLUE
CbCr
A
3, 15, 24,
30, 39, 42,
51, 79, 81
5, 14, 22,
29, 38, 46,
49, 80, 82
54,
57, 60
2, 23, 40, 41,
43, 66
78
77
59 56
BI
MGD668
GI
n.c.
V
SP AP
V
V
V
DDA1
DDD1
SSD1
to
to
to
V
V
DDA3
DDD9
SSD9
Fig.1 Block diagram; PLCC84.
1996 Oct 02
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
RTCI
RCV1 TTXRQ XTALO LLC
RCV2
V
to V
DDA9
DDA4
TESTB
RESET SDA SCL SA
CREF XTALI
h
CDIR
73 72 71 75
63
32 36
27 38 25 26 11 35 33
52, 53,
56, 58,
60, 62
2
I C-bus
8
control
2
I C-BUS
SECAM
SYNC
INTERFACE
PROCESSOR
CLOCK
2
I C-bus
control
2
8
I C-bus
8
clock
and timing
1 to 4
control
DP0
to
DP7
DbDr
7 to 10
8
Y
Y
61
59
57
15 to 18
21 to 24
8
CVBS
Y
MP7
to
MP0
D
OUTPUT
INTERFACE
DATA
ENCODER
CbCr
C
MANAGER
A
CHROMA
77 to 79
3
OVL2
to
OVL0
V
SSA1
80
2
2
41, 55, 64
I C-bus
I C-bus
control
KEY
to
8
8
internal
control bus
control
V
2
SSA3
I C-bus
control
42
54
51
TESTC
SELI
RI
2
12
I C-bus
8
TTX
SAA7182A
SAA7183A
control
3
50
47
44
RED
D
Y
RGB
PROCESSOR
GREEN
BLUE
CbCr
A
6, 14, 20,
29, 31, 39,
67, 69, 74
5, 13, 19,
28, 34, 37,
68, 70, 76
43,
46, 49
66
65
30, 40
n.c.
48 45
BI
MGD670
GI
V
SP AP
V
V
V
DDA1
DDD1
SSD1
to
to
to
V
V
DDA3
DDD9
SSD9
Fig.2 Block diagram; QFP80.
1996 Oct 02
5
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PINNING
PIN
SYMBOL
DESCRIPTION
PLCC84 QFP80
RESET
1
73
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I2C-bus receiver waits for the START condition.
n.c.
2
3
4
−
6
not connected
digital ground 1
VSSD1
SA
75
The I2C-bus slave address select input pin. LOW: slave address = 88H,
HIGH = 8CH.
VDDD1
OVL2
OVL1
OVL0
KEY
5
13
77
78
79
80
1
digital supply voltage 1 (3.3 V)
6
7
3-bit overlay data input. This is the index for the internal look-up table.
Key input for OVL. When HIGH it selects OVL input.
8
9
DP0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DP1
2
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
DP2
3
DP3
4
VDDD2
VSSD2
DP4
5
digital supply voltage 2 (5 V)
digital ground 2
14
7
DP5
8
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
DP6
9
DP7
10
11
12
28
−
TTXRQ
TTX
Teletext request output, indicating when bit stream is valid.
Teletext bit stream input.
VDDD3
n.c.
digital supply voltage 3 (3.3 V)
not connected
VSSD3
MP7
20
15
16
17
18
19
29
21
22
23
24
25
26
digital ground 1
MP6
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
MP5
MP4
VDDD4
VSSD4
MP3
digital supply voltage 4 (5 V)
digital ground 4
MP2
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
MP1
MP0
RCV1
RCV2
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for video port. This pin provides an HS pulse of programmable
length or receives an HS pulse.
1996 Oct 02
6
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN
SYMBOL
DESCRIPTION
PLCC84 QFP80
RTCI
37
27
Real Time Control input. If the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality.
VDDD5
VSSD5
n.c.
38
39
40
41
42
43
44
68
39
40
−
digital supply voltage 5 (3.3 V)
digital ground 5
not connected
n.c.
not connected
VSSD6
n.c.
31
30
32
digital ground 6 for oscillator
not connected
XTALI
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be
connected to ground.
XTALO
VDDD6
CREF
LLC
45
46
47
48
33
34
35
36
Crystal oscillator output (to crystal).
digital supply voltage 6 for oscillator (3.3 V)
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O
direction is set by the CDIR pin.
VDDD7
CDIR
49
50
37
38
digital supply voltage 7 (5 V)
Clock direction. If CDIR input is HIGH, the circuit receives a clock and optional
CREF signal, otherwise if CDIR is LOW, CREF and LLC are generated by the
internal crystal oscillator.
VSSD7
VSSA1
TESTC
VDDA1
BLUE
BI
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
67
41
42
43
44
45
46
47
48
49
50
51
52
53
54
digital ground 7
Analog ground 1 for the DACs.
Analog test pin. Leave open-circuit for normal operation.
Analog supply voltage 1 for the RGB DACs (3.3 V).
Analog output of the BLUE component.
Analog input that can be switched to BLUE when SELI = HIGH.
Analog supply voltage 2 for RGB DACs (3.3 V).
Analog output of GREEN component.
VDDA2
GREEN
GI
Analog input that can be switched to GREEN when SELI = HIGH.
Analog supply voltage 3 for RGB DACs (3.3 V).
Analog output of RED component.
VDDA3
RED
RI
Analog input that can be switched to RED when SELI = HIGH.
Analog supply voltage 4 for DACs (3.3 V).
Analog supply voltage 5 for DACs (3.3 V).
VDDA4
VDDA5
SELI
Select analog input. Digital-to-analog converted RGB output when SELI = LOW;
RI, GI and BI output when SELI = HIGH.
n.c.
66
67
68
69
70
−
not connected
VSSA2
VDDA6
CHROMA
VDDA7
55
56
57
58
Analog ground 2 for the DACs.
Analog supply voltage 6 for DACs (3.3 V).
Analog output of the chrominance signal.
Analog supply voltage 7 for the Y/C/CVBS DACs (3.3 V).
1996 Oct 02
7
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PIN
SYMBOL
DESCRIPTION
PLCC84 QFP80
Y
71
72
73
74
75
76
77
78
79
80
81
82
83
84
59
60
61
62
63
64
65
66
69
76
74
70
71
72
Analog output of VBS signal.
VDDA8
CVBS
VDDA9
TESTB
VSSA3
AP
Analog supply voltage 8 for the Y/C/CVBS DACs.
Analog output of the CVBS signal.
Analog supply voltage 9 for the Y/C/CVBS DACs.
Analog test pin. Leave open-circuit for normal operation.
Analog ground 3 for the DACs.
Test pin. Connected to digital ground for normal operation.
Test pin. Connected to digital ground for normal operation.
digital ground 8
SP
VSSD8
VDDD8
VSSD9
VDDD9
SCL
digital supply voltage 8 (3.3 V)
digital ground 9
digital supply voltage 9 (5 V)
I2C-bus serial clock input.
I2C-bus serial data input/output.
SDA
1996 Oct 02
8
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
DP2 12
DP3 13
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
V
DDA9
CVBS
V
14
15
V
DDD2
DDA8
V
Y
SSD2
DP4 16
DP5 17
DP6 18
DP7 19
V
DDA7
CHROMA
V
DDA6
V
SSA2
TTXRQ 20
TTX 21
n.c.
SELI
SAA7182A
SAA7183A
V
22
V
DDD3
DDA5
n.c. 23
24
V
DDA4
V
RI
SSD3
MP7 25
MP6 26
MP5 27
MP4 28
29
RED
V
DDA3
GI
GREEN
V
V
DDD4
DDA2
V
30
BI
SSD4
MP3 31
BLUE
MP2
32
V
DDA1
MGD669
Fig.3 Pin configuration; PLCC84.
9
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
DP0
DP1
DP2
DP3
1
2
3
4
5
6
7
8
9
64 V
SSA3
63 TESTB
62
V
DDA9
61 CVBS
V
60
59
58
V
Y
V
DDD2
DDA8
DDA7
V
SSD1
DP4
DP5
DP6
57 CHROMA
56
55
V
V
DDA6
SSA2
DP7 10
TTXRQ 11
TTX 12
54 SELI
53
52
V
V
DDA5
DDA4
SAA7182A
SAA7183A
V
13
14
DDD1
V
51 RI
SSD2
MP7 15
MP6 16
MP5 17
MP4 18
19
50 RED
49
V
DDA3
48 GI
47 GREEN
V
46 V
DDA2
DDD4
V
20
45 BI
SSD3
MP3 21
MP2 22
MP1 23
MP0 24
44 BLUE
43
V
DDA1
42 TESTC
41
V
SSA1
MGD671
Fig.4 Pin configuration; QFP80.
10
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
actual subcarrier, PAL-ID, and if connected to SAA7111,
definite subcarrier phase can be inserted.
FUNCTIONAL DESCRIPTION
The digital video encoder (EURO-DENC2) encodes digital
luminance and colour difference signals into analog CVBS
and simultaneously S-Video signals. NTSC-M, PAL B/G,
SECAM standards and sub-standards are supported.
The EURO-DENC2 synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock.
European teletext encoding is supported if an appropriate
teletext bitstream is applied to the TTX pin.
Both interlaced and non-interlaced operation is possible
for all standards.
Wide screen signalling data can be loaded via the I2C-bus,
and is inserted into line 23 for standards using 50 Hz field
rate.
In addition, the de-matrixed Y, Cb, and Cr input is
available on three separate analog outputs as RED,
GREEN and BLUE. Under software control the dematrix
can be by-passed to output digital-to-analog converted Cr,
Y, and Cb signals on RGB outputs. Separate digital gain
adjustment for luminance and colour difference signals is
available.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21), and supports anti-taping
signal generation in accordance with Macrovision; it also
supports overlay via KEY and three control bits by a
24 × 8 LUT.
Analog on-chip multiplexing between internal
digital-to-analog converted RGB and external RI, GI and
BI signals is also supported.
A number of possibilities are provided for setting different
video parameters such as:
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of “RS-170-A” and “CCIR 624”.
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I2C-bus interface to abort any running bus transfer and
sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers
are not influenced by a reset.
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see
Figs 5, 6, 7, 8, 9 and 10. The DACs for Y, C, and CVBS
are realized with full 10-bit resolution, DACs for RGB are
with 9-bit resolution.
Data manager
In the data manager, real time arbitration on the data
stream to be encoded is performed.
The MPEG port (MP) accept 8 line multiplexed Cb, Y, Cr
data.
Depending on the polarity of pin KEY, the MP input
(or MP/DP input) or OVL input are selected to be encoded
to CVBS and Y/C signals, and output as RGB.
The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is to operate in
slave mode.
KEY controls OVL entries of a programmable LUT for
encoded signals and for RGB output. The common KEY
switching signal can be disabled by software for the
signals to be encoded (Y, C and CVBS), such that OVL will
appear on RGB outputs, but not on Y, C and CVBS.
Alternatively, 8-bits Y on MP port and 8-bit multiplexed Cb,
Cr on DP port can be chosen as input.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided.
OVL input under control of KEY can be also used to insert
decoded teletext information or other on-screen data.
Optionally, the OVL colour LUTs located in this block, can
be read out in a pre-defined sequence (8 steps per active
video line), achieving, for example, a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
It is also possible to connect a Philips Digital Video
Decoder (SAA7111 or SAA7151B) in conjunction with a
CREF clock qualifier to EURO-DENC2. Via the RTCI pin,
connected to RTCO of a decoder, information concerning
1996 Oct 02
11
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Encoder
CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.
VIDEO PATH
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, and blanking level,
programmable also in a certain range to allow for
manipulations with Macrovision anti-taping, additional
insertion of AGC super-white pulses, programmable in
height, is supported.
The actual line number where data is to be encoded in, can
be modified in a certain range.
Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. This filter is also
used to define smoothed transients for synchronization
pulses and blanking period. For transfer characteristic of
the luminance interpolation filter see Figs 7 and 8.
It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.
ANTI-TAPING (SAA7183A ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from 6.75 MHz data rate to 27 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. For transfer characteristics of the
chrominance interpolation filter see Figs 5 and 6.
RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, Cb and Cr signals are de-matrixed, individual
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
For transfer curves of luminance and colour difference
components of RGB see Figs 9 and 10.
The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.
SECAM processor
The numeric ratio between Y and C outputs is in
accordance with set standards.
SECAM specific pre-processing is achieved in this block
by a pre-emphasis of colour difference signals (for gain
and phase see Figs 11 and 12).
TELETEXT INSERTION AND ENCODING
Pin TTX receives a teletext bitstream sampled at the LLC
clock, each teletext bit is carried by four or three LLC
samples.
A baseband frequency modulator with a reference
frequency shifted from 4.286 MHz to DC carries out
SECAM modulation in accordance with appropriate
standard or optionally wide clipping limits.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
After the HF pre-emphasis, also applied on a DC reference
carrier (anti-Cloche filter; see Figs 13 and 14), line-by-line
sequential carriers with black reference of 4.25 MHz (Db)
and 4.40625 MHz (Dr) are generated using specified
values for FSC programming bytes.
TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines selectable independently for both fields.
The internal insertion window for text is set to 360 teletext
bits including clock run-in bits. For protocol and timing
see Fig.19.
Alternating phase reset in accordance with SECAM
standard is carried out automatically. During vertical
blanking the so-called bottle pulses are not provided.
1996 Oct 02
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
Output interface/DACs
or;
In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
• An ODD/EVEN signal which is LOW in odd fields, or;
• A field sequence signal (FSEQ) which is HIGH in the first
of 4, 8, 12 fields respectively.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
of the DAC for CVBS is reduced by 15
⁄16 with respect to
Y and C DACs to make maximum use of conversion
ranges.
The polarity of both RCV1 and RCV2 is selectable by
software control.
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 9-bit resolution. It is
also possible to feed through three external analog RGB
signals at pins RI, BI and GI when pin SELI = HIGH
The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
Outputs of the DACs can be set together in two groups via
software control to minimum output voltage for either
purpose.
I2C-bus interface
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Synchronization
Synchronization of the EURO-DENC2 is able to operate in
two modes; slave mode and master mode.
Two I2C-bus slave addresses are selected:
88H: LOW at pin SA
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
8CH: HIGH at pin SA.
Input levels and formats
EURO-DENC2 expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with “CCIR 601”.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin.
Timing and trigger behaviour can also be influenced for
RCV2.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
If there are missing pulses at RCV1 and/or RCV2, the time
base of EURO-DENC2 runs free, thus an arbitrary number
of synchronization slopes may miss, but no additional
pulses (with the incorrect phase) must occur.
For RGB outputs variable amplification of the Y, Cb and Cr
components is provided, enabling adjustment of contrast
and colour saturation in certain range.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
Alternatively, the device can be triggered by auxiliary
codes in a CCIR 656 data stream at the MP port
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
1996 Oct 02
13
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 1 “CCIR 601” signal component levels
SIGNALS(1)
COLOUR
Y
Cb
Cr
R(2)
G(2)
B(2)
White
Yellow
Cyan
235
210
170
145
106
81
128
16
128
146
16
235
235
16
235
235
235
235
16
235
16
166
54
235
16
Green
Magenta
Red
34
16
202
90
222
240
110
128
235
235
16
235
16
16
Blue
41
240
128
16
235
16
Black
16
16
16
Notes
1. Transformation:
a) R = Y + 1.3707 × (Cr − 128)
b) G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128)
c) B = Y + 1.7324 × (Cb − 128).
2. Representation of R, G and B (or Cr, Y and Cb) at the output is 9 bits at 27 MHz.
Table 2 8-bit multiplexed format (similar to “CCIR 601”)
BITS
TIME
0
1
2
2
4
5
6
7
Sample
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Luminance pixel number
Colour pixel number
0
1
2
3
0
2
Table 3 16-bit multiplexed format (DTV2 format)
BITS
TIME
0
1
2
3
4
5
6
7
Sample Y line
Y0
Cb0
0
Y1
Cr0
1
Y2
Cb2
2
Y3
Cr2
3
Sample UV line
Luminance pixel number
Colour pixel number
0
2
1996 Oct 02
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
1996 Oct 02
15
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
1996 Oct 02
16
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
I2C-bus format
Table 5 I2C-bus address; see Table 6
S
SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
--------
DATA n ACK
P
Table 6 Explanation of Table 5
PART
DESCRIPTION
S
START condition
Slave address
1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1)
acknowledge, generated by the slave
subaddress byte
ACK
Subaddress (note 2)
DATA
--------
P
data byte
continued data bytes and ACKs
STOP condition
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
Slave Receiver
Table 7 Subaddress 26 and 27
DATA BYTE
LOGIC LEVEL
DESCRIPTION
WSS0 to WSS13
−
Wide Screen Signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
WSSON
0
1
wide screen signalling output is disabled
wide screen signalling output is enabled
Table 8 Subaddress 38 and 39
DATA BYTE
DESCRIPTION
GY0 to GY4
Gain luminance of RGB (Cr, Y and Cb) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested
nominal value = −6 (11010b), depending on external application.
GCD0 to GCD4 Gain Colour Difference of RGB (Cr, Y and Cb) output, ranging from (1 - 16⁄32) to (1 + 15⁄32).
Suggested nominal value = −6 (11010b), depending on external application.
1996 Oct 02
17
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 9 Subaddress 3A
DATA
BYTE
LOGIC
LEVEL
DESCRIPTION
UV2C
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cb, Cr data are two’s complement.
Cb, Cr data are straight binary. Default after reset.
Y data is two’s complement.
Y2C
Y data is straight binary. Default after reset.
FMT16
DEMOFF
SYMP
Selects Cb, Y, Cr and Y on 8 lines on MP port (“CCIR 656” compatible). Default after reset.
Selects Cb and Cr on DP port and Y on MP port.
Y, Cb and Cr for RGB dematrix is active. Default after reset.
Y, Cb and Cr for RGB dematrix is bypassed.
Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset.
Horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port.
Normal polarity of CREF for DIG-TV2 compatible input signals.
Inverted polarity of CREF for DIG-TV2 compatible input signals.
OVL keying enabled for Y, C and CVBS outputs. Default after reset.
OVL keying disabled for Y, C and CVBS outputs.
PCREF
DISKEY
CBENB
Data from input ports is encoded. Default after reset.
Colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in
upward order from index 0 to index 7.
1996 Oct 02
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 10 Subaddress 42 to 59
DATA BYTE(1)
COLOUR
INDEX(2)
OVLY
OVLU
OVLV
White
107 (6BH)
107 (6BH)
82 (52H)
0 (00H)
0 (00H)
0 (00H)
0 (00H)
0
1
2
3
4
5
6
7
Yellow
Cyan
144 (90H)
172 (ACH)
38 (26H)
29 (1DH)
182 (B6H)
200 (C8H)
74 (4AH)
56 (38H)
218 (DAH)
227 (E3H)
112 (70H)
84 (54H)
0 (00H)
18 (12H)
14 (0EH)
144 (90H)
172 (ACH)
162 (A2H)
185 (B9H)
94 (5EH)
71 (47H)
112 (70H)
84 (54H)
238 (EEH)
242 (F2H)
0 (00H)
34 (22H)
42 (2AH)
03 (03H)
Green
Magenta
Red
17 (11H)
240 (F0H)
234 (EAH)
212 (D4H)
209 (D1H)
193 (C1H)
169 (A9H)
163 (A3H)
144 (90H)
144 (90H)
Blue
Black
0 (00H)
0 (00H)
Notes
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with “CCIR 601”
(Y, Cb and Cr), but two’s complement, e.g. for a 100
⁄
100 (upper number) or 100
⁄
75 (lower number) colour bar.
2. For normal colour bar with CBENB = logic 1.
Table 11 Subaddress 5A
DATA BYTE(1)
VALUE
RESULT
CHPS
tbf
tbf
tbf
tbf
PAL-B/G and data from input ports
PAL-B/G and data from look-up table
NTSC-M and data from input ports
NTSC-M and data from look-up table
Note
1. Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256
degrees.
1996 Oct 02
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 12 Subaddress 5B and 5D
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINU
variable gain for Cb signal; white-to-black = 92.5 IRE(1)
input representation
accordance with
GAINU = 118 (76H)
“CCIR 601”
GAINU = 0
output subcarrier of U contribution = 0
output subcarrier of U contribution = nominal
white-to-black = 100 IRE(2)
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
nominal GAINU for
SECAM encoding
value = 106 (6AH)
Notes
1. GAINU = −2.17 × nominal to +2.16 × nominal.
2. GAINU = −2.05 × nominal to +2.04 × nominal.
Table 13 Subaddress 5C and 5E
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
GAINV
variable gain for Cr signal; white-to-black = 92.5 IRE(1)
input representation
accordance with
GAINV = 165 (A5H)
“CCIR 601”
GAINV = 0
output subcarrier of V contribution = 0
output subcarrier of V contribution = nominal
white-to-black = 100 IRE(2)
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
nominal GAINV for
SECAM encoding
value = −129 (17FH)
Notes
1. GAINV = −1.55 × nominal to +1.55 × nominal.
2. GAINV = −1.46 × nominal to +1.46 × nominal.
Table 14 Subaddress 5D
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLCKL
variable black level; input white-to-sync = 140 IRE(1)
representationaccordance
with “CCIR 601”
BLCKL = 0
output black level = 24 IRE
output black level = 49 IRE
BLCKL = 63 (3FH)
white-to-sync = 143 IRE(2)
BLCKL = 0
output black level = 24 IRE
output black level = 50 IRE
BLCKL = 63 (3FH)
Notes
1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal.
2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
1996 Oct 02
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 15 Subaddress 5E
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLNNL
variable blanking level
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
white-to-sync = 143 IRE(2)
BLNNL = 0
output blanking level = 42 IRE
output blanking level = 17 IRE
BLNNL = 63 (3FH)
logic 0
output blanking level = 43 IRE
DECTYP
RTCI
real time control input from SAA7151B
real time control input from SAA7111
logic 1
Notes
1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
Table 16 Subaddress 5F
DATA BYTE
BLNVB
DESCRIPTION
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
select cross colour reduction filter in luminance; see Table 17
CCRS
Table 17 Logic levels and function of CCRS
CCRS1
CCRS0
FUNCTION
0
0
1
1
0
1
0
1
no cross colour reduction; for overall transfer characteristic of luminance see Fig.7
cross colour reduction #1 active; for overall transfer characteristic see Fig.7
cross colour reduction #2 active; for overall transfer characteristic see Fig.7
cross colour reduction #3 active; for overall transfer characteristic see Fig.7
1996 Oct 02
21
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 18 Subaddress 61:
DATA BYTE LOGIC LEVEL
DESCRIPTION
FISE
0
1
0
1
0
864 total pixel clocks per line; default after reset
858 total pixel clocks per line
PAL
NTSC encoding (non-alternating V component)
PAL encoding (alternating V component); default after reset
SCBW
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); wide clipping for
SECAM
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 5 and 6); default after reset
SECAM
YGS
0
1
0
1
0
1
0
1
0
1
no SECAM encoding; default after reset
SECAM encoding activated
luminance gain for white − black 100 IRE; default after reset
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
PAL switch phase is nominal; default after reset
INPI
PAL switch phase is inverted compared to nominal
DACs for CVBS, Y and C in normal operational mode; default after reset
DACs for CVBS, Y and C forced to lowest output voltage
DACs for R, G and B in normal operational mode; default after reset
DACs for R, G and B forced to lowest output voltage
DOWNA
DOWNB
1996 Oct 02
22
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 19 Subaddress 62A
DATA BYTE LOGIC LEVEL
DESCRIPTION
RTCE
0
1
no real time control of generated subcarrier frequency
real time control of generated subcarrier frequency through SAA7151B or SAA7111
(timing see Fig.18)
Table 20 Subaddress 62B
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BSTA
amplitude of colour burst; white-to-black = 92.5 IRE;
input representation in
accordance with
“CCIR 601”
burst = 40 IRE; NTSC encoding
BSTA = 0 to 1.25 × nominal(1)
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
BSTA = 0 to 1.76 × nominal(2)
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding
BSTA = 0 to 1.20 × nominal(3)
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
BSTA = 0 to 1.67 × nominal(4)
fixed burst amplitude with SECAM encoding
Notes
1. Recommended value: BSTA = 102 (66H).
2. Recommended value: BSTA = 72 (48H).
3. Recommended value: BSTA = 106 (6AH).
4. Recommended value: BSTA = 75 (4BH).
Table 21 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
FSC0 to FSC3 ffsc = subcarrier frequency
(in multiples of line
frequency);
FSC3 = most significant byte
f
FSC = round fsc × 2 32
-------
fllc
FSC0 = least significant byte
fllc = clock frequency (in
multiples of line
see note 1
frequency)
Note
1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
c) SECAM: ffsc = 274.304, fllc = 1728 → FSC = 681786290 (28A33BB2H).
1996 Oct 02
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Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 22 Subaddress 67 to 6A
DATA BYTE(1)
DESCRIPTION
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
Note
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format.
Table 23 Subaddress 6B
DATA BYTE LOGIC LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
ORCV2
CBLF
0
1
0
pin RCV2 is switched to input; default after reset
pin RCV2 is switched to output
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default
after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, this is a
reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking
Interval, which is defined by FAL and LAL
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
PRCV1
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
after reset
1
0
1
0
polarity of RCV1 as output is active LOW, falling edge is taken when input
pin RCV1 is switched to input; default after reset
pin RCV1 is switched to output
ORCV1
TRCV2
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of CCIR 656 input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
defines signal type on pin RCV1; see Table 24
SRCV1
−
1996 Oct 02
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 24 Logic levels and function of SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
FUNCTION
SRCV11
SRCV10
0
0
1
0
1
0
VS
FS
VS
FS
vertical sync each field; default after reset
frame sync (odd/even)
FSEQ
FSEQ
field sequence, vertical sync every fourth field
(PAL = 0), eighth field (PAL = 1) or twelfth field
(SECAM = 1)
1
1
not applicable not applicable
−
Table 25 Subaddress 6C and 6D
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbf (tbf)
Table 26 Subaddress 6D
DATA BYTE LOGIC LEVEL
DESCRIPTION
VTRIG
−
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
Table 27 Subaddress 6E
DATA BYTE LOGIC LEVEL
DESCRIPTION
SBLBN
0
1
−
−
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 28
field length control; see Table 29
PHRES
FLC
Table 28 Logic levels and function of PHRES
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
0
1
1
0
1
0
1
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines or SECAM-specific if bit SECAM = 1
reset every eight fields
reset every four fields
1996 Oct 02
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 29 Logic levels and function of FLC
DATA BYTE
FUNCTION
FLC1
FLC0
0
0
1
1
0
1
0
1
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
Table 30 Subaddress 6F
DATA BYTE LOGIC LEVEL
DESCRIPTION
CCEN
−
0
1
−
enables individual Line 21 encoding; see Table 31
disables teletext insertion
TTXEN
enables teletext insertion
SCCLN
selects the actual line, where closed caption or extended data are encoded
line = (SCCLN + 4) for M-systems
line = (SCCLN + 1) for other systems
Table 31 Logic levels and function of CCEN
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
Line 21 encoding off
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
Table 32 Subaddress 70 to 72
DATA BYTE
DESCRIPTION
RCV2S
start of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2S = tbfH (tbfH)
RCV2E
end of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2E = tbfH (tbfH)
1996 Oct 02
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Table 33 Subaddress 73 to 75
DATA BYTE
DESCRIPTION
start of signal on pin TTXRQ (standard for 50 Hz field rate = tbf)
TTXHS
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
end of signal on pin TTXRQ (standard for 50 Hz field rate = TTXHS + 1402)
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
TTXHE
Table 34 Subaddress 76, 77 and 7C
DATA BYTE
DESCRIPTION
TTXOVS
TTXOVE
first line of occurrence of signal on pin TTXRQ in odd field = TTXOVS + 1 (50 Hz field rate)
last line of occurrence of signal on pin TTXRQ in odd field = TTXOVE (50 Hz field rate)
Table 35 Subaddress 78, 79 and 7C
DATA BYTE
DESCRIPTION
TTXEVS
TTXEVE
first line of occurrence of signal on pin TTXRQ in even field = TTXEVS + 1 (50 Hz field rate)
last line of occurrence of signal on pin TTXRQ in even field = TTXEVE (50 Hz field rate)
Table 36 Subaddress 7A to 7C
DATA BYTE
DESCRIPTION
FAL
first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
Table 37 Subaddress 7A to 7C
DATA BYTE
DESCRIPTION
LINE
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
SUBADDRESSES
In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
1996 Oct 02
27
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Slave Transmitter
Table 38 Slave transmitter (slave address 89H or 8DH)
DATA BYTE
D4 D3
REGISTER
SUBADDRESS
FUNCTION
D7
D6
D5
D2
D1
D0
Status byte
−
VER2
VER1
VER0 CCRDO CCRDE
0
FSEQ
O_E
Table 39 No subaddress
DATA BYTE LOGIC LEVEL
DESCRIPTION
VER
−
Version identification of the device. It will be changed with all versions of the IC that
have different programming models. Current Version is 001 binary.
CCRDO
1
0
Closed caption bytes of the odd field have been encoded.
The bit is reset after information has been written to the subaddresses 67 and 68. It
is set immediately after the data has been encoded.
CCRDE
FSEQ
O_E
1
0
Closed caption bytes of the even field have been encoded.
The bit is reset after information has been written to the subaddresses 69 and 6A.
It is set immediately after the data has been encoded.
1
During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields,
SECAM = 12 fields.
0
1
0
Not first field of a sequence.
During even field.
During odd field.
1996 Oct 02
28
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MBE737
6
G
v
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.5 Chrominance transfer characteristic 1.
MBE735
handbook, halfpage
2
G
v
(dB)
0
(1)
(2)
−2
−4
−6
0
0.4
0.8
1.2
1.6
f (MHz)
(1) SCBW = 1.
(2) SCBW = 0.
Fig.6 Chrominance transfer characteristic 2.
29
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGD672
6
G
v
(dB)
(4)
0
(2)
(3)
−6
−12
−18
(1)
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) CCRS1 = 0; CCRS0 = 1.
(2) CCRS1 = 1; CCRS0 = 0.
(3) CCRS1 = 1; CCRS0 = 1.
(4) CCRS1 = 0; CCRS0 = 0.
Fig.7 Luminance transfer characteristic 1.
MBE736
handbook, halfpage
1
G
v
(dB)
(1)
0
−1
−2
−3
−4
−5
0
2
4
6
f (MHz)
(1) CCRS1 = 0; CCRS0 = 0.
Fig.8 Luminance transfer characteristic 2.
30
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB708
6
G
v
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
Fig.9 Luminance transfer characteristic in RGB.
MGB706
6
G
v
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
Fig.10 Colour difference transfer characteristic in RGB.
31
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB705
10
G
v
(dB)
8
6
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.11 Gain of SECAM pre-emphasis.
MGB704
30
ϕ
(deg)
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.12 Phase of SECAM pre-emphasis.
32
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
MGB703
20
G
v
(dB)
16
12
8
4
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.13 Gain of SECAM anti-Cloche.
MGB702
80
ϕ
(deg)
60
40
20
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
f (MHz)
Fig.14 Phase of SECAM anti-Cloche.
33
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
CHARACTERISTICS
VDDD(3) = 3.0 to 3.6 V; VDDD(5) = 4.75 to 5.25 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDDA(3)
VDDD(3)
VDDD(5)
IDDA
analog supply voltage (3.3 V)
digital supply voltage (3.3 V)
digital supply voltage (5 V)
analog supply current
3.1
3.5
3.6
V
3.0
4.75
−
V
5.25
110
80
V
note 1
mA
mA
mA
IDDD(3)
IDDD(5)
digital supply current (3.3 V)
digital supply current (5 V)
note 1
note 1
−
−
10
Inputs
VIL
LOW level input voltage
−0.5
+0.8
V
(except SDA, SCL, AP, SP and XTALI)
VIH
HIGH level input voltage
2.0
VDDD(5) + 0.5 V
(except LLC, SDA, SCL, AP, SP and XTALI)
HIGH level input voltage (LLC)
input leakage current
input capacitance
2.4
−
VDDD(5) + 0.5 V
ILI
Ci
1
µA
clocks
−
10
8
pF
pF
pF
data
−
I/Os at high impedance
−
8
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
note 2
note 2
0
0.6
V
VOH
HIGH level output voltage
(except LLC, SDA, and XTALO)
2.4
2.6
VDDD(5) + 0.5 V
VDDD(5) + 0.5 V
HIGH level output voltage (LLC)
I2C-bus; SDA and SCL
VIL
VIH
Ii
LOW level input voltage
−0.5
3.0
−10
−
+1.5
V
HIGH level input voltage
input current
VDDD(5) + 0.5 V
Vi = LOW or HIGH
IOL = 3 mA
+10
0.4
−
µA
VOL
Io
LOW level output voltage (SDA)
output current
V
during acknowledge
3
mA
Clock timing (LLC)
TLLC
cycle time
note 3
note 4
note 3
note 3
34
40
−
41
60
5
ns
%
δ
tr
tf
duty factor tHIGH/TLLC
rise time
ns
ns
fall time
−
6
Input timing
tSU;DAT
input data set-up time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
6
3
−
−
ns
ns
tHD;DAT
input data hold time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
1996 Oct 02
34
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency (usually 27 MHz)
3rd harmonic
−
30
MHz
10−6
∆f/fn
permissible deviation of nominal frequency note 5
−50
+50
CRYSTAL SPECIFICATION
Tamb
CL
operating ambient temperature
0
8
−
70
−
°C
pF
Ω
load capacitance
RS
C1
series resistance
80
motional capacitance (typical)
parallel capacitance (typical)
1.5 −20% 1.5 +20%
3.5 −20% 3.5 +20%
fF
C0
pF
Data and reference signal output timing
CL
th
output load capacitance
output hold time
7.5
4
40
−
pF
ns
ns
td
output delay time
−
25
CHROMA, Y, CVBS and RGB outputs
Vo(p-p)
Rint
RL
output signal voltage (peak-to-peak value)
note 6
1.35
1
1.45
3
V
internal serial resistance
Ω
output load resistance
75
10
−
300
−
Ω
B
output signal bandwidth of DACs
LF integral linearity error of DACs
LF differential linearity error of DACs
−3 dB
MHz
LSB
LSB
ILE
DLE
±2
±1
−
Notes
1. At maximum supply voltage with highly active input signals.
2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF.
3. The data is for both input and output direction.
4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
6. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.4 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
1996 Oct 02
35
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
T
LLC
t
HIGH
2.6 V
1.5 V
0.6 V
LLC clock output
t
t
t
HD; DAT
f
r
T
LLC
t
HIGH
2.4 V
1.5 V
0.8 V
LLC clock input
t
t
f
t
HD; DAT
r
t
SU; DAT
2.0 V
valid
input data
valid
not valid
0.8 V
t
d
t
HD; DAT
2.4 V
valid
output data
valid
not valid
0.6 V
MBE742
Fig.15 Clock data timing.
LLC
MP(n)
RCV2
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.16 Functional timing.
1996 Oct 02
36
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
LLC
CREF
MP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
RCV2
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
Fig.17 Digital TV timing.
sequence reserved (2)
bit (1)
H/L transition
4 bits
5 bits
reset
count start
reserved
reserved
bit (3)
LOW
HPLL
increment
FSCPLL increment (4)
128
13
0
21
0
RTCI
time slot:
01
14
19
67 68
not used in
SAA7182A/83A
valid
sample sample
invalid
8/LLC
MGD673
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.18 RTCI timing.
1996 Oct 02
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Thus 37 TTX bits correspond to 144 LLC clocks, each bit
has a duration of nearly 4 LLC clocks. The chip-internal
sequencer and variable phase interpolation filter
minimizes the phase jitter, and thus generates a
bandwidth limited signal, which is digital-to-analog
converted for the CVBS and Y outputs.
Teletext timing
Time tFD is the time needed to interpolate input data TTX
and inserting it into the CVBS and Y output signal, such
that it appears at tTTX = 10.2 µs after the leading edge of
the horizontal synchronization pulse.
Time tPD is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data.
At the TTX input, bit duration scheme repeats after 37 TTX
bits or 144 LLC clocks. The protocol demands that TXX
bits 10, 19, 28 and 37 are carried by three LLC samples,
all others by four LLC samples. After a cycle of 37 TTX
bits, the next bits with three LLC samples are bits 47, 56,
65 and 74; this scheme holds for all succeeding cycles of
37 TTX bits, until 360 TTX bits (including 16 run-in bits)
are completed. For every additional line with TTX data, the
bit duration scheme starts in the same way.
Since the pulse representing the TTXRQ signal is fully
programmable in duration and rising/falling edges (TTXHS
and TTXHE), the TTX data is always inserted at the correct
position of 10.2 µs after the leading edge of outgoing
horizontal synchronization pulse.
Time tTTXWin is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletext bits (maximum) at a text data rate of
6.9375 Mbits/s. The insertion window is not opened if the
control bit TTXEN is zero.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
TELETEXT PROTOCOL
The frequency relationship between TTX bit clock and the
system clock LLC for 50 Hz field rate is given by the
relationship of line frequency multiples, which means
1728/444.
CVBS/Y
t
t
TTX
TTXWin
textbit #:
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TTX
4
3
4
1/LLC
4
3
4
1/LLC
t
t
PD
FD
TTXRQ
MGB701
Fig.19 Teletext timing diagram.
38
1996 Oct 02
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
APPLICATION INFORMATION
GM6D74
o o k , f u l l p a g e w i d t h
1996 Oct 02
39
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
GM0D7
b o o k , f u l l p a g e w i d t h
1996 Oct 02
40
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Values for the external series resistors result from a 75 Ω
Analog output voltages
load (see Figs 20 and 21).
The analog output voltages are dependent on the open
loop voltage of the operational amplifiers for full-scale
conversion (typical value 1.4 V), the internal series resistor
(typical value 2 Ω), the external series resistor and the
external load impedance.
The analog inputs RI, GI, and BI are shifted first by an
offset of 0.16 V (typical value), followed by an amplification
of 1.72 (typical value). For an input voltage of 0 to 0.7 V an
open loop output voltage of 0.28 to 1.48 V is achieved,
resulting in Vo = 0.86 V (p-p) with an internal series
resistor of 2 Ω, an external series resistor of 27 Ω at a 75 Ω
load impedance.
The digital output signals in front of the DACs under
nominal conditions occupy different conversion ranges, as
indicated in Table 40 for a 100
⁄100 colour bar signal.
Table 40 Digital output signals conversion range
CONVERSION RANGE (peak-to-peak
CVBS, SYNC
TIP-TO-PEAK CARRIER
(digits)
RGB (Y)
BLACK-TO-WHITE AT GDY = GDC = −6
(digits)
Y (VBS) SYNC TIP-TO-WHITE
(digits)
1023
888
712
1996 Oct 02
41
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PACKAGE OUTLINES
PLCC84: plastic leaded chip carrier; 84 leads
SOT189-2
e
e
D
E
y
X
A
74
54
Z
53
E
75
b
p
b
1
w
M
84
1
H
E
E
pin 1 index
e
A
A
1
A
4
(A )
3
k
L
1
p
11
β
33
k
detail X
12
32
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
v
w
y
β
b
D
E
D
E
p
3
p
1
max. max.
4.57
4.19
0.81 29.41 29.41
0.66 29.21 29.21
28.70 28.70 30.35 30.35 1.22
27.69 27.69 30.10 30.10 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.30
0.020 0.01 0.13
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 1.158 1.158
0.026 1.150 1.150
1.130 1.130 1.195 1.195 0.048
1.090 1.090 1.185 1.185 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT189-2
1996 Oct 02
42
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
y
X
A
64
65
41
40
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
w M
p
θ
pin 1 index
L
p
b
L
80
25
detail X
1
24
w M
Z
v
M
M
D
A
B
b
p
e
D
B
H
v
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.45 0.25 20.1 14.1
0.30 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.4
1.2
1.0
0.6
1.2
0.8
mm
3.2
0.25
0.8
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-12-15
95-02-04
SOT318-2
1996 Oct 02
43
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
• The package footprint must incorporate solder thieves at
the downstream corners.
SOLDERING
Introduction
QFP
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Reflow soldering
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
QFP100 (SOT382-1) or QFP160 (SOT322-1).
METHOD (PLCC AND QFP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
PLCC
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
1996 Oct 02
44
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Oct 02
45
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