SAA7750-N1D [NXP]
Generic device for portable multimedia applications; 通用设备,用于便携式多媒体应用型号: | SAA7750-N1D |
厂家: | NXP |
描述: | Generic device for portable multimedia applications |
文件: | 总66页 (文件大小:1555K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
Generic device for portable
multimedia applications
SAA7750-N1D
Preliminary Specification version 1.3
2002 Jan 21
File under Integrated Circuits, <Handbook>
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
CONTENTS
6.9.1
6.9.2
6.9.3
6.10
Functional Description
UART Pin Description
BaudRate Generator
General Purpose I/O
Functional Description
Interrupts
Real Time Clock (RTC)
Functional Description
Interrupts
Power Down operation
Timers
Functional description
Interrupts
Watchdog Timer
Functional description
Interrupts
IIC master Interface
Functional Description
Interrupt
IIC slave Interface
Functional description
Interrupt
LCD Interface
Functional Description
Interface
System Interface
Resetting the LCD controller
Serial mode:
Using wait states
Checking the busy flag of the LCD controller
Loopback mode
1
FEATURES
1.1
1.2
1.3
Hardware Features
General Features
Software features
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.12
6.12.1
6.12.2
6.13
6.13.1
6.13.2
6.14
6.14.1
6.14.2
6.15
6.15.1
6.15.2
6.16
6.16.1
6.16.2
6.16.3
6.16.4
6.16.5
6.16.6
6.16.7
6.16.8
6.16.9
6.17
2
3
4
5
6
GENERAL DESCRIPTION
APPLICATIONS
BLOCK DIAGRAM
PINNING
HARDWARE DESCRIPTION SSA
6.1
ARM720T microcontroller
Overview
BLOCK DIAGRAM
The THUMB Concept
Internal busses
6.1.1
6.1.2
6.1.3
6.2
6.2.1
6.2.2
6.3
Advanced High-performance Bus (AHB)
AHB Address Decoder
Memory controllers
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.4
Overview
Static Memory Controller
SDRAM Interface Controller
Internal Memory Controller
FLASH memory controller
FLASH reads
Erasing the FLASH block
Programming the FLASH block
Operating conditions
Interrupt Controller
6.4.1
6.4.2
6.5
Overview
Interrupt
Functional Description
Power Management Unit (PMU)
Functional Description
Wake-up behaviour
Watchdog behaviour
Pause behaviour
Power down behaviour
Power down Request
Power down Acknowledge
Oscillators and clock generation
Overview clock generation module
Functional Description
Multi Media Card Interface (MMC)
Choice of flash memory cards
10-bit ADC
Remote Control Interface
Functional Description
Parallel Port Interface (PPI)
USB Interface
6.17.1
6.18
6.19
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.5.1
6.5.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.8
6.19.1
Interrupts
6.19.1.1 USB_int_req_FIQ
6.19.1.2 USB_int_req_IRQ
6.19.1.3 Interrupt handling
6.19.1.4 Zero overhead operation
6.20
6.20.1
CD Block Decoder
Functional Description
6.20.1.1 Features
6.20.2
6.20.3
6.20.4
6.20.5
6.20.6
6.20.7
6.20.8
6.20.9
6.21
Input/Output Pin Function
I2C Interface
Standard Serial Interface UART
Subcode Interface
Serial Data Interface
Minimal Block Decoder
CD TEXT Mode
Q-subcode Frame Format
Digital Signal Processor (EPICS7a)
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.9
Overview
Functional description
Multi channel A/D conversion scan
ADC resolution
Interrupts
UART
2002 Jan 21
2
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
6.22
7
Digital Audio input and output
HARDWARE DESCRIPTION SSA CODEC
7.1
7.2
7.3
7.4
7.5
7.6
General
Multiple format data INPUT interface
Multiple format data OUTPUT interface
DAC digital sound processing
Block diagram
Connections to SAA7750
8
HARDWARE DESCRIPTION FLASH
LIMITING VALUES
9
10
11
12
13
14
15
16
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINE
SOLDERING
DEFINITIONS
DISCLAIMERS
17PURCHASE OF PHILIPS I2C COMPONENTS
2002 Jan 21
3
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
1
FEATURES
NOTE: this datasheet is for SAA7750El version N1D onwards!!
1.1
Hardware Features
• Integrated ARM720T 32 bit RISC processor, capable of running at 72MHz.
• High performance 32-bits bus (AHB)
• Centralized address decoding for all AHB devices
• Four possible memory maps:
– external boot
– internal flash boot
– internal ROM boot
– normal operation
• Supports USB 1.1 compliant interface for down loading data from PC
• Support for flash-card applications:
– Supports the Multi Media Card (MMC)
– Supports Smart Media Card (EBI)
– NAND FLASH (EBI)
• Memory interface (EBI) supporting a number of memory types like Static RAM, SDRAM, external Flash.
The maximum bus frequency can be up to 48MHz.
• Integrated CD block decoder for CD-DA and MP3 CD applications
• UART + IrDA (IrDA is a new block on the N1D version)
• Integrated Master and Slave IIC interface
• Real-Time Clock (RTC)
• General-Purpose IO pins (28 pins)
• Integrated Remote Control interface
• Integrated LCD interface with 6800 / 8080 type interface
• Integrated 10 bits ADC with 8 selectable inputs (via analog multiplexer).
• Integrated SPDIF output interface
• Integrated IIS input and output interface
• Integrated stereo Audio Codec
– Stereo Line input with Programmable Gain Amplifier (PGA)
– Mono Microphone input with embedded Low Noise Amplifier (LNA) and Variable Gain Amplifier (VGA
– stereo analog input with analog volume control (e.g. for tuner applications)
– stereo line output
– integrated stereo headphone driver which can be used in DC coupling (short circuit protection and detection build
in).
1.2
General Features
• Integrated ARM720T 32 bit RISC processor
• Programmable architecture enables support of multiple audio decompression algorithms.
• Designed for applications that require long battery life
2002 Jan 21
4
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
• Embedded 3Mbit (384kbyte) flash for Field upgradibility
• Embedded Audio Codec with headphone driver
• small footprint LFBGA208 package
1.3
Software features
• Audio Decoder support:
– Supports MPEG 1 layer 3 and MPEG 2 layer 2.5 and layer 3 audio decoding (MP3), up to 320kbit/s , fixed and
variable bitrate.
– Supports Microsoft WMTA 4.0 decoding
– Supports AAC-LC decoding
• Features on the audio codec:
– Digital Automatic Gain Control (AGC) on the microphone input.
– Programmable Gain Amplifier (PGA) for analog stereo line input
– Volume control (incl. balance)
– Bass-boost and Treble (left/right)
• DSP features:
– UltraBass II
– Incredible headphone
– Infrapitch
2
GENERAL DESCRIPTION
The SAA7750 is an IC based on an embedded RISC processor in combination with a simple embedded DSP core for
audio post-processing. The device is designed for hand-held applications like portable CD-DA/ MP3 players, memory
card applications or other portable applications. The high level of integration, low power consumption and high processor
performances make the SAA7750 very suitable for portable hand-held devices.
The SAA7750 is based on the powerful ARM720T CPU core, which is a full 32-bit RISC processor featuring the 16-bit
Thumb instruction set for effective memory usage. The audio streaming and post-processing for the SAA7750 is handled
by a separate audio co-processor DSP, which is a small, fast and powerful 24-bit Epics7A DSP core.
3
APPLICATIONS
• Portable Solid State Audio player
• Portable MP3 CD player
• Home audio applications
• Non-automotive Car applications
• Other portable applications like PDA
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SAA7750EL/N1 LFBGA208
low profile fine-pitch ball grid array package; 208 balls;
body 15 x 15 x 1.2 mm.
SOT631-1
2002 Jan 21
5
PHILIPSCONFIDENTIAL
5
BLOCK DIAGRAM
supplies (8C + 4P)
JTAG/TCB
AHB
Arbiter
5
12
AHB
ROM
SMC
TIC
mode selection pins
wrapper
3
AHB
wrapper
external bus interface + tic
SRAM
EBI
49
AHB
Decoder
SDRAM
Controller
FLASH memory
FLASH
3Mbit
FLASH
Controller
2
52
AHB
wrapper
ARM720T
ETU
3
4
DSP
AHB to APB
bridge
EPICS7a
TCB
Interrupt
1
4
Controller
L3/IIC
IIS
Input
bus
Interface
CD-Block
Decoder
10
IIS/SPDIF
Output
PGA
Master
IIC Interface
3
5
4
2
3
Stereo
ADC
IIS
CTU
Output
MCI
3
General
Purpose I/O
Timers
Stereo
DAC
IIS
Input
28
2
Remote
Control
3
1
Watchdog
Clock
Shop
Slave
IIC Interface
3
5
Headphone
Driver
Real-Time
Clock
3
Audio Codec
IrDA
UART
10-bits
ADC
9
4
12
USB 1.1
Interface
LCD
Interface
12
3
OSCs
PLLs
Clock
Shop
SSA
PMU
1
10
2
Fig. 1 Block diagram Solid State Audio 1
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
6
PINNING
Table 1 Pin list SAA7750EL
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
General Purpose Pins (fixed: 16 pins)
GPIO<27>
GPIO<26>
GPIO<25>
GPIO<24>
GPIO<23>
GPIO<22>
GPIO<21>
GPIO<20>
GPIO<19>
GPIO<18>
GPIO<17>
GPIO<16>
A13
A12
B12
A11
B11
A10
B10
A9
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
B9
A8
B8
A7
F4
GPIO<15>
GPIO<14>
GPIO<13>
GPIO<12>
GPIO<11>
GPIO<10>
GPIO<9>
GPIO<8>
GPIO<7>
GPIO<6>
GPIO<5>
GPIO<4>
GPIO<3>
GPIO<2>
GPIO<1>
GPIO<0>
G2
F3
G1
F2
F1
D3
E2
D4
E1
D2
D1
C2
C1
B1
A1
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
General Purpose IO pin
Memory Card Interface (fixed: 3 pins)
MCI_DAT
MCI_CLK
MCI_CMD
A4
A2
B2
0-5 VDC tolerant
I/O
O
Data input/Data output
MCI clock output
0-5 VDC tolerant
I/O
Command input/Command output
USB Interface (fixed: 4 pins)
USB_DP
C17
A
A
O
I
Positive USB data line
Negative USB data line
Soft connect output
USB_DM
D17
D16
C15
USB_CONNECT_N
USB_VUSB
0-5 VDC tolerant
USB supply detection input
6 MHz oscillator (fixed: 4 pins)
XTAL1I
P4
R3
A
A
6MHz clock input
6MHz clock output
XTAL1O
2002 Jan 21
7
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
VDDA1
VSSA1
R2
Analog supply Oscillator 1
R1
Analog ground Oscillator 1
32.768 kHz oscillator (fixed: 4 pins)
XTAL2I
XTAL2O
VDDA2
VSSA2
N4
P3
P2
P1
A
A
32.768 kHz clock input
32.768 kHz clock output
Analog supply Oscillator 2
Analog ground Oscillator 2
Voltage Supply PLLs (fixed: 2 pins)
VDDA3
N2
N1
Analog supply PLLs
Analog ground PLLs
VSSA3
PLL (fixed: 1 pin)
CLKO1
F15
O
toggling
256fs clock output
Write Enable
LCD Interface (fixed: 13 pins)
LCD_WE
K3
O
O
LCD_RW_WR
A16
6800 read/write select
8080 active ‘high’ write enable
LCD_E_RD
B15
O
6800 active ‘low’ enable
8080 active ‘high’ write enable
LCD_DB<0>
LCD_DB<1>
LCD_DB<2>
LCD_DB<3>
LCD_DB<4>
LCD_DB<5>
LCD_DB<6>
LCD_DB<7>
LCD_CSB
D14
B17
C14
C16
D13
A17
C13
B16
C12
D12
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Data input 0/Data output 0
Data input 1/Data output 1
Data input 2/Data output 2
Data input 3/Data output 3
Data input 4/Data output 4
Data input 5/Data output 5/serial clock
Data input 6/Data output 6/Serial data input
Data input 7/Data output 7/Serial data output
Chip Select (active low)
LCD_RS
O
‘high’ Data register select
‘low’ Instruction register select
Parallel Port Interface (fixed: 18 pins) .. THIS FUNCTIONALITY HAS BEEN REMOVED!!
10-bit ADC (fixed: 12pins)
GPA<7>
GPA<6>
GPA<5>
GPA<4>
GPA<3>
GPA<2>
GPA<1>
GPA<0>
VREFP<1>
VREFP<0>
VDDA4
B7
A6
B6
A5
B5
J3
A
A
A
A
A
A
A
A
A
A
Analog General Purpose pin 7
Analog General Purpose pin 6
Analog General Purpose pin 5
Analog General Purpose pin 4
Analog General Purpose pin 3
Analog General Purpose pin 2
Analog General Purpose pin 1
Analog General Purpose pin 0
10-bit ADC Reference voltage 1
10-bit ADC Reference voltage 0
Analog supply 10-bit ADC
M4
N3
M3
L2
M2
M1
VSSA4
Analog ground 10-bit ADC
Remote Control (fixed: 2 pins)
DO<0>
K1
K2
O
I
Remote Control Data Output 0
Remote Control Data Input 0
DI<0>
0-5 VDC tolerant
0-5 VDC tolerant
IIS input (fixed: 3 pins)
BCKI1
J15
I
Bitclock input (external)
2002 Jan 21
8
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
WSI1
H15
G15
0-5 VDC tolerant
0-5 VDC tolerant
I
Wordselect input (external)
DATAI1
I
Serial data input (external)
IIS output (fixed: 3 pins)
BCKO1
WSO1
M14
F16
E16
O
O
O
Tri-state
Bitclock output (external)
Wordselect output (external)
Serial data output (external)
Tri-state
DATAO1
Output/Low
SPDIF output (fixed: 1 pin)
DATAO2_SPDIFO
JTAG (fixed: 5 pins)
JTAG_NTRST
E15
O
Serial data output (internal), SPDIF output
K15
U12
0-5 VDC tolerant
0-5 VDC tolerant
I
I
JTAG Reset Input
JTAG Clock Input
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
K16
T13
U13
0-5 VDC tolerant
0-5 VDC tolerant
I
I
JTAG Mode Select Input
JTAG Data Input
O
JTAG Data Output
IIC slave Interface (fixed: 3 pins)
SCL_SLAVE
SDA_SLAVE
A0_SLAVE
P12
R12
T12
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
I/O
I
Serial clock IIC Slave
Serial data IIC Slave
Address selection Slave
IIC master interface (fixed: 2 pins)
SDA_MASTER
R13
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
IIC data I/O line (open drain output)/
UART Serial Data Input
SCL_MASTER
P13
IIC clock line output/
UART Serial Data Output
CD Block Decoder (fixed: 10 pins)
CDB_CRQ_NERDY
C5
0-5 VDC tolerant
I
Communication request line/CD engine is ready to receive the next
frame
CDB_NCRST_NHRDY
CDB_CLAB
D5
C9
C7
C8
O
I
CD engine reset line/Host is ready to receive the next frame
IIS/EIAJ input bit clock
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
CDB_DAAB
I
IIS/EIAJ serial data
I
IIS/EIAJ word clock
CDB_WSAB
CDB_EFAB
D9
D8
D6
D7
C6
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
I
IIS/EIAJ error flags
CDB_V4_SUB
CDB_CFLAG_SBSY
CDB_SFSY
Versatile pin 4:single wire subcode/EIAJ subcode data bits
Absolute time sync/EIAJ subcode block sync
EIAJ subcode frame sync
I
I
CDB_RCK
O
EIAJ subcode clock output
EBI (fixed: 49 pins)
EBI_NCS<2>
EBI_NCS<1>
EBI_NCS<0>
EBI_SDNCS<0>
EBI_WEN
G16
T10
U10
H3
O
O
O
O
O
O
O
O
O
O
O
O
Chip Selected 2
Chip Selected 1
Chip Selected 0
External SDRAM selection1 and SDRAM selection0
Write enable not
EBI address
J2
EBI_A<20>
J16
H16
F14
G14
H14
J14
R9
EBI_A<19>
EBI address
EBI_A<18>
EBI address
EBI_A<17>
EBI address
EBI_A<16>
EBI address
EBI_A<15>
EBI address
EBI_A<14>
EBI address
2002 Jan 21
9
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
EBI_A<13>
T9
U9
R8
T8
O
O
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI address
EBI data
EBI_A<12>
EBI_A<11>
EBI_A<10>
EBI_A<9>
O
O
U8
P11
R7
P10
U7
P9
T7
O
EBI_A<8>
O
EBI_A<7>
O
EBI_A<6>
O
EBI_A<5>
O
EBI_A<4>
O
EBI_A<3>
O
EBI_A<2>
P8
R6
U6
T6
O
EBI_A<1>
O
EBI_A<0>
O
EBI_D<15>
EBI_D<14>
EBI_D<13>
EBI_D<12>
EBI_D<11>
EBI_D<10>
EBI_D<9>
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
U5
T5
EBI data
EBI data
U4
T4
EBI data
EBI data
U3
T3
EBI data
EBI data
EBI_D<8>
P7
U2
P6
U1
R5
T2
EBI data
EBI_D<7>
EBI data
EBI_D<6>
EBI data
EBI_D<5>
EBI data
EBI_D<4>
EBI data
EBI_D<3>
EBI data
EBI_D<2>
P5
T1
EBI data
EBI_D<1>
EBI data
EBI_D<0>
R4
J1
EBI data
EBI_SDCLKOUT
EBI_CKE<0>
EBI_DQM<1>
EBI_DQM<0>
EBI_NRAS
EBI_NCAS
EBI_NOE
SDRAM clock
H4
T11
U11
R10
R11
H2
O
SDRAM clock enable
SDRAM data mask 1
SDRAM data mask 0
SDRAM row address strobe
SDRAM column address strobe
EBI output enable
O
O
O
O
O
Test pins (3 pins)
TEST_DAT<3>
TEST_DAT<2>
TEST_DAT<1>
UART (fixed: 9 pins)
UART_IO_NRI
UART_DIR_TX
UART_REQ_RX
UART_RST_NRTS
UART_CLK
B3
A3
B4
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I/O
I/O
I/O
Data input/Data output
Data input/Data output
Data input/Data output
E14
D10
C10
C11
D11
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
O
I
O
I/O
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
UART_NCTS
B14
A15
B13
A14
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
I
UART_NDCD
UART_NDSR
UART_NDTR
I
O
Mode Selection pins SAA7750 (fixed: 3 pins)
MODE<2>
MODE<1>
MODE<0>
L16
M15
M16
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
I
I
Wake-up input pin SAA7750 (fixed: 1 pin)
WAKE_UP L1 0-5 VDC tolerant
Reset input pin SAA7750 (fixed: 1 pin)
NRESET_IN L15 0-5 VDC tolerant
Reset output pin SAA7750 (fixed: 1 pin)
RESET_OUT N16
Reset input pin SSA Audio Codec (fixed: 1 pin)
RESET N15 0-5 VDC tolerant
DAC SSA Audio Codec (fixed: 4 pins)
I
I
Wake up input pin
System Reset Input
O
I
Reset output
Reset input pin with pull-down for creating Power-On-Reset
VOUTL
P15
R16
R17
P16
A
A
Analog left output pin
Analog right output pin
Analog supply DAC
Analog ground DAC
VOUTR
VDDA(DA)
VSSA(DA)
Headphone Amplifier SSA Audio Codec (fixed: 5 pins)
VOUTL(HP)
VOUTR(HP)
VREF(HP)
VDDA(HP)
VSSA(HP)
T17
U17
T16
R15
U16
A
A
A
Analog left output pin
Analog right output pin
Analog reference output pin
Analog supply Headphone Driver
Analog ground Headphone Driver
ADC SSA Audio Codec (fixed: 8 pins)
VINL
M17
K17
H17
G17
J17
A
A
A
A
A
A
Left line input
VINR
Right line input
VINM
Microphone input
VADCP
VADCN
VREF
Positive Reference voltage ADC
Negative Reference voltage ADC
Reference voltages ADC
Analog supply ADC
P17
L17
N17
VDDA(AD)
VSSA(AD)
Analog ground ADC
Control pins SSA Audio Codec (fixed: 4 pins)
L3CLOCK_SCL
L3DATA_SDA
L3MODE_A0
P14
R14
U15
T15
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
0-5 VDC tolerant
I
I
I
I
L3 Clock/IIC clock input
L3 Data/IIC data input
L3 Mode/IIC address selection
Select pin for L3 (LOW) or IIC control (HIGH)
SELECT_L3_IIC
Test pin SSA Audio Codec (fixed: 1 pin)
TEST1 T14 0-5 VDC tolerant
Supplies SSA Audio Codec (fixed: 2 pins)
I
Test control pin
VDDD(CODEC)
VSSD (CODEC)
N14
U14
Digital supply Audio Codec
Digital ground Audio Codec
Supplies SSA Flash memory (fixed: 2 pins)
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
LFBGA
208
PIN
PIN STATE
AFTER
RESET
APPL.
FUNC
SYMBOL(1)
DIGITAL I/O LEVEL
DESCRIPTION
VDDD(FLASH)
VSSD (FLASH)
E17
F17
Digital supply Flash
Digital ground Flash
Digital supplies SAA7750 (fixed: 8 pins)
VDDI1
VSSIS1
VDDI2
VSSI2
VDDI3
VSSI3
VDDI4
VSSI4
L4
L3
Core supply SAA7750
Core ground and substrate SAA7750
Core supply SAA7750
Core ground SAA7750
Core supply SAA7750
Core ground SAA7750
Core supply SAA7750
Core ground SAA7750
G4
G3
E4
E3
C4
C3
Peripheral supplies SAA7750 (fixed: 4 pins)
VDDE3V3
VSSE3V3
VSSE3V3
VDDE2V5
VSSE2V5
J4
K4
Peripheral (I/O) supply SAA7750 (3.3V)
Peripheral (I/O) ground SAA7750
Peripheral (I/O) ground SAA7750
Peripheral (I/O) supply SAA7750 (2.5V)
Peripheral (I/O) ground SAA7750
H1
K14
L14
Not connected pins (fixed: 2 pins)
NC D15
Not connected
1. Pin positions are fixed.
2002 Jan 21
12
PHILIPSCONFIDENTIAL
Table 2 : pinning diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
B
C
D
E
GPIO<0>
GPIO<1>
GPIO<2>
GPIO<4>
GPIO<6>
MCI_CLK
TEST_DA
T<2>
MCI_DAT< GPA<4>
0>
GPA<6>
GPA<5>
GPIO<16> GPIO<18> GPIO<20> GPIO<22> GPIO<24> GPIO<26> GPIO<27> UART_nD
UART_nD
CD
RW_WR
DB<7>
DB<3>
DB<5>
DB<1>
TR
MCI_CMD TEST_DA
T<3>
TEST_DA
T<1>
GPA<3>
GPA<7>
DAAB
GPIO<17> GPIO<19> GPIO<21> GPIO<23> GPIO<25> UART_nD
UART_nC
TS
E_RD
VUSB
N.C.
SR
GPIO<3>
GPIO<5>
GPIO<8>
VSSI4
VDDI4
CRQ_nER RCK
D
WSAB
CLAB
EFAB
REQ_RX
RTRST_n
F
CSB
RS
DB<6>
DB<4>
DB<2>
USB_DPL
US
GPIO<9>
VSSI3
GPIO<7>
VDDI3
CRST_nH
RQ
CFLAG_S SFSY
BSF
V4_SUB
UART_DI
R_T
UART_CL
K
DB<0>
USB_CO
NNECT
USB_DMI
N
UART_IO_ SPDIFO
nF
DATAO1
VDD(F)
F
G
H
J
GPIO<10> GPIO<11> GPIO<13> GPIO<15>
A<18>
A<17>
A<16>
A<15>
CLK01
DATAI1
WSI1
WSO1
nCS_2
A<19>
A<20>
VSS(F)
VADCP
VINM
GPIO<12> GPIO<14> VSSI2
VDDI2
VSSE
nOE
SDnCS0
GPA<2>
WE
CKE0
DCLKO
DO<0>
WEN
DI<0>
VDDE3V3
WSSE3V3
BCKI1
VADCN
VINR
K
VDDE2V5 JTAG_nT
RST
JTAG_TM
S
L
M
N
P
R
T
WAKE_U
P
VREFP<0
>
VSSI1
VDDI1
GPA<1>
XTAL2i
XTAL1I
D<0>
VSSE2V5
BCK01
VDDD
nRESET_I MODE<2> VDDA(AD)
N
VSSA4
VSSA3
VSSA2
VSSA1
D<1>
VDDA4
VDDA3
VDDA2
VDDA1
D<3>
VREFP<1
>
MODE<1> JTAG_MO VINL
DE<0>
GPA<0>
XTAL2O
XTAL1O
D<9>
RESET
RESET_O VSSA(AD)
UT
D<2>
D<6>
A<1>
D<16>
A<0>
D<8>
A<7>
A<3>
A<5>
A<2>
A<4>
A<6>
A<8>
SCL_SLA
VE
SCL_M
SDA_M
L3CLOCK VOUTL
L3DATA VDD(HP)
VSSA(DA) VREF
D<4>
A<11>
A<10>
A<9>
A<14>
A<13>
A<12>
nRAS
nCAS
SDA_SLA
VE
VOUTR
VDDA(DA)
D<11>
D<12>
D<13>
D<14>
nCS<1>
nCS<0>
DQM<1>
DQM<0>
AO_SLAV
E
JTAG_TDI TEST1
SEL_L3_II VREFHP
C
VOUTL-H
P
U
D<5>
D<7>
D<10>
JTAG_TC
K
JTAG_TD
O
VSSD
14
L3MODE
VSS(HP)
VOUTR-H
P
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
Note: the pins which which have been changed between the version N1A, N1B, N1C and the final version N1D of the IC have been marked with RED.
The pins which were changed and changed from digital to analog are marked with BLUE.
There is one pin (pin D15) which is left open.
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
7
HARDWARE DESCRIPTION SAA7750
ARM720T microcontroller
7.1
Quick reference:
• High performance low power ARM7TDMI based 32-bit RISC processor
• ARM 16-bit Thumb instruction set
• 8 KByte Unified Cache
• Memory Management Unit (MMU) giving full virtual memory and fast context switching support
• 32-bit register bank
• 32-bit ALU for RISC performance
• 32-bit shifter
• 32-bit addressing (no paging required above 64KByte)
• 32 x 8 DSP multiplier for signal processing
• Embedded ICE logic for debug
• Maximum ARM core clock frequency is 72MHz.
7.1.1
OVERVIEW
ARM720T is a general-purpose 32-bit microprocessor with 8KB cache, enlarged write buffer and Memory Management
Unit (MMU) combined in a single core. The CPU within ARM720T is the ARM7TDMI. The ARM720T is software
compatible with the ARM processor family.
ARM720T is a fully static part and has been designed to minimize power requirements. This makes it ideal for portable
applications, where both these features are essential.
The ARM720T architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are greatly simplified compared with micro programmed Complex Instruction Set Computers
(CISC).
The MMU’s mixed data and instruction cache, together with the write buffer, substantially raise the average execution
speed and reduce the average amount of memory bandwidth required by the processor. This means that there is a
minimal performance loss, when using ‘slow’ DRAM and ‘slow’ internal flash memory.
The memory interface has been designed to allow the performance potential to be realized without incurring high costs
in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented
in standard low-power logic, and these control signals permit the exploitation of paged mode access offered by industry
standard DRAMs.
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
7.1.2
BLOCK DIAGRAM
Virtual Address Bus
JTAG
Debug
Interface
ARM7TDMI
CPU
8 KB Cache
MMU
Coprocessor
Interface
Internal Data Bus
Data and
Address
Buffers
Control and
Clocking
Logic
System
Control
Coprocessor
AMBA Interface
AMBA Bus
Interface
Fig. 2 ARM720T Block Diagram
7.1.3
THE THUMB CONCEPT
The THUMB instruction set is a subset of the ARM instruction set. The THUMB is designed to increase the performance
of ARM implementations that uses a 16-bit memory data bus, and may allow better code density than ARM instruction
set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining
most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible
because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM
processor connected to a 16-bit memory system.
Note: in standard operation accesses are 32-bit, only when executing via EBI the accesses are 16-bit.
2002 Jan 21
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Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
7.2
Memory controllers
TThe SAA7750 offers transparent memory-mapped access for the processor to static memory and SDRAM devices.
Refer to the application notes on the memory controller.
7.2.1
OVERVIEW
The memory interface consists of an external bus interface (EBI) that handles all data and address interfacing from the
SAA7750 to the outside world, and consists of two memory controllers. The first memory controller handles SRAM /
ROM. This controller is also known as Static Memory Controller (SMC). The second memory controller handles SDRAM
which is located externally. In Fig.3 on page 16 a block diagram of the SAA7750 memory interface is depicted.
AHB
CD Block
SDRAM
Decoder
External
Bus
Controller
control
sel
Interface
SDRAM
TIC
address + data
SRAM
sel
Static Memory
Controller
control
Fig. 3 Block diagram of SAA7750 memory interface
Note: the SDRAM and the SMC cannot be used together in one application since there is no arbitragion in the EBI to
control the priority between the two blocks and the refresh of the SDRAM in that case.
7.2.2
Static Memory Controller
Within the memory interface the Static Memory Controller (SMC) is one the controllers which communicates with the
External Bus Interface (EBI). This static memory controller can control up to four independent memory or expansion
banks simultaneously. Those memories can be SRAM, ROM, FLASH or off-chip located peripherals. Each bank is 64
MByte, where the Static Memory Controller can handle all of the six main functions:
• Memory bank selection: support of 8 memory banks (64MByte each)
• Little Endian system
• Programmable wait states for read and write access:
– 1...32 wait states for standard memory access
– 0...15 wait states for burst mode reads from ROMs
• Supports sequential access burst reads of up to four consecutive locations in 8-, 16-, or 32-bit memories
• byte lane write control
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
• external bus interface
7.2.3
SDRAM Interface Controller
The SDRAM interface also known as Dynamic Memory Controller (DMC) has one port connection which is connected to
the AHB system bus. This connection interfaces to the main SDRAM control engine and the External Bus Interface. The
SDRAM control engine generates an efficient sequence of commands, to issue to the SDRAMs to transfer the requested
data. A block diagram of the memory interface is depicted in Fig.3 on page 16 . The SDRAM controller provides the
following features:
• Support for four banks of external SDRAM
• The width of each SDRAM bank can be either 8 or 16 bits
• Fast page-mode access support
• Byte, half word and word transaction support
• SDRAM refresh controller using CAS-before-RAS (CBR) refresh, hidden refresh or RAS-only refresh
• Auto pre-charge SDRAM accesses
• Shutdown mode where all SDRAM accesses (including refresh) are disabled. This state is compatible with self-refresh
devices.
• Power down mode where all SDRAM accesses are disabled and all SDRAM control lines are driven low. This mode
can be used to remove supply power from the SDRAM devices.
7.2.4
Internal Memory Controller
The internal memory is made up of two units, a bank of SRAM and one bank of ROM. The internal memory controller
allows the wait states of the SRAM and ROM to be controlled.
Embedded SRAM:
• 64KByte embedded SRAM (16K x 32)
• Supports byte, half-word and word access.
Embedded ROM:
• 256KByte embedded program ROM (64K x 32)
7.2.5
FLASH MEMORY CONTROLLER
The FLASH memory controller takes care of programming, erasing and reading the internal 384 KB FLASH memory.
7.2.5.1
FLASH reads
Any reads from the FLASH via the AHB will be handled automatically by the slave interface using the programmed
number of wait states from the ‘RdWaitCycles’ of the FLASHWS register.
If the FLASH interface is in write mode when the AHB FLASH read is attempted then an abort will be generated. This
means that the FLASH can’t be programmed when the CPU is running code from FLASH. The default mode is FLASH
read, with 8 wait states. Any writes to this area of the SSA memory map will generate an abort.
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
7.2.5.2
Erasing the FLASH block
Erasing (part) of the flash is necessary if the FLASH already contains data on the location that needs to be written.
Erasing can be done in two ways: sector erase and mass erase.
7.2.5.3
Programming the FLASH block
Before writing words into the FLASH, ensure that the respective addresses are empty (erased). Writing to a non-empty
address will result in invalid data on that location.
7.2.5.4
Operating conditions
Reading from the FLASH ROM can be done at any AHB speed. The number of programmed wait states is: 42 ns/ <HCLK
cycle time>, rounded upwards. The number of CPU cycles for each read is 1+ <programmed WS>
The maximum bus speed for programming and erasing the FLASH is 48 Mhz;
A Mass erase takes 101 ms at this speed
A Sector erase takes 21 ms at this speed
Programming a word takes 41 us at this speed
The minimum bus speed for programming is 24 Mhz.Programming/erasing at 24 Mhz takes twice as long as
programming at 48 Mhz.
The maximum time a sector can be accessed in write mode is 60 ms. If this is more, the data in this sector can be
corrupted. Software must take care not to exceed this value. Using speed optimized code for FLASH-writes is
recommended to keep programming time as short as possible.
7.3
Interrupt Controller
Refer to the application note “Interrupt handling SAA7750”.
OVERVIEW
The interrupt controller has the following features:
1. Status information about the interrupt source.
2. Separate enabling and disabling of interrupt sources.
3. Polarity and mode (edge/level) controlled interrupt source.
4. Software programmable FIQ/IRQ interrupt source.
7.3.1
FUNCTIONAL DESCRIPTION
The interrupt controller provides a simple software interface to the interrupt system. Certain interrupt bits are defined for
the basic functionality required in any system, while the remaining bits are available for use by other devices in any
particular implementation.
The ARM720T processor within the SAA7750 supports two levels of interrupts:
1. FIQ (Fast Interrupt Request) for fast, low hardware latency interrupt handling.
2. IRQ (Interrupt Request) for more general interrupts.
For the FIQ only a single source should be in use at any particular time. This interrupt provides a true low-latency
interrupt, because a single source ensures that the interrupt service routine may be executed directly without the need
to determine the source of the interrupt. It also reduces the interrupt latency because the extra banked registers within
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
the ARM720T core, which are available for FIQ interrupts, may be used to maximum efficiency by preventing the need
for a context save. For SAA7750 a multiple FIQ will be used to have more flexibility without a great loss of latency.
The IRQ interrupt controller uses a bit position for each different interrupt source. Bit positions are defined for sources
like, communication channels, timers, clock, etc. shared in different IRQ registers.
The interrupt controller is not based on hardware priority or does not provide any kind of interrupt vectors, because these
functions can be provided in the software.
7.4
Power Management Unit (PMU)
The Power Management and Reset Unit contains logic and registers used to support power management and to control
the reset behaviour of SAA7750. The power management mode can be divided into:
• Operating mode
• Stand-by mode
• Power down mode
The Power Management Unit can take care off a proper power-up and power-down sequence under software control.
All peripherals are controlled by the CPU. The CPU will request a power-down of a certain peripheral. After power-down
the PMU will acknowledge the power-down request to the ARM.
To power-up a device, the ARM will request this to the PMU. The PMU takes care of the sequence and as soon as the
peripheral is ready to receive data, the PMU will acknowledge the ARM for having a powered up peripheral.
If all peripherals are in powered down, including the ARM itself (power-down mode), the system can be wake-up via the
PMU. As soon as an external interrupt occurs, a wake-up signal is asynchronously send to the PMU. This causes the
PMU the enable all clocks of all peripherals and the clock of the CPU followed by generating an interrupt to the interrupt
controller. The CPU will return to the last entered mode and all peripherals which aren’t used in this specific mode can
be disabled on request by the CPU.
7.4.1
FUNCTIONAL DESCRIPTION
The Power Management Unit can be divided into 5 main modules (Fig.4), clock generation module, register module,
clock block, reset module and the power down module. The clock generation module serves all the derived clocks from
the two master input clocks with internal PLL modules. All the outputs are controlled by the clock register module to
enable or disable clocks in the main system. After selecting the clocks, the clock block takes care of hardwired overruling
(enabling/disabling) which is only needed in testmode or evaluation modes. The reset module controls the resetting of
blocks in the right way. The power down module controls the request/acknowledge mechanism to the CPU and can
control the clock register as well, e.g. switching modules in a certain sequence. The register module takes care that the
arm can write and read to the registers.
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
Clock Block
EXAMPLE OF SOME OF THE CLOCKS
Clock Generation
HCLK
OSC_6MHz
OSC_32KHz
ARM_PWD
&
PLL
PLL
PLL
PWD_HCLK_ARM
>
1
HCLK_ARM
TST_CLK
D
Q
TCB_TEST_CLK_SEL
CP
CONTROL_DIS
TCB_DIS_HCLK_ARM
&
1
TCB_CCTM_SEL
DIS_CLK_REG<1>
HCLK
*_PWD
&
Registers
PWD_HCLK_*
>
1
HCLK_*
TST_CLK
D
Q
TCB_TEST_CLK_SEL
APB-bus
CP
CONTROL_DIS
&
TCB_DIS_HCLK_*
1
DIS_CLK_REG<*>
TCB_CCTM_SEL
DSPCLK
*_PWD
&
PWD_DSPCLK_*
PowerDown module
Reset module
>
1
DSPCLK_*
TST_CLK
D
Q
TCB_TEST_CLK_SEL
wake-up
CP
CONTROL_DIS
interrupts
&
TCB_DIS_DSPCLK_*
1
TCB_CCTM_SEL
DIS_CLK_REG<*>
Fig. 4 PMU Block schematic
7.4.2
WAKE-UP BEHAVIOUR
If the system is setup properly, all the clocks can be shutdown. In this state the SAA7750 does consume minimum power.
Only the RTC is running (if enabled). The asynchronous part of the GPIO can receive a wake-up signal. This will trigger
the PMU to enable all clocks and to generate a wake-up interrupt to the ARM. The ARM should read the interrupt register
to determine that there was a wake-up interrupt. Related to this interrupt, the ARM needs to read the GPIO interrupt
register to determine who woke up the ARM and to handle the corresponding request. The following peripherals can
wake-up the complete system:
• GPIO pins (15:0), and GPIO pins (20,21,22,25,26)
• IIC slave interface
• External wake-up pad
• RTC Alarm
• CD-Block decoder
• Uart
• Remote control
• USB interface
7.4.3
WATCHDOG BEHAVIOUR
The watchdog has the functionality of resetting the complete system due to an external disturbance. In that case, it is
unknown which peripherals caused the lock, so the complete system needs a reset. In normal mode, the ARM will rewrite
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
the watchdog timer before it has timed out. As soon as the ARM is unable to rewrite the counter, the watchdog will request
a reset to the PMU. The PMU will reset the complete system, including all the peripherals and switch on all the clocks.
The power-on-reset (POR) bit will not be set and a watchdog request bit is set in the PMU. There is no interrupt
generated, because the interrupt controller has been reset.
7.4.4
PAUSE BEHAVIOUR
The pause behaviour is implemented as part of the standby mode. By enabling this bit, it is possible to keep all the
peripherals running and just prevent the ARM fetching instructions out of the memory. The pause can be retrieved by
either pressing the hardware reset or if any peripheral generates an interrupt (and the interrupt is enabled). The interrupt
controller will generate an IRQ or FIQ interrupt which is routed to both the ARM and PMU. The PMU will release the
pause bit and the ARM will start with the corresponding interrupt handler.
7.5
Reset module
Using the MODE<2> and MODE<1> pins, the boot mode of the SAA7750 can be set accoring to the following settings:
Table 3
MODE<2> MODE<1>
DESCRIPTION
Download mode => can be used for debugging
0
0
0
1
start executing from INTERNAL FLASH memory after initialisation and Remap according to
the internal ROM boot code
1
1
0
1
start executing from EXTERNAL ROM memory after initialisation and Remap according to
the internal ROM boot code
NO Remap will be done
7.6
Oscillators and clock generation
Refer to the application note “Clock and PLL settings in the SAA7750”.
7.6.1
Overview clock generation module
The clock generation module contains logic for generating all clock signals required in SAA7750. The clock generation
module consists of oscillators, PLL-based system clock synthesizers and dividers for generating several different clock
signals required by the other internal modules and a clock multiplexer to select between the generated clock from the
different inputs. The clock generation module is controlled by the PMU registers for enabling/disabling clocks, PLL
settings and clock selection control.
7.6.2
Functional Description
The clock generator contains two oscillators, one oscillator of 32.768kHz (for real time clock) and one oscillator of 6 MHz.
These oscillators are the base frequency for generating the rest of the main system frequencies.
Other system clocks will be generated by three PLL’s:
• One MASTER PLL to generate the clock frequency of 96MHz/48MHz/24MHz/12MHz and
64MHz/32MHz/16MHz/8MHz/4MHz/2MHz/1MHz/500kHz/250kHz/125kHz/62.5kHz/31.25kHz
• One Audio PLL to generate the 256fs and 128fs clock with the sample frequency’s 64kHzor 88.2kHz or 96 kHz. These
frequency’s can be divided by 1, 2, 4 or 8 to get other audio frequency(32kHz, 16kHz, 8kHz or 44.1kHz, 22.05kHz,
11.025kHz or 48kHz, 24kHz, 12kHz).
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•
One DSP PLL to generate other clock frequency for the ARM core or DSP core in the range from 8.5Mhz to 133MHz
The clock mux is a multiplexer which select depending on the control signals which of the input clock will be connected
to the output clock.
The register block takes care that the ARM can control what the frequency of the ARM, DSP and audio part will be and
what will be the source of the clock signals.
Note: the maximum speed of teh ARM core is 72MHz. The maximum frequency of the bus-clock and memory interface
bus is up to 48MHz.
7.7
Multi Media Card Interface (MMC)
The Multimedia Card Interface (MCI) is an advanced microcontroller bus architecture (AMBA) compliant peripheral.
The multimedia card system provides communications and data storage, and consists of:
• A multimedia card stack. This can consist of up to 30 cards on a single physical bus.
• A multimedia card controller: This is the multimedia card master, and provides an interface between the system bus
and the multimedia card bus.
The multimedia cards are grouped into three types according to their function:
• Read Only Memory(ROM) cards, containing a preprogrammed data.
• Read/Write(R/W) cards, used for mass storage.
• Input/Output(I/O) cards, used for communication.
The multimedia card system transfers commands and data using three signal lines:
• CLK: One bit transferred on both command and data lines with each clock cycle. The clock frequency varies between
0 MHz and 20 MHz.
• CMD: Bidirectional command channel that initializes a card and transfers commands. CMD has two operational
modes, first mode ‘open drain’ for initialization and second mode ‘push-pull’ for command transfer.
• DAT: Bidirectional data channel, operating in push-pull mode.
7.7.1
Choice of flash memory cards
There are two different types of FLASH memory: NAND FLASH and NOR FLASH. The two FLASH types lend
themselves to different applications. Basically NOR FLASH is a replacement for EPROM. NAND FLASH is a magnetic
media replacement, particularly suited to serial data.
Today’s FLASH cards are give in the table below.
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Table 4 Available FLASH Cards.
FLASH CARD
VENDOR
VCC
CAPACITY
INTERFACE
SIZE
SAA7750
Solid State Floppy Disk Card Toshiba &
2.7-3.6V
and 5V
...32 MByte available DOS file system
37 x 45 x
0.76
EBI
(SSFDC) or
Samsung
64 MByte Q2 1999
ATA (22-pins)
SmartMedia Card
Multi Media Card (MMC)
Hitachi Ltd. &
Infineon
Technologies
(open standard)
2.7-3.6V
16 MByte available
32 MByte Q3 1999
64 MByte 2000
SPI (7-pins)
32 x 24 x
1.40
MMC
interface
128 MByte 2001
Memory Stick (MS)
Sony (license
needed)
2.7-3.6V
...8 MByte available
16 MByte Q2 1999
Serial (10-pins)
50 x 21.5 x
2.8
no
no
Compact Flash Card (CFC)
SanDisk Corp.
3.3V/5V
tolerant
...64 MByte available DOS file system
ATA (50-pins)
42 x 36 x 3.3
The Pinning of the Multi Media Card is given in table 5
Table 5 Pinning of the Multi Media Card (3 pins)
PIN
SYMBOL
MCI_DAT
DESCRIPTION
A4
A2
B2
Data
MCI_CLK
MCI_CMD
Clock
Command/Response
7.8
10-bit ADC
Refer to the apllication note “the build-in 10 bits ADC of the SAA7750”.
OVERVIEW
This section specifies the ADC interface, which can be used e.g. for observing battery voltage and/or scanning resistive
key’s. The interface can be divided into 2 main modules, a 10 bit A/D converter and an ADC controller/multiplexer. The
A/D converter is a 10 bit successive approximation analog to digital converter.
The basic characteristics of the ADC interface module are:
• Eight analog input channels, selected by an analog multiplexer;
• Programmable ADC resolution from 2 to 10 bits;
Converted digital values are stored in a 2 * 10 bits register;
• Maximum conversion rate is 400Ksamples/s in 10bits accuracy and 1500Ksamples/s in 2 bits accuracy mode.
• Single A/D conversion scan mode and continuous A/D conversion scan mode;
• Power down mode.
7.8.1
FUNCTIONAL DESCRIPTION
The ADC is able to convert on of its 8 inputs from analog to digital in 10 bits with a conversion rate of 400Ksampls/s .
The resulution can be reduced till 2 bits and in that case the conversion speed can be increased to 1500Ksamples/s. The
ADC is composed of an analog 8:1 multiplexer to select the input to convert. One 10 bits conversion requires 11 ADC
clock cycles to complete. During the first cycle the selected input is sampled, in the next 10 cycles the sample is
converted into 10 bits.
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7.8.2
MULTI CHANNEL A/D CONVERSION SCAN
Associated to each analog input channel is a set of two 10 bits result registers for storage of A/D conversion result. It is
programmable which channels are included and which channels are excluded from the A/D conversion scan process.
The A/D conversion scan process can be started by software.
There are two scan modes, ‘Continuous Scan’ mode and ‘Single Scan’ mode:
• In ‘Continuous Scan’ mode, A/D conversion scans are carried out continuously: once one scan completed, the next
one is started automatically.
• In ‘Single Scan’ mode, only a single conversion scan is carried out, the next scan must be started explicitly by software.
7.8.3
ADC RESOLUTION
The resolution within the AD conversion process is software programmable through ADC controller variables. The
resolution can be adjust between 2 and 10 bits.
The conversion rate is computed as follows:
clockfrequency
conversionrate =
---------------------------------------------
(resolution + 1)
7.8.4
INTERRUPTS
The ADC interface implements one interrupt, a scan interrupt which indicates the completion of an A/D conversion scan
process and the validity of the data in the result registers.
7.9
UART
The UART can be used for connecting a Modem, Blue tooth IC or a terminal emulator to the SAA7750 IC.
Overview:
• 16 word wide transmit and receive FIFO’s
• Supports external modem peripheral
• Optional interface to external Philips Smartcard
• Build-in IrDA receiver
7.9.1
FUNCTIONAL DESCRIPTION
The receiver block, Rx, monitors the serial input line, SIN, for valid input. The Rx Shift Register (RSR) accepts valid
characters via SIN. After a valid character is assembled in the RSR, it is passed to the Rx Buffer Register FIFO to await
access by the CPU or host via the generic host interface.
The transmitter block, Tx, accepts data written by the CPU or host and buffers the data in the Tx Holding Register FIFO
(THR). The Tx Shift Register (TSR) reads the data stored in the THR and assembles the data to transmit via the serial
output pin, SOUT.
The Baud Rate Generator block, BRG, generates the timing enables used by the Tx block. The BRG clock input source
is either the APB clock, PCLK, or the UART clock, UCLK. The main clock is divided down per the divisor specified in the
DLL and DLM registers. This divided down clock is a 16x oversample clock, NBAUDOUT.
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The modem interface contains registers MCR and MSR. This interface is responsible for handshaking between a modem
peripheral and the UART.
The interrupt interface contains registers IER and IIR and controls the interrupt output pin, INTR. The interrupt interface
receives several one clock wide enables from the Tx, Rx and modem blocks.
Status information from the Tx and Rx is stored in the LSR. Control information for the Tx and Rx is stored in the LCR.
The build-in IrDA block can be enabled or disabled. If disabled, the UART signals pass through this block unchanged .
The build-in IrDA block operates over the entire range of 2.4kb/s up to 115.2kb/s.
7.10 General Purpose I/O
The General Purpose Input-Output (GPIO) module provides 16 external GPIO pins which can be independently
programmed to be input or output. This means that each pin has a data input/output bit, a data direction bit and a value
bit. The GPIOs can be used e.g. like push-buttons and detection switches.
• A maximum of 28 General Purpose pins externally
• Each General Purpose pin has an interrupt which can be dynamically configured:
– active high or low polarity
– edge or level sensitive
– masked or enabled
7.10.1 FUNCTIONAL DESCRIPTION
Interrupt
Controller
APB
SelGPIO
GPIO_IRQ
GPIO_FIQ
HclkGPIO_INT
GPIO-
Controller
APB
SelGPIO
32
32
GPIO_out Lines
GPIO_IN Lines
32
GPIO_Enable
HclkGPIO
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The GPIO module consists of two parts: The GPIO controller which functions as an input/output interface to the GPIO
lines, and an interrupt controller which checks the GPIO-lines for level and/or edge changes and generates an interrupt
to the CPU.
7.10.2 INTERRUPTS
Refer to the application note “Interrupt handling SAA7750”.
Each GPIO line can be configured to generate interrupts either as an FIQ or an IRQ. They can be level or edge sensitive
and either low/high active or Positive/negative edged.
The interrupt controller contains a raw status register where each GPIO line can be checked for an interrupt, independent
of masking. It contains a Status register, which contains the values after masking.
7.11 Real Time Clock (RTC)
• Measures passage of time to maintain calendar and clock
• Uses external 32.768kHz crystal
• Counts seconds, minutes, hours, days, and years with leap year correction
• Counter increment interrupt
• Alarm clock interrupt
The Real-Time Clock (RTC) module consists of a counter which increments at a frequency of typically 32.768kHz. The
RTC provide a set of counters to measure time during power on and power off operation. It is designed to use little power
consumption in power down mode.
7.11.1 FUNCTIONAL DESCRIPTION
The RTC interfaces to a standard APB with either a unidirectional or bidirectional data bus. The data bus is 32-bits wide
while the consolidated time registers are included to read all time counters with only three read operations.
The RTC uses a 32.768 kHz clock, that is divided down to a 1 Hz clock using a ripple counter. A ripple counter is used
to minimize power during power down mode.
The counter clock consists of the exclusive-or of the 1 Hz clock and the counter write strobe. During a non-write operation
the counters operate as a set of sequential counters clocked by the 1 Hz clock. During a write operation no event is
allowed on the 1 Hz clock. To insure this condition is true the user should disable the 1 Hz clock by setting the clock
enable bit (CR[0]) to zero before writing to the RTC.
Each counter has its count enable gated so that during a counter write operation no counter is increment by the clock
pulse generated by the write strobe. Two of the counters have dynamic maximum values, the Day of Month counter and
the Day of Year counter. These maximum values are determined via combinational logic whose inputs are the Year
counter (for leap year) and Month counter.
For determining a leap year, the RTC does a simple bit comparison to see if the two lowest order bits of the year counter
are zero. If true, then the RTC considers that year a leap year. A more accurate algorithm would prevent years evenly
divisible by 100, but not evenly divisible by 400, from being leap years (the year 2000 is a leap year, but 2100 is not).
The RTC considers all years evenly divisible by 4 as a leap year. This algorithm will be accurate until the year 2100.
2002 Jan 21
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Generic device for portable
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7.11.2 INTERRUPTS
Interrupt generation is controlled through the Counter Increment Interrupt Register (CIIR), the alarm registers, and the
Alarm Mask register (AMR). Interrupts are generated only by the transition into the interrupt state. Each bit in CIIR
corresponds to one of the time counters. If CIIR is enabled for a particular counter, then every time the counter is
increment an interrupt is generated. The alarm registers allow the user to specify a date and time for an interrupt to be
generated. The AMR provides a mechanism to mask alarm compares. If all non-masked alarm registers match the value
in their corresponding time counter, then an interrupt is generated.
7.11.3 POWER DOWN OPERATION
When the external signal pwr_up is active low the RTC goes into power down mode. In power down mode all bus
interface inputs are gated. Besides the first element in the ripple counter, and the optional alarm clock sampling flip flop,
all loads to the 32.768 KHz clock are gated to reduce power.
The user can optionally specify that the alarm compare interrupt output should remain active in power down mode to
allow for a power-on timer. If this option is selected, the alarm registers are included in the low power section of the
design. When powered down, the synchronizing clock for alarm comparison will be the 1 Hz clock. When powered up,
the bus clock is used to synchronize the alarm.
7.12 Timers
• Two independent 32-bit timers
• Can be programmed to interrupt the processor
• Can operate in either free running or periodic timer mode
The timer block contains two fully independant timers, where each timer has its own clock and chip-select. Each timer is
a 32 bit wide down-counter with selectable pre-scale. The pre-scaler allows either the system clock to be used directly,
or the clock divided by 16 or 256 may be used. This is provided by 0, 4 or 8 stages of pre-scale. Two modes of operation
are available, free-running and periodic timer. In periodic timer mode the counter will generate an interrupt at a constant
interval. In free-running mode the timer will overflow after reaching its zero value and continue to count down from the
maximum value.
Note: The timer speed depends on the system clock. The system clock can change depending the operation mode,
which means that the timer can not be used as a real time clock.
7.12.1 FUNCTIONAL DESCRIPTION
The timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a
count of zero an interrupt will be generated. The interrupt may be cleared by writing to the Clear register.
After reaching a zero count, if the timer is operating in free-running mode then the timer will continue to decrement from
its maximum value. If periodic timer mode is selected then the timer will reload from the Load register and continue to
decrement. In this mode the timer will effectively generate a periodic interrupt. The mode is selected by a bit in the Control
register.
At any point the current timer value may be read from the Value register.
At any point the timer_load may be re-written. This will cause the timer to restart to the timer_load value.
the timer is enabled by a bit in the control register. At reset the timer will be disabled, the interrupt will be cleared and the
Load register will be undefined. The mode and pre-scale value will also be undefined.
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The timer clock is generated by a pre-scale unit. The timer clock may be the system clock, the system clock divided by
16, which is generated by 4 bits of pre-scale, or the system clock divided by 256, which is generated by a total of 8 bits
of pre-scale.
7.12.2 INTERRUPTS
The timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On reaching a
count of zero an interrupt will be generated. The interrupt may be cleared by writing to the Clear register
7.13 Watchdog Timer
The watchdog block is of similar design to the existing timer block, except that in stead of interrupting the CPU, it provides
a reset request to the PMU and that it consists of only one timer.
Once the watchdog is enabled, it will monitor the programmed timeout period and generate a reset request when the
period expires. In normal operation the watchdog is triggered periodically, resetting the watchdog counter and ensuring
that no reset is generated. In the event of a software or hardware failure preventing the CPU from triggering the
watchdog, the timeout period will be exceeded and a reset requested from the PMU/reset control logic.
The reset request allows the PMU to select a default set of clocks, and reset the CPU subsystem.
7.13.1 FUNCTIONAL DESCRIPTION
The functional description is the same as that of the timer block. Mind that the watchdog only contains one timer!
7.13.2 INTERRUPTS
The watchdog timer is loaded by writing to the Load register and then, if enabled, the timer will count down to zero. On
reaching a count of zero an interrupt will be generated to the PMU.
7.14 IIC master Interface
The I2C master module provides a serial interface that meets the I2C bus specification and supports all transfer modes
from and to the I2C bus. It supports the following functionality:
• It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL).
• It has word (32-bits) access from the CPU side.
• Interrupt generation on received or sent byte (and some special cases).
• It has two modes of operation: master transmitter and master receiver.
• 16 8bits word wide transmit and receive FIFO’s
Important note: since 2 pins of the master IIC interface are shared with the pins of the CD-block decoder UART, the IIC
master interface cannot be used in cases in which the CD-block decoder UART is used!
7.14.1 FUNCTIONAL DESCRIPTION
The main features of the I2C-bus are:
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
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Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
• The I2C bus may be used for test and diagnostic purpose
Two wires, SDA (serial data) and SCL (serial clock) carry information between devices connected to the I2C bus. Each
device can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters
and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the
device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device
addressed by a master is considered a slave.
Generation of clock signals on the I2C bus is always the responsibility of the master device; each master generates its
own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are
stretched by a slow-slave device holding down the clock line, or by another master when arbitration occurs.
7.14.2 INTERRUPT
Active low signal indicates if an interrupt is pending. The reason for the interrupt is encoded in Status Register. There
are several possible interrupt types: transfer completed, arbitration failure, missing acknowledge, need more data, Tx
FIFO has room for more data, or data has been received.
7.15 IIC slave Interface
The I2C Slave module provides a serial interface that meets the I2C bus specification and supports all transfer modes
from and to the I2C bus. It supports the following functionality:
• It supports both the normal mode (100 kHz SCL) and the fast mode (400 kHz SCL).
• It has word (32-bits) access from the CPU side.
• Interrupt generation on received or sent byte (and some special cases).
• It has two modes of operation: slave transmitter and slave receiver.
7.15.1 FUNCTIONAL DESCRIPTION
The main features of the I2C-bus are:
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
• The I2C bus may be used for test and diagnostic purpose
Two wires, SDA (serial data) and SCL (serial clock) carry information between devices connected to the I2C bus. Each
device can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters
and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the
device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Any device
addresses by a master is considered a slave.
Generation of clock signals on the I2C bus is always the responsibility of the master device; each master generates its
own clock signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are
stretched by a slow-slave device holding down the clock line, or by another master when arbitration occurs.
2002 Jan 21
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PHILIPSCONFIDENTIAL
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7.15.2 INTERRUPT
Active low signal indicates if an interrupt is pending. The reason for the interrupt is encoded in Status Register. There
are several possible interrupt types: transfer completed, arbitration failure, missing acknowledge, need more data, Tx
FIFO has room for more data, or data has been received.
7.16 LCD Interface
The LCD interface contains logic to interface to a 6800/8080 compatible LCD controller. The LCD interface is compatible
with the 6800 bus standard and the 8080 bus standard, with one address pin (RS) for selecting the data or instruction
register.
The LCD interface contains a couple of options to delay the access on the 6800/8080 bus, if the specific controller
requires it.
7.16.1 INTERFACE
• 8/4 bit parallel interface mode: 6800-series, 8080-series
• Supports multiple frequencies for the 6800/8080 bus, to support high and low speed controllers
• Supports a maximum of 16 wait states on lcd-bus actions
• Supports polling the busy flag from LCD controller to off-load the CPU from polling
• Contains an 16 byte FIFO for sending control and data information to the LCD controller
• Contains a serial interface which uses the same FIFO for serial transmissions.
• Contains maskable interrupts.
7.16.2 SYSTEM INTERFACE
Table 6 Various modes of the LCD interface
RW_W
PS
MI
IF
CSB
RS
E_RD DB0-3
DB4-
DB5
DB6
DB7
R
Bus
mode
(L)
6800-ser 8 bit (L)
CSB
CSB
CSB
CSB
CSB
RS
RS
RS
RS
RS
nR/W
nR/W
nWR
nWR
*
E
E
DB0-3
DB4
DB4
DB4
DB4
*
DB5
DB5
DB5
DB5
SCL
DB6
DB6
DB6
DB6
SI
DB7
DB7
DB7
DB7
SO
ies (H)
4 bit (H)
*
8080-ser 8 bit (L)
nRD
nRD
*
DB0-3
ies (L)
4 bit (H)
*
*
Serial
mode
(H)
*
*
Note:
1. * Don’t care (“High”, ”Low” or “Open”)
PS = Parallel/Serial mode
CSB = Chip Select. Default low active
IF = 4 or 8-bit mode
MI = Motorola/Intel mode
RS = Register Select (also seen as A0)
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E_RD = Enable / Read. Enable in 6800 mode, Read in 8080 mode.
RW_WR = ReadWrite / WRITE. Read/write in 6800 mode, Write in 8080 mode.
DB(7-0) = Data Bus.
SCL = Serial CLock.
SI = Serial Input.
SO = Serial Output.
7.16.3 RESETTING THE LCD CONTROLLER
Not all LCD controllers require a reset pin to reset the controller. In some cases a simple instruction to the controller is
enough to perform the reset.
A GPIO pin, or maybe the system reset can be used to act as a reset signal for the LCD controller, if it requires a hardware
reset pin.
7.16.4 OPERATIONAL MODES
The LCD_interface has three modes for outputting data: Byte-mode, 4-bit mode and serial-mode.
Byte mode:
At each shift of the FIFO, the last byte from the FIFO will be put on the data pins, and pin RS will indicate if the data is
an instruction or data value.
In read mode the data on pins DB_IN 7-0 will be sampled by the LCD_interface.
4-bit mode:
At each shift of the FIFO, the last byte from the FIFO will be split, where the order depends on the ‘MSB_first’ from the
control register.
When set to ‘1’, bit 7-4 from the FIFO byte will be put first, or read first, at the data pins, and then bit 3-0.
When set to ‘0’ bits 3-0 will be written or read first, and then bits 7-4.
7.16.5 SERIAL MODE:
At each shift of the FIFO the last FIFO byte will be split in 8 separate bits and be put on data pin 7, where the order
depends on the ‘MSB_first’ from the control register.
When set to ‘0’, then first bit 0 and last bit 7 will be written or read first, else the order is from 7 downto 0.
Signal RS is included for each 8 bits and indicates a instruction or data. Not all controllers require this signal in serial
mode, but can be used if required.
7.16.6 LOOPBACK MODE
Setting the register ‘LOOPBACK’ of the CONTROL register to ‘1’, will set the LCD interface in loopback-mode.
Internally, the LCD data output is connected to the LCD data input. The programmer can test correct behaviour of the
LCD interface, by doing the following:
• Place the LCD interface in parallel, 8-bit mode
• Write a single byte to the LCD_DATA_BYTE register
• Write ‘0x01’ to the LCD_READ_CMD register to request a bus read
• Poll the status bit, or wait for the ‘valid’ interrupt (if MASK is cleared)
• If valid, read the byte from LCD_DATA_BYTE register
• Compare this value with the written value
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7.16.7 INTERRUPT
An interrupt is generated on the following occasions:
• When the FIFO is empty (LCD_FIFO_EMPTY).
• When the FIFO is half empty. (LCD_FIFO_HALF_EMPTY)
• When the FIFO is overrun. (LCD_FIFO_OVERRUN)
• When the requested instruction/data register is valid. (LCD_READ_VALID)
Any of these interrupts can be masked individually to keep them from generating an interrupt to the CPU, by using the
LCD_INT_MASK register. The interrupts after masking can be read in the LCD_STATUS register. Writing a ‘1’ in the
mask register will mask the interrupt. The status of the interrupts without masking can be read in the ‘LCD_INT_RAW’
register
Clearing the interrupts:
An interrupt can be cleared by writing a ‘1’ to the respectable bit in the LCD_INT_CLR register. If the interrupt has not
been solved, for instance the FIFO is still empty, this will re-set the interrupt, when not masked.
2002 Jan 21
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7.17 Remote Control Interface
The remote control build into the SAA7750 is based on the discharge of a RC combination. Making different RC
combinations, key’s can be identified.
Key interface - Consists of DO and DI signals.
The key interface consists of an output pin, DO, which is a signal of high and low periods, similar to a clock.
Output pin, DO, when low, is used to discharge an RC network.
Input pin, DI, is sampled by the block to determine the time DI remains low.
NOTE: A sample is the time DI pin i
s low. Normally DO is used to discharge a RC network. DO going low will discharge the Capacitor and the time it takes
to recharge is monitored by DI.
7.18 USB Interface
7.18.1 OVERVIEW
The SAA7750 USB interface can be used for:
• Down load bulk audio data (compressed) from a PC to the application with the SAA7750
• Download new firmwarde from a PC into the build-in program FLASH
• Up load speech or audio from a (analog) source to a PC
7.18.2 FUNCTIONAL DESCRIPTION
The USB interface for SAA7750 is a full speed USB interface (12Mbits/s) and is USB 1.1 compliant. It consist of an
analog transceiver (ATX), and a Full Speed USB module (FS22).
• USB 1.1 compliant interface
• Supports bus-powered or self-powered operation (programmable)
• One full duplex control end points (8 bytes)
• Two full duplex interrupt end points (16 bytes)
• One full duplex bulk end point (64 bytes, double buffered)
• One full duplex isochronous end point (294 bytes, double buffered)
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USB_Vbus
3.3 Volt
USB_Vbus
USB_Connect_N
USB_int_Req_FIQ
USB_int_Req_IRQ
1.5 kOhm
ATX
APB
DP
USB
interface
DM
The USB_Connect_N line can be used in the situation where internal initialisation of the USB device is longer than the
time needed according to USB specification:
“120ms after detection by the host of a USB device, the USB device should start responding to the transaction on the
USB”.
A USB_Connect_N line can be used to switch the external pull-up resistor of 1.5kOhm under software control.
7.18.3 INTERRUPTS
There are two interrupts to the system:
• USB_int_req_FIQ
• USB_int_req_IRQ
7.18.3.1 USB_int_req_FIQ
This is the high priority interrupt to the system. The frame interrupt, Bulk OUT interrupt or Bulk IN interrupt can be routed
to generate the FIQ. It is a must that this interrupt should have only one source at a time.
7.18.3.2 USB_int_req_IRQ
This is the low priority interrupt to the system. The data transfer for all end points other than the FIQ source is initiated
through this interrupt. This interrupt has got multiple sources, sources different from the source that created the FIQ at
that point in time.
7.18.3.3 Interrupt handling
When CPU gets FIQ interrupt it does not need to read the status register as there is only one source for it depending on
the selection of the FIQ select register. In the service routine CPU has to clear the interrupt by writing ‘1’ into bit position
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Generic device for portable
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‘0’ of intr_clear_register but when it gets the IRQ interrupt it has to read the Interrupt status register and understand which
interrupt bit is set. The service routine has to clear the corresponding interrupt. If it is an interrupt from USB core (Bit 1
to Bit 8 of Status register) the clear interrupt command to the USB core must also be executed.
7.18.3.4 Zero overhead operation
To read the data without software overhead the CPU has to rely on the end_of_packet interrupt. The CPU can go on
reading the receive data register and the read operation is to be terminated when the end of packet interrupt occurs.
Hence the software does not have to track how many bytes it transferred. Still the number of bytes information is needed
to remove the garbage bytes read.
7.19 CD Block Decoder
The CD decoder block enables the SSA chip to playback from an audio CD or an MP3 CD. Major functionality’s of this
block include various data interfaces, a minimal block decoder, a buffer manager and an SDRAM controller. External CD
engine is controlled through the serial command interface (IIC or UART) and disc data comes in through the serial data
interface in either IIS or EIAJ format and the subcode interface in either V4 or EIAJ format. The minimal decoder detects
sync and frame address and performs necessary error detection and descrambling. The buffer manager maintains read
and write pointers and stores data in the data buffer (SDRAM) through the SDRAM controller.
This report provides proposed features and functional descriptions of the CD decoder block. Register addresses are
aligned to word (32-bit) boundary to facilitate accesses from the CPU.
7.19.1 FUNCTIONAL DESCRIPTION
7.19.1.1 Features
• Support of CD-DA mode, CD-ROM Yellow book and CD-ROM XA.
• CRC Q-subcode error detection.
• EDC C3 error detection to enable optional software correction through use of C2 error flag.
• Scratch pad random access area in SDRAM for use by the CPU.
• CD-DA seamless playback enables Constant-Angular-Velocity (CAV) drive compatibility
• I2C master(1) and UART command interfaces with CD engine. Configurable UART baud rate.
• Support of I2S/EIAJ with error flags.
• V4/EIAJ subcode interface.
• Hardware extraction of formatted Q-channel subcode.
• Support of 16Mbit or 64Mbit SDRAM chips with 8- or 16-bit data bus.
• Clock of the CD decoder block can be stopped and resumed to save power.
• Support of CD-TEXT mode.
Important note: the CD-block decoder has a PRIVITEpath to the SDRAM, having priority on the EBI over the ARM. This
means that the CD block decoder can ALWAYS access the SDRAM. It also means that in all applications there MUST
be an external SDRAM!
(1) An I2C slave also exists in the SSA system for connection to the user interface.
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Block Diagram(1)
I2C Slave
FRONT
PANEL
(VLSI)
I2C Master
(VLSI)
CDM-M5
APB
I2C / UART
4
Minimal
UART
Micro-
Controller
I2S / EIAJ
V4 / EIAJ
4
Minimal
Decoder
CD10
4
AHB to APB
Bridge
Buffer
Manager
AHB master
CD-Decoder
IRQ
AHB
AHB slave
12
16
ADDR
DQ
SDRAM
Controller
SDRAM
CTRL
7
(ARM PL170)
SSA
Fig. 8 CD-BLOCKDECODER DIAGRAM
7.19.2 INPUT/OUTPUT PIN FUNCTION
in table 7, the function of the pins of the CD blockdecoder are mentioned for both the IIC and the UART mode.
(1) CDM-M5 is a Philips CD engine that includes a microcontroller and a CD10 chip.
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Table 7 Input/Output Pin Function(1)
MODE 1 PIN
MODE 1
NAME
PIN
INPUT/
FUNCTION
NR
OUTPUT
MODE 2 PIN
MODE 2
NAME
R13 IIC
UART
P13 IIC
UART
IIC
SDA
RXD
SLK
TXD
CRQ
Input/Output
Input
IIC data I/O line (open-drain output)
UART Serial Data Input
Input/Output
Output
IIC clock line (open-drain output)
UART Serial Data Output
C5
D5
Input
Communication request line
CD engine is ready to receive the next frame
CD engine reset line
UART
IIC
ENGINE_RDY Input
CRST
Output
UART
HOST_RDY
Output
Host is ready to receive the next frame
Serial Data Interface
C9
C7
C8
D9
IIS or EIAJ CLAB
IIS or EIAJ DAAB
IIS or EIAJ WSAB
IIS or EIAJ EFAB
Input
Input
Input
Input
IIS/EIAJ input bit clock
IIS/EIAJ serial data
IIS/EIAJ word clock
IIS/EIAJ error flags
Subcode Interface
D8
D6
D7
C6
V4
V4
Input
Input
Input
Versatile pin 4: single wire subcode
EIAJ subcode data bits (3 wire)
Absolute time sync
EIAJ
V4
SUB
CFLAG
V4
Not used
SFSY
EIAJ
V4
Input
EIAJ subcode frame sync (3 wire)
EIAJ subcode clock input (3 wire)
Not used
RCK
EIAJ
Input/Output
7.19.3 I2C Interface
This is the communication interface between the CD decoder block and the CD engine. The CD decoder block represents
the I2C master and communicates with the CD engine. The interface signals consist of the two wires used by I2C
bus-SDA (serial data) and SCL (serial clock), a communication request line CRQ and a reset line (CRST). The CRQ line
is used by the CD engine to signal a message is ready to be read out. The CRST line resets the CD engine. The high-low
transition of CD engine insert line SENS_I is used for the detection of CD insertion.
Important note: since 2 pins of the IIC master interface and the CD-block decoder UART are combined, the use of IIC
master interface OR the UART are mutually exclusive!
(1) Pin name and function for different modes are listed for shared pins.
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7.19.4 Standard Serial Interface UART
The UART serial port in the CD decoder block is a full duplex interface. For each frame, 11 bits are transmitted (through
TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a parity bit and a stop bit (logic 1). Parity and
baud rate can be configured through the UART_CTRL registers (see table 207). Both transmit and receive have a
one-byte buffer that can be accessed through the UART_TX and the UART_RX registers, respectively. If enabled, an
interrupt is generated at each byte transmitted or received.
Baud rate is controlled through BaudRate field of UART_CONF1 register. It is effective for both transmit and receive. The
receive logic is able to tolerate a 5% baud-rate shift, provided that the HCLK frequency is correctly set in UART_CONF2
register.
All bits in UART_STATUS register can be cleared by writing a logic 1 to that bit, which also clears the interrupt associated
with that bit.
7.19.5 Subcode Interface
There are two subcode interfaces:
1. One that conforms to “EIAJ CP-2401” (using SBSY, SFSY, RCK and SUB) and can be configured as a 3 wire
interface. The interface formats are illustrated in Fig.9.
2. The Philips V4 format on V4 pin as illustrated in Fig.10. The subcode sync word is formed by a pause of 200 ms
minimum at nominal speed, where all subcode channels are muted. Each subcode byte starts with a 1 at the
P-channel bit position followed by 7 bits (Q to W), with P-channel bits discarded. The gap between two consecutive
bytes can vary from 11.3 ms to 90 ms.
The byte alignment is found by searching for a minimum gap of 200 ms (at nominal speed) on the V4 input. The gap is
counted against 12 rising edges of WSAB on the serial data interface (IIS or EIAJ). Once a start bit is detected, both
rising and falling edges of WSAB, in conjunction with CLAB, are used to synchronize the sampling of subcode data.
The 96-byte subcode data in a subcode frame is buffered in the subcode area of a 3KB buffer block. In addition, the 96-bit
Q-channel subcode is duplicated in a separate 12-byte area within the same block. The last 16 bits of the Q-channel
subcode are used internally to perform CRC.
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SF0
SF1
SF2
P-W
SF3
SF4
SF96
SF97
P-W
SF0
SF1
SFSY
RCK
SUB
P-W
P-W
EIAJ 3-wire subcode interface
SFSY
RCK
P
Q
R
S
T
U
V
W
SUB
Fig. 9 EIAJ Subcode Interface Format
11.3 ms
200 ms min.
(subcode sync)
11.3 µs min.
90ms max.
1
W96
Q1 R1
S1
T1
U1
V1
W1
1
Q2
P-channel bit replaced by ‘1’
Fig. 10 Philips V4 Subcode Format
In audio mode, the first flag bit, F1, of the CFLAG input pulses for every block thus defines the block boundary. The flag
is also called absolute time sync. The format of CFLAG is illustrated in Fig.11. Note that the audio sampling must
always start from the left channel, which follows a falling edge of WSAB in IIS mode or a rising edge of WSAB in EIAJ
mode.
11.3 ms
33.9 ms
(nominal speed )
1
1
F1
F2
F3
F4
F5
F6
F7
F8
Fig. 11 CFLAG Input Timing Diagram
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7.19.6 Serial Data Interface
The serial data interface can be switched between two modes: Philips I2S and the EIAJ format. In each case, the serial
data is transferred through a 3-wire interface: WSAB (word select), CLAB (serial clock) and DAAB (serial data). The
polarity of CLAB can be inverted. The fourth line, EFAB, indicates the C2 error flags that associates with each byte. The
error flags are stored in the data buffer and can be used for C3 error correction. For audio mode, EFAB has no meaning
as concealment is already performed within the engine. The timing of I2S and EIAJ is illustrated in Fig.12 on page 40 (1)
.
CLAB
DAAB
15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
1
0
WSAB
right
left
left LSB valid
right LSB valid
EFAB
(error flags)
right MSB valid
Philips I2S timing
CLAB
1
0
16 15 14 13 12 11 10 9
left
8 7 6 5 4 3 2 1 0
17
DAAB
WSAB
right
EFAB
EIAJ timing
Fig. 12 I2S and EIAJ Interface Timing
7.19.7 Minimal Block Decoder
This block accepts data from the serial data interface (I2S or EIAJ) and performs necessary word alignment,
synchronization, data descrambling and error detection for the type of data being read.
Four CD formats are supported:
•
•
The CD-DA format for audio playback. The MSF address is embedded in the Q-channel subcode. CRC is per-
formed on the Q-channel data and MSF information is de interleaved. The audio data has no block structure, how-
ever, the F1 flag is used to divide the data stream into 2352-byte blocks to facilitate data buffering. Error flags are
stored in the data buffer. Data descrambling must be disabled.
The CD-ROM Yellow Book Mode 1 format. The data frame structure is illustrated in Fig.48. The C3 check bytes,
including 172 P-parity bytes and 104 Q-parity bytes, along with the C2 error flags coming through EFAB line, are
(1) The IIS timing shown in Fig.12 is Philips 24-bit format, in which 24 CLAB cycles are contained within each half cycle of WSAB. There
are other formats that are being used, such as 16-bit and 32-bit formats. However, for all formats, the 16 data bits are always aligned
to the leading edge.
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saved in the buffer and can be used for software C3 correction if desired. Data descrambling is performed before
EDC. The four EDC bytes are generated from the sync pattern, the header, and the user data. EDC calculation is
performed by the minimal decoder to validate these data fields.
•
•
The CD-ROM XA Mode 2 Form 1. The data frame structure is illustrated in Fig.49. The form bit is included in both
copies of sub-header. For each block, two form bits are extracted from each copy of sub-header and then com-
pared. A mismatch is marked in the status field of the buffer block and also causes EDC failure since sub-header
is used for EDC calculation. Data descrambling is performed before EDC. Note that EDC for this format does not
cover the MSF address.
The CD-ROM XA Mode 2 Form 2. As shown in Fig.50, compared with Form 1 data, Form 2 blocks do not contain
C3 check bytes in exchange for more user data. The 4-byte EDC is not used for discs of this format. Descrambling
and form bits extraction are performed in the same way as in Form 1. Sub-header mismatch is marked in the sta-
tus field of the corresponding buffer block.
Format of an MP3 disc can be either CD-ROM Yellow Book Mode 1 or CD-ROM XA Mode 2 Form 1.
For CD-ROM modes, the EDC polynomial for a data frame is: G(x) = X32+X31+X16+X15+X4+X3+X+1. An EDC failure is
indicated in the status field of the buffer block.
The 16-bit CRC of Q-subcode specifies a Cyclic Redundancy Check character computed over the CONTROL, ADR and
DATA-Q fields. The field contains the inverted parity bits. The most significant bit of the CRC is in bit 81. The CRC
generation polynomial is: P(x) = X16+X12+X5+1.
A flywheel circuit is needed to interpolate a data frame sync if the sync pattern is not seen at the expected time. Some
protection against spurious sync pattern is also needed by only allowing the sync pattern detector to operate within a
small window which encompasses the expected time for the sync pattern. Address interpolation must be implemented.
Address interpolation is needed for Q-subcode frames as the MSF address information is only guaranteed to appear on
9 out of 10 consecutive frames while the other slots may contain UPC or MCN information.
If EDC is enabled in CD-ROM Yellow Book Mode 1 and CD-ROM XA Mode 2 Form 1, the block decoder will stop at any
data block that fails EDC if EDCFailStop bit is set; BUF_WR_PTR and BlockCnt values will remain as they were when
the last EDC-passed frame was buffered.
7.19.8 CD TEXT MODE
CD-TEXT data can be stored in the Lead-In Area and the Program Area and is read out from the disc through R-W
subcode channels. The structure of CD-TEXT data is illustrated in Fig.13
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Generic device for portable
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Text Group
Block 0
Text Group
Block 1
Text Group
Block 2
Text Group
Text Group
Block 3
max. 256 Packs
Pack (0)
Pack (1)
Pack (n)
n<=255
CRC
Header Field =
4 bytes
Text Data field =
12 bytes
field =
2 bytes
Fig. 13 Structure of CD-TEXT data
In CD-TEXT mode, R-W bits of subcode are de-interleaved (symbol to byte conversion) and saved into the buffer. Each
Pack occupies a 20-byte buffer area, with 18 bytes of data and 2 bytes of status, in which only bit 0 of the last byte is
used for CRC indication. CRC of CD-TEXT data uses the same algorithm as the CRC used in Q-channel subcode.
Note that in CD-TEXT mode, the Q-channel data can be accessed through Q_BUF registers.
7.19.9 Q-SUBCODE FRAME FORMAT
The general data format of Q-channel is illustrated in Fig.0. In all modes, the Q-channel subcode date can be read from
registers Q_BUF_0 through Q_BUF_5, each register contains two subcode bytes. See table 212 for the organization of
these registers. The Q_BUF registers are updated for each Q block sync detected and value of these registers belong
to the last Q block.
S0, S1 CONTROL
ADR
DATA-Q
CRC
S0, S1
96 bits
Fig. 0 General Q-Channel Data Format
• CONTROL: 4 flag bits to define the kind of information in a track, MSB first.
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• ADR: 4 control bits for DATA-Q, MSB first.
• DATA-Q: 72 data bits, MSB first.
• CRC: 16-bit CRC on CONTROL, ADR and DATA-Q. MSB first. On the disc the parity bits are inverted. The remainder
has to be checked at zero.
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7.20 Digital Signal Processor (EPICS7a)
In this chapter a description is given of the audio data flows between the ARm and the external world (with or without
DSP intervention) and of the control data flow between the ARM and the DSP.
DIO
Bypass
11
IFLAG
EPICS7A
XRAM
SPDIF_out
SPDIF out
4kx24
24
11
Clk
YRAM
Line-in L/R
Microphone
Microphone+
MCM
ADC frontend+
Decimator
4kx12
Audio-Codec
IISIN_1
12
DAI
DAO
IISOUT_1
24
12
DAO
DAI
PMEM
4kx32
Line-out L/R
SDAC+
Headphone L/R
headphone+
32
MPi_interface
Interpolator
IIC slave
IISIN_2
DAI
I/O FLAGS
IISOUT_2
DSP_REG
DAO
PC_RESET
etu_reg2
etu_reg1
BYPASS
DIO_CONTROL
IIC master
W
FIFO
R
FIFO
FIFO
FIFO
O
I
CTU
address
length
address
length
ARM720T
MTU
ATU
audio
ETU
memory
control
Fig. 15 AUDIO SUBSYSTEM
The DSP subsystem consists of the following main parts:
• 4K x 32 Program RAM (PRAM, field upgradable)
• 4K x 24 Data RAM (XRAM)
• 4K x 12 Coefficient RAM (YRAM, field upgradable)
• The EPICS Transfer Unit (ETU)
The ETU consist out of an Audio Transfer Unit (ATU) and a Memory Transfer Unit (MTU). The ATU is for transferring
the audio data between the CPU and the DIO. The MTU is for transferring data between the CPU and the DSP
memories.
• The DSP
The DSP (EPICS7a) is capable of processing all audio inputs and audio outputs of the DIO. The PMEM controls the
ROM/RAM access for the EPICS7a. The PMEM also allows the ETU controller to access this memory.
• The Digital Input Output (DIO) module
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The DIO consist of two IIS inputs (DAI) and two IIS outputs (DAO), connected to the Audio-codec Module. It contains
a SPDIF_output including channel-, user- and validity bits for transferring audio as well as CD-trackdata.
A bypass part is included in the DIO to allow the option of bypassing the DSP and let the CPU take control of the DIO
directly.
• The MPI interface
This part interfaces the MTU to the correct DSP memories.
• The DSP registers (DSP_REG)
The DSP registers indicates the SPDIF output status, user and validity bits and the selection bits of the DIO.
7.21 Digital Audio input and output
This part controls all digital inputs and outputs to and from the EPICS7A. All the audio streams are related to the same
sampling frequency which is generated by the master digital input source. If no digital input source is available, the
related signals are generated from the master system clock. All sources are feed to the DSP core via IO-addresses. The
DSP will read these addresses and process the data. After processing, the data is sent back to a DSP IO-address which
will go to a IIS output generator, a SPDIF channel output or to the CPU via the ATU. If the DSP is not used for
audio-processing, the DSP can be powered-down and put in bypass-mode. In this case a selection can be made to feed
any input to any output and the generator will generate the related signals.
The DIO system consist of the following blocks
• IIS input
This part is an IIS input. It generates a parallel data signal for left and right and a newsam signal. Depending on the
selection of the input the format will be IIS, LSB justified (16, 18, 20 and 24 bits) or MSB justified.
• IIS output
This part will generate an IIS output data stream and depending on the setting it will be a IIS, LSB justified (16, 18, 20
or 24 bits) or MSB justified output format
• SPDIF Output, which supports:
- Level II output
- Support of 32kHz, 44.1kHz and 48kHz output frequencies.
- Left and right channel status bits (40 bits per channel) can be set by the micro controller interface.
• BYPASS GEN
This part defines if the audio inputs will be send to the DSP or if they will be send directly to an audio output
– When bypass is disabled the ‘YMU’ signal and MODE signals to the LOGIC_block won’t be changed by the
BYPASS block
– When bypass is enabled the ‘YMU’ signal to the LOGIC_block depends on the register settings of the BYPASS
block. In these registers is stored which audio input is connected to which output. MODE and will always be ‘000000’
in bypass mode.
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8
HARDWARE DESCRIPTION BUILD-IN AUDIO CODEC
Refer to the application note “The SAA7750 build-in Audio Codec” and the “Application note: the Philips L3 interface”.
General
• 2.4 to 3.6 V power supply
• 5V tolerant digital inputs (at 2.4 to 3.6V power supply)
• 24bits datapath for ADC and DAC datapath
• Selectable control via L3 micro-controller interface or I2C interface control. Choice of 2 device addresses in L3 and I2C
mode.
• Supports sample frequencies from 8kHz to 55kHz for the ADC part, and 8kHz to 100kHz for the DAC part.
This means from the ADC point of view no DVD audio (e.g. 96kHz audio) can be supported for the ADC part.
For play-back 8kHz to 100kHz could be specified! = DVD playback is supported!
• Power management unit:
– separate power control for ADC, AVC, DAC headphone driver and PLL.
– analog blocks like ADC and PGA have a block to power down the bias circuits
– when ADC and/or DAC are powered down, also the clocks to these blocks are stopped to save power.
• ADC part and DAC part can run at different frequencies (either system clock or WSPLL)
• ADC and PGA plus integrated high pass filter to cancel DC offset
• The decimation filter is equipped with a digital Automatic Gain Control.
• mono microphone input with Low Noise Amplifier (LNA) of 26dB and VGA (Variable Gain Control) with 0 to 30dB gain
in 2dB steps.
• Integrated digital filter plus DAC
• separate single ended line output and one stereo Head Phone output, capable of driving 16Ω load. The headphone
driver has build-in short circuit protection circuit with status bits which can be read out from the L3/IIC interface.
• Digital silence detection
• Easy application
• build-in plop prevention circuitry for the line out and headphone driver output
Note: By default, when the IC is powered up, the complete chip will be in power down mode!
8.1
ADC front-end features
• ADC plus decimator can run at either PLL (regenerating the clock from WSI) or on SYSCLK.
• Stereo line in with PGA: gain range from 0dB till 24dB with 3dB steps
• Low Noise Amplifier with 29dB fixed gain for mono microphone input, including Variable Gain Amplifier with gain from
0dB till 30dB with 2dB steps
• Digital Left and Right independant volume control and mute in 0.5dB steps from +24dB gain till -63.5dB
8.2
DAC digital sound processing
• Separate digital logarithmic volume control for left and right channels via L3 or I2C from 0dB down to -78dB in steps of
0.25dB.
• Digital tone control, bass boost and treble via L3 or I2C
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• Digital de-emphasis for 32, 44.1, 48 and 96kHz fs via L3 or I2C
• cosine roll-off soft mute function
• Output signal polarity control via L3 or I2C
• Digital mixer for mixing ADC output signal and digital serial input signal (in case they run at the same sampling
frequency)
8.3
General description
The build-in audio Codec is a single chip stereo audio codec.
The build-in audio Codec front-end is equipped with a stereo line input which has PGA control, and a mono microphone
input with a Low Noise Amplifier (LNA) and a Variable Gain Control (VGA). The digital decimation filter is equipped with
an AGC which can be used in case of voice-recording.
The DAC part is equipped with a stereo line out and a headphone driver output. The headphone driver is capable of
driving a 16Ω load. The headphone driver is also capable of driving a headphone without the need for external DC
decoupling capacitors, since the headphone can be connected to a reference pin on the chip. In addition, there is a
built-in short circuit protection circuit for the headphone driver output which, in case of short circuit, limits the current
through the OPAMPs and signals the event via L3/I2C bits.
The build-in audio Codec also supports an application mode in which the codec itself is not running, but an analog signal,
like coming from an FM tuner, can be controlled in gain and output via the headphone driver and line outputs.
The build-in audio Codec has sound processing features in playback mode, de-emphasis, volume, mute, bass boost and
treble which can be controlled by micro-controller interface.
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8.4
Block diagram
VDDA(AD)VSSA(AD) VADCP VADCN
VREF
PGA
SDC
PGA
SDC
VINR
VINL
+26dB
Mic AMP
+ VGA
SDC
VINM
n.c.
ADC
ADC
VDDD
VSSD
RESET
DECIMATION FILTER
AGC
DC-CANCELLATION FILTER
L3CLOCK
L3MODE
L3/I2C-BUS
INTERFACE
DATA OUTPUT
INTERFACE
L3DATA
DATA INPUT
INTERFACE
select_L3_IIC
RTCB
DSP FEATURES
WSPLL
INTERPOLATION FILTER
NOISE SHAPER
ANA VC
ANA VC
FSDAC
FSDAC
VOUTR
VOUTL
HEADPHONE
DRIVER
HEADPHONE
DRIVER
VDD(DA)
VSS(DA)
VoutLHP
VrefHP
VoutRHP
VDD(HP)
VSS(HP)
Fig.1 Block diagram.
2002 Jan 21
48
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
9
HARDWARE DESCRIPTION FLASH
2002 Jan 21
49
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os
VI
DC input voltage range
DC output voltage range
output current
note 1
−0.5
−
−
4
5.0
V
V
VO
IO
−0.5
3.6
VDDE3V3 = 3.3 Volt
mA
Temperature values
Tj
junction temperature
0
−
125
+150
85
°C
°C
°C
Tstg
Tamb
storage temperature
−55
-40
−
operating ambient temperature
25
Electrostatic handling
Ves
electrostatic handling
HBM
MM
−2000
−250
−
−
+2000
+250
V
V
Note
1. All inputs are 5 Volt tolerant except for the USB pads.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
tbf
UNIT
Rthj-a
thermal resistance from junction to ambient
in free air
K/W
12 DC CHARACTERISTICS
VDDE(3V3) = 3.3 V; VDDE(2V5) = 2.5V; VDDI = 1.8 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply voltages
VDDE3V3
VDDE2V5
VDDI1
Peripheral (I/O) supply
SAA7750
3.0
2.2
1.6
1.6
1.6
1.6
3.3
2.5
1.8
1.8
1.8
1.8
3.6
2.8
2.0
2.0
2.0
2.0
V
V
V
V
V
V
Peripheral (I/O) supply
SAA7750
digital supply voltage 1
SAA7750
VDDI2
digital supply voltage 2
SAA7750
VDDI3
digital supply voltage 3
SAA7750
VDDI4
digital supply voltage 4
SAA7750
2002 Jan 21
50
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA1
analog supply voltage 1,
6 MHz xtal supply voltage
1.6
1.6
1.6
2.5
1.8
1.8
1.8
3.3
2.0
2.0
2.0
3.6
V
VDDA2
VDDA3
VDDA4
analog supply voltage 2,
32 kHz xtal supply voltage
V
V
V
analog supply voltage 3,
PLLs of SAA7750
analog supply voltage 4,
10-bit ADC supply voltage
VDDDF
digital supply voltage flash
digital supply voltage codec
2.2
2.4
2.4
2.5
3.3
3.3
2.8
3.6
3.6
V
V
V
VDDDC
VDDA(AD)
analog supply voltage ADC
of codec
VDDA(DA)
VDDA(HP)
analog supply voltage DAC
of codec
2.4
2.4
3.3
3.3
3.6
3.6
V
V
analog supply voltage
Headphone Driver of codec
Supply currents (depend heavily on the application)
IDDI1
IDDI2
IDDI3
IDDI4
IDDA1
digital supply current 1
SAA7750
−
−
−
−
tbf
tbf
tbf
tbf
−
−
−
−
mA
mA
mA
mA
digital supply current 2
SAA7750
digital supply current 3
SAA7750
digital supply current 4
SAA7750
analog supply current 1,
6 MHz xtal
Oscillation
−
−
−
−
−
−
−
−
−
−
−
−
−
−
300
−
−
µA
nA
µA
nA
mA
µA
µA
µA
mA
µA
mA
mA
mA
µA
Power down
Oscillation
10
2.5
1
IDDA2
IDDA3
IDDA4
IDDDF
IDDDC
analog supply current 2,
32 kHz xtal
1.5
−
Power down
Lock mode
Power down
Normal mode
Power down
analog supply current 3,
PLLs of SAA7750
3
-
−
3
analog supply current 4,
10-bit ADC
−
400
1
−
digital supply current flash Normal mode
Power down
15
−
-
10
−
digital supply current codec Playback mode
Recording mode
5.0
6.0
−
Full operational mode
10.0
4.0
−
Power down
−
2002 Jan 21
51
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IDDA(AD)
analog supply current ADC Speech recording mode
−
−
−
4.5
7.0
9.4
−
−
−
mA
mA
mA
of codec
Audio recording mode
Speech + Audio
recording mode
AVC only
Power down
−
−
−
−
−
3.15
2.0
3.4
2.0
3.5
−
−
−
−
−
mA
µA
IDDA(DA)
analog supply current DAC Normal mode
mA
µA
of codec
Power down
IDDA(HP)
analog supply current
Normal mode, no signal
mA
Headphone Driver of codec applied
Power down
−
2.0
−
µA
USB Interface (D+ and D−)
VIH
HIGH-level input voltage
(driven)
2.0
2.7
V
V
VIHZ
HIGH-level input voltage
(floating)
3.6
0.8
VIL
LOW-level input level
V
V
V
VDI
VCM
differential input sensitivity
0.2
0.8
differential common mode
range
2.5
0.3
3.6
2.0
VOL
LOW-level output voltage
RL = 1.425 kΩ
connected to VDD
0.0
2.8
1.3
V
V
V
VOH
VCRS
HIGH-level output voltage
(driven)
RL = 14.25 kΩ
connected to GND
output signal crossover
voltage
I2C-bus (SDA and SCL)
VIL
LOW-level input voltage
V
V
V
V
VIH
VOL
VOH
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
Digital input pins: 5V tolerant TTL compatible
VIL
VIH
ILI
LOW-level input voltage
HIGH-level input voltage
input leakage current
0.2*VDDE3V3
V
0.8*VDDE3V3
V
1.0
µA
Digital output pins
VOL
VOH
LOW-level output voltage
0.4
V
V
HIGH-level output voltage
0.85*VDDE3V3
10-bits ADC
Vin
input voltage
VSSA4
−
−
Vrefp
V
V
Vrefp
reference voltage
VSSA4+2.0
VDDA4
2002 Jan 21
52
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Rrefp
n
input impedance Vrefp
resolution
20
2
−
−
39
10
kΩ
bits
LSB
LSB
mV
mV
INL
DNL
OSe
FSe
Integral non linearity
Differential non linearity
Offset error
+/- 1
+/- 1
20
-20
-20
−
−
Full Scale error
20
LNA+VGA build in audio Codec
RI
CI
G
input resistance
−
12
24
−
−
kΩ
pF
dB
dB
input capacitance
gain control range
gain control step size
−
-
20
−
50
−
∆G
2
PGA SSA Codec
RI
CI
G
input resistance
−
−
0
-
12
tbf
-
−
kΩ
pF
dB
dB
input capacitance
gain control range
gain control step size
tbf
24
-
∆G
3
ADC build in audio Codec
Vref
reference voltage
with respect to VSSA(AD) 0.45VDDA(AD) 0.5VDDA(AD) 0.55VDDA(AD
V
V
V
)
VADCP
VADCN
positive reference voltage
of the audio ADC
−
−
VDDA(AD)
VSSA(AD)
−
−
negative reference voltage
of the audio ADC
Analog Volume Control build-in Codec
G
gain control range
-48
−
+16.5
dB
dB
dB
∆Gf
∆Gc
fine gain control step size
1.5
6.0
−
−
coarse gain control step
size
−
DAC build-in Codec
VOD(CM)
common mode output
−
0.5VDDA(DA)
−
V
voltage
Io(max)
RLD
maximum output current
load resistance DAC
load capacitance DAC
−
3
−
tbf
−
tbf
−
mA
kΩ
pF
CLD
−
50
Headphone Amplifier build-in Codec
VOH(CM)
common mode output
voltage
−
−
0.5VDDA(HP)
0.1
−
−
V
ROH(VOUT) output resistance at
VOUTL (HP) and
Ω
VOUTR(HP)
2002 Jan 21
53
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Io(max)
RLH
maximum output current
−
tbf
tbf
mA
load resistance Headphone
Driver
16
−
−
Ω
CLH
load capacitance
Headphone Driver
−
−
tbf
pF
2002 Jan 21
54
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
13 AC CHARACTERISTICS
VDDE(3V3) = 3.3 V; VDDE(2V5) = 2.5 V; VDDI = 2.5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP.
10-bit ADC dynamic characteristics
MAX.
UNIT
Fsmpl
sampling rate
400
−
1500
KS/s
(10 bits)
(2 bits)
tconv
conversion time
3
−
11
clk
(2 bits)
(10 bits)
cycles
Oscillator 1
fosc1
oscillator frequency
duty cycle
−
6
−
MHz
%
αosc1
−
50
tbf
−
Ci(XTAL1I)
parasitic input capacitance
XTAL1a
tbf
tbf
pF
Ci(XTAL1O)
parasitic input capacitance
XTAL2a
tbf
tbf
tbf
pF
tstart
start-up time
500
µs
Pdrive
crystal level of drive
100
500
µW
Oscillator 2
fosc2
αosc2
gm
oscillator frequency
duty cycle
−
32.768
50
−
kHz
%
−
−
transconductance
output resistance
tbf
tbf
tbf
tbf
tbf
tbf
tbf
mS
kΩ
pF
Ro
tbf
Ci(XTAL2I)
parasitic input capacitance
XTAL1a
tbf
Ci(XTAL2O)
parasitic input capacitance
XTAL2a
tbf
tbf
4
tbf
pF
tstart, avg
Pdrive
average start-up time
crystal level of drive
−
−
ms
0.5
1.5
µW
Analog-to-digital converter
Vi(rms)
input voltage (RMS value)
0 dB setting
−
−
−
−
−
−
−
−
−
−
1.0
−
−
−
−
−
−
−
−
−
−
V
3 dB setting
6 dB setting
9 dB setting
12 dB setting
15 dB setting
18 dB setting
21 dB setting
24 dB setting
708
501
354
252
178
125
89
mV
mV
mV
mV
mV
mV
mV
mV
dB
63
∆Vi
unbalance between channels
<0.1
2002 Jan 21
55
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
at 0 dB
MIN.
TYP.
MAX.
UNIT
(THD + N)/S48 total harmonic distortion plus
noise-to-signal ratio at
0 dB setting
3 dB setting
−
−
−
−
−
−
−
−
−
-85
−
−
−
−
−
−
−
−
−
dB
fs = 48 kHz
-85
-85
-85
-84
-83
-82
-80
-78
dB
dB
dB
dB
dB
dB
dB
dB
6 dB setting
9 dB setting
12 dB setting
15 dB setting
18 dB setting
21 dB setting
24 dB setting
at −60 dB; A-weighted
0 dB setting
−
−
−
−
−
−
−
−
−
−
−
-37
-36
-36
-36
-35
-34
-33
-32
-30
tbf
−
−
−
−
−
−
−
−
−
−
−
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
3 dB setting
6 dB setting
9 dB setting
12 dB setting
15 dB setting
18 dB setting
21 dB setting
24 dB setting
αs
channel separation
S/N48
signal-to-noise ratio at
fs = 48 kHz
Vi = 0 V; A-weighted
97
LNA input plus analog-to-digital converter
VI(rms)
input voltage (rms value)
−
−
−
−
−
−
35
−
mV
dB
dB
dB
dB
(THD+N)/S
total harmonic distortion plus
noise-to-signal ratio: fs=48kHz
at 0dB
-74
-25
85
70
at -60 dB; A-weighted
VI=0V; A-weighted
−
S/N
signal-to-noise: fs=48kHz
channel separation
−
αCS
−
Digital-to-analog converter
Vo(rms)
output voltage (RMS value)
at 0 dB (FS) digital
input
−
0.9
−
V
∆Vo
unbalance between channels
−
−
−
<0.1
−85
−40
−
−
−
dB
dB
dB
(THD+N)/S48 total harmonic
distortion-plus-noise to signal
at 0 dB
at −60 dB; A-weighted
ratio at fs = 48 kHz
(THD+N)/S96 total harmonic
at 0 dB
−
−
−80
−37
−
−
dB
dB
distortion-plus-noise to signal
ratio at fs = 96 kHz
at −60 dB; A-weighted
S/N48
signal-to-noise ratio at
fs = 48 kHz
code = 0; A-weighted
−
100
−
dB
2002 Jan 21
56
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
97
MAX.
UNIT
dB
S/N96
αcs
signal-to-noise at fs = 96 kHz
channel separation
code = 0; A-weighted
−
−
−
−
−
−
90
60
dB
dB
PSRR
power supply rejection ratio
fripple = 1 kHz;
Vripple = 30 mV (p-p)
Headphone driver build in Codec
PO(rms)
output power
at 0 dB (FS) digital
input, assuming 16Ω
load
−
22
−
mW
dB
(THD+N)/S
total harmonic distortion-
plus-noise to signal ratio:
fs=48kHz
at 0 dB, 16Ω loaded
at 0 dB, 5KΩ loaded
at -60 dB; A-weighted
code=0; A-weighted
−
−
−
−
−
-65
-85
-35
95
−
−
−
−
−
dB
dB
dB
S/N
signal-to-noise; fs=48kHz
channel separation
αCS
16Ω load, using
32
VREF(HP), no DC
decoupling capacitors
16Ω load, single-ended
with DC decoupling
capacitors (100uF
typical), note 1
−
56
−
dB
Analog volume control (line in via ADC input, output on line-out and Headphone driver)
VI(rms)
input voltage (rms value)
−
−
−
150
-80
-28
−
−
−
mV
dB
dB
(THD+N)/S
total harmonic distortion-
plus-noise to signal ratio at
fs=48kHz
at 0dB
at -60 dB; A-weighted
S/N
signal-to-noise: fs=48kHz
channel separation
VI=0V; A-weighted
−
−
87
82
−
−
dB
dB
αCS
2002 Jan 21
57
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
14 TIMING
VDDD = VDDA(ADC) = VDDA(DAC) = VDDA(HP) = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages referenced to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
USB Interface driver characteristics D+ and D- (full-speed mode)
tFR
rise time
CL = 50 pF
CL = 50 pF
4
−
−
−
−
20
ns
tFF
fall time
4
20
ns
%
Ω
tFRFM
ZDRV
rise/fall time matching (tFR/tFM
)
90
28
111.11
44
driver output resistance
steady-state drive
Serial interface input/output data timing (see Fig.2)
fBCK
bit clock frequency
bit clock cycle time
−
−
−
−
128fs
Hz
s
1
Tcy(BCK)
Tcy(s) = sample
⁄
128Tcy(s)
frequency cycle time
tBCKH
tBCKL
tr
bit clock HIGH time
bit clock LOW time
rise time
30
30
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
−
tf
fall time
−
tsu(WS)
th(WS)
tsu(DATAI)
th(DATAI)
th(DATAO)
word select set-up time
word select hold time
data input set-up time
data input hold time
data output hold time
10
10
10
10
0
−
−
−
−
td(DATAO-BCK) data output to bit clock delay
td(DATAO-WS) data output to word select delay
L3-bus interface timing (see Figs 3 and 4)
−
30
30
−
tr
rise time
note 2
note 2
note 3
−
−
−
−
−
−
−
−
10
10
−
ns/V
ns/V
ns
tf
fall time
Tcy(CLK)L3
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
500
250
250
190
−
ns
−
ns
L3MODE set-up time in address
mode
−
ns
th(L3)A
L3MODE hold time in address
mode
190
190
190
190
190
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
tsu(L3)D
th(L3)D
tstp(L3)
tsu(L3)DA
L3MODE set-up time in data
transfer mode
L3MODE hold time in data
transfer mode
L3MODE stop time in data
transfer mode
L3DATA set-up time in address
and data transfer mode
2002 Jan 21
58
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ns
th(L3)DA
L3DATA hold time in address and
data transfer mode
30
50
−
−
tsu(L3)R
th(L3)R
ten(L3)R
tdis(L3)R
L3DATA set-up time for read data
L3DATA hold time for read data
L3DATA enable time for read data
L3DATA disable time for read data
−
−
−
−
−
−
−
−
ns
ns
ns
ns
360
380
50
SDA and SCL lines (standard mode I2C-bus) 100kHz mode
fSCL
SCL clock frequency
0
−
−
−
−
100
−
kHz
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.0
tHIGH
tHD;STA
−
µs
hold time (repeated) START
condition
−
µs
tSU;STA
set-up time for a repeated START
condition
4.7
−
−
µs
tSU;STO
tBUF
set-up time for STOP condition
4.0
4.7
−
−
−
−
µs
µs
bus free time between a STOP
and START condition
tHD;DAT
tSU;DAT
tr
data hold time
5.0
250
−
−
−
−
0.9
−
µs
ns
ns
data set-up time
rise time of both SDA and SCL
signals
1000
tf
fall time of both SDA and SCL
signals
−
−
300
ns
SDA and SCL lines (standard mode I2C-bus) 400kHz mode
fSCL
SCL clock frequency
SCL LOW time
0
−
−
−
−
−
−
−
−
−
400
−
kHz
µs
µs
ns
ns
µs
µs
µs
µs
tLOW
tHIGH
tr
1.3
SCL HIGH time
0.6
−
rise time SDA and SCL
fall time SDA and SCL
hold time START condition
set-up time repeated START
set-up time STOP condition
note 4
note 4
note 5
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
−
tf
tHD;STA
tSU;STA
tSU;STO
tBUF
0.6
−
0.6
−
bus free time between a STOP
and START condition
1.3
−
tSU;DAT
tHD;DAT
tSP
data set-up time
100
0
−
−
−
−
−
ns
µs
ns
pF
data hold time
−
pulse width of spikes
capacitive load for each bus line
note 6
0
50
400
Cb
−
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency.
2002 Jan 21
59
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
2. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
small as possible.
3. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 1⁄64fs cycle.
4. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
5. After this period, the first clock pulse is generated.
6. To be suppressed by the input filter.
WS
t
BCKH
t
t
d(DATAO-BCK)
t
t
f
h(WS)
r
t
su(WS)
BCK
t
BCKL
t
t
h(DATAO)
d(DATAO-WS)
T
cy(BCK)
DATAO
DATAI
t
su(DATAI)
t
h(DATAI)
MGS756
Fig.2 Serial interface input data timing.
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
L3MODE
t
t
su(L3)A
h(L3)A
t
CLK(L3)L
t
t
t
CLK(L3)H
su(L3)A
h(L3)A
L3CLOCK
T
cy(CLK)(L3)
t
t
h(L3)DA
su(L3)DA
BIT 0
BIT 7
L3DATA
MGL723
Fig.3 Timing of address mode.
t
L3MODE
stp(L3)
t
CLK(L3)L
t
T
h(L3)D
cy(CLK)L3
t
t
CLK(L3)H
su(L3)D
L3CLOCK
t
su(L3)DA
BIT 0
t
h(L3)DA
L3DATA
write
BIT 7
L3DATA
read
t
t
dis(L3)R
t
en(L3)R
su(L3)R
t
h(L3)R
MGU015
Fig.4 Timing of data transfer mode for write and read.
2002 Jan 21
61
PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
SDA
t
t
t
t
t
t
SP
r
BUF
LOW
HD;STA
f
SCL
t
t
SU;ST
HD;STA
t
t
t
t
SU;DAT
SU;STA
HD;DAT
HIGH
P
S
Sr
MB
Fig.5 Timing of the I2C-bus transfer.
2002 Jan 21
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PHILIPSCONFIDENTIAL
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
16 SOLDERING
Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often
used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook” (order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SSOP packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between
50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following conditions must be observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm,
that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less
than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a
dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
2002 Jan 21
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PHILIPSCONFIDENTIAL
17 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Semiconductors
Preliminary Specification version 1.3
Generic device for portable
multimedia applications
SAA7750-N1D
18 DISCLAIMERS
Life support applications
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Philips Semiconductors for any damages resulting from such application.
Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or
performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or
warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2002 Jan 21
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PHILIPSCONFIDENTIAL
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