SAA8113HL_技术文档

INTEGRATED CIRCUITS

DATA SHEET

SAA8113HL

Digital PC-camera signal processor

Preliminary speciﬁcation

1999 Sep 27

File under Integrated Circuits, IC22

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

CONTENTS

1

2

3

4

5

6

7

8

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

8.1

8.2

8.3

Black offset preprocessing

Y, C_Rand C_Bseparation

RGB processing

8.4

Y processing

8.5

8.6

RGB to UV conversion

UV processing

8.7

Display function

8.8

8.9

Analog output processing

Measurement engine

VH reference and window timing and control

Pulse pattern generator

Miscellaneous functions

Mode control

Microcontroller

Audio amplifier

I²C-bus interface

8.10

8.11

8.12

8.13

8.14

8.15

8.16

9

LIMITING VALUES

10

11

12

13

14

15

15.1

THERMAL CHARACTERISTICS

OPERATING CHARACTERISTICS

ELECTRICAL CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount

packages

15.2

15.3

15.4

15.5

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for

wave and reflow soldering methods

16

17

18

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I²C COMPONENTS

1999 Sep 27

2

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

1

FEATURES

• High precision digital processing with 10-bit input

• Medium resolution complementary mosaic CCD

sensors PAL or NTSC (interlaced mode only)

• Internal PPG, dedicated to SHARP, TOSHIBA and

PANASONIC sensors

• Integrated microcontroller (80C51) for control loops

Auto Optical Black (AOB), Auto White Balance (AWB)

and Auto Exposure (AE)

3

GENERAL DESCRIPTION

The SAA8113HL is a 2nd generation camera Digital

Signal Processor (DSP) designed for low-cost DTV

applications. It integrates the DSP core, the Pulse Pattern

Generator (PPG), the 80C51 microcontroller and the

VDAC in one IC. It is the successor of the SAA8110G,

dedicated to analog output cameras.

• Black offset preprocessing

• RGB separation

• RGB processing (colour correction matrix,

programmable knee and gamma)

The SAA8113HL must be applied together with an analog

front-end that includes a Correlated Double Sampling

(CDS), an Automatic Gain Control (AGC) and an

Analog-to-Digital Converter (ADC). This may be the

TDA8786 or the TDA8784.

• Separate Y-processing (saturation concealment,

programmable knee and gamma)

• RGB to UV conversion (including down-sampling filters)

• Noise reduction in Y and UV

• Display function for system evaluation

The PPG generates the timing pulses to drive medium

resolution PAL/NTSC complementary mosaic CCD

sensors (512 × 492 NTSC and 512 × 582 PAL).

• Analog output processing, including PAL/NTSC encoder

and 9-bit Video Digital-to-Analog Converter (VDAC)

• Measurement engine (prepared for AE and AWB

features)

The input of the DSP is 10 bits with a maximum pixel

frequency equal to 9.66 MHz. The DSP core processes

this sensor signal to a standard video output signal. The

• Miscellaneous functions, e.g. power management, 7-bit

Control DAC (CDAC) serial interface with preprocessing SAA8113HL output is an analog CVBS video signal.

• VH reference and window timing for internal use

• Master I²C-bus interface for communication with an

external EEPROM (containing the default settings)

• Slave I²C-bus interface for communication with an

The microcontroller provides the settings for the IC

registers from EEPROM at power-up or reset and controls

the AWB, AE and AOB loops. It also provides a hardware

I²C-bus interface, so the microcontroller can be used as an

I²C-bus slave. The software code is embedded in an

internal ROM but it is also possible to use a combined data

and address bus, connected to an external program

EPROM.

external microcontroller

• Parallel interface for communication with an external

EPROM (for ROM code debugging)

• Integrated audio amplifier.

A built-in power management function allows the power

dissipation to be optimized.

2

APPLICATIONS

• Low-cost desktop video applications

• Videophone systems.

4

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

SAA8113HL

LQFP100

plastic low proﬁle quad ﬂat package; 100 leads;

SOT407-1

body 14 × 14 × 1.4 mm

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

5

QUICK REFERENCE DATA

Measured over full voltage and temperature range.

SYMBOL

PARAMETER

digital supply voltage

CONDITIONS

MIN.

3.0

TYP.

3.3

MAX.

3.6

UNIT

V_DDD

V_DDA

I_DD(tot)

V_I

V

analog supply voltage

total supply current

input voltage

3.0

3.3

60

3.6

V

V_DDD= 3.3 V

−

mA

V

3.0 V < V_DDD< 3.6 V low-voltage TTL compatible

note 1 5 V tolerant, TTL compatible

3.0 V < V_DDD< 3.6 V low-voltage TTL compatible

V

V_O

output voltage

V

note 1

5 V tolerant, TTL compatible

V

f_clk

δ

clock frequency input

duty factor of f_clk

−

38

50

200

−

MHz

%

−

P_tot

T_stg

T_amb

T_j

total power dissipation

storage temperature

ambient temperature

junction temperature

T_amb= 25 °C

T_amb= 70 °C

−

250

+150

70

mW

°C

−55

0

25

−

−40

+125

Note

1. This concerns pins SCL and SDA.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

7

PINNING

SYMBOL

I/O

DESCRIPTION

M2

1

I

test mode control signal bit 2

test mode control signal bit 1

test mode control signal bit 0

input connected to DSP core

M1

2

M0

3

KNOB4

KNOB3

KNOB2

KNOB1

KNOB0

RESET

SCLE

4

5

I/O I/O connected to internal 80C51

6

7

8

9

I

Power-on reset

master I²C-bus clock output to control EEPROM

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

O

SDAE

I/O master I²C-bus data I/O to control EEPROM

AGND1

V_DDA1

I

analog ground 1 for output buffers

analog supply voltage 1 for output buffers

slave I²C-bus clock input

SCL

SDA

I/O slave I²C-bus data I/O

T1

I

Timer 1 for internal 80C51

V_DDA2

analog supply voltage 2 for DAC output buffer

VDAC output buffer for CVBS signal

analog ground 2 for DAC output buffer

VDOBCVBS

AGND2

AGND3

AGND4

DECREF

V_DDA3

O

I

analog ground 3 for analog DAC core and band gap (connected to substrate)

analog ground 4 for analog DAC core and band gap (not connected to substrate)

decoupled pin for reference voltage HIGH

I

O

I

analog supply voltage 3 for analog DAC core and band gap

microphone input audio buffer

MICIAB

V_COMAB

AGND5

OUTAB

AGND6

V_DDA4

I

common voltage for audio buffer

I

analog ground 5 for audio buffer (not connected to substrate)

output audio buffer

O

I

analog ground 6 for audio buffer (connected to substrate)

analog supply voltage 4 for audio buffer

I

OUTBVEN

OUTGAIN

PSEN

AD8

O

I

output to enable the bias voltage of the microphone for the audio buffer

output to control the gain factor of an external audio buffer

program store enable; read strobe for external program memory (active LOW)

address bit 8 for external program memory (PROM)

address bit 9 for external program memory (PROM)

address bit 10 for external program memory (PROM)

address bit 11 for external program memory (PROM)

address bit 12 for external program memory (PROM)

address bit 13 for external program memory (PROM)

address bit 14 for external program memory (PROM)

analog supply voltage 5 for output buffers

AD9

AD10

AD11

AD12

AD13

AD14

V_DDA5

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

AGND7

I/O

DESCRIPTION

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

I

analog ground 7 for output buffers

P0.0

I/O port 0 bidirectional bit 0 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 1 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 2 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 3 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 4 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 5 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 6 for external program memory data I/O (PROM)

I/O port 0 bidirectional bit 7 for external program memory data I/O (PROM)

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

ALE

O

I

address latch enable pulse for external latch

output to drive LED

LED

EA

external access select bit for internal 80C51 (active LOW)

interrupt 1 for internal 80C51

INT1

I

DGND1

V_DDD1

DGND2

V_DDA6

RBIASCDAC

CDACOUT

AGND8

AGND9

XIN

I

digital ground 1 for input buffers, predrivers and the digital core

digital supply voltage 1 for input buffers, predrivers and the digital core

digital ground 2 for input buffers, predrivers and the digital core

analog supply voltage 6 for CDAC

I

O

I

bias resistor for CDAC

output CDAC

analog ground 8 for CDAC

I

analog ground 9 for 38 MHz (fundamental) crystal oscillator

oscillator input

I

XOUT

V_DDA7

V1X

O

I

oscillator output

analog supply voltage 7 for 38 MHz (fundamental) crystal oscillator

vertical CCD transfer pulse 1X

O

I

VH1X

V2X

vertical CCD load pulse H1X

vertical CCD transfer pulse 2X

V3X

vertical CCD transfer pulse 3X

VH3X

V4X

vertical CCD load pulse H3X

vertical CCD transfer pulse 4X

V_DDA8

AGND10

OFDX

FH2

analog supply voltage 8 for output buffers

analog ground 10 for output buffers

I

O

overﬂow drain pulse for shutter control

horizontal CCD transfer pulse F2

FH1

horizontal CCD transfer pulse F1

FR

CCD output ampliﬁer reset pulse (TDA8786 or TDA8784)

CCD output level sample and hold pulse (TDA8786 or TDA8784)

reference level sample and hold pulse (TDA8786 or TDA8784)

black pixel clamp pulse (TDA8786 or TDA8784)

dummy pixel clamp pulse (TDA8786 or TDA8784)

pixel clock to preprocessor (TDA8786 or TDA8784)

FS

FCDS

BCP

DCP

CLK1

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

I/O

DESCRIPTION

AGND11

V_DDA9

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

I

analog ground 11 for output buffers

analog supply voltage 9 for output buffers

SMP

O

I

switch mode pulse for DC-to-DC power supply

(preprocessed) AD-converted CCD signal bit 9

(preprocessed) AD-converted CCD signal bit 8

(preprocessed) AD-converted CCD signal bit 7

(preprocessed) AD-converted CCD signal bit 6

(preprocessed) AD-converted CCD signal bit 5

(preprocessed) AD-converted CCD signal bit 4

(preprocessed) AD-converted CCD signal bit 3

(preprocessed) AD-converted CCD signal bit 2

(preprocessed) AD-converted CCD signal bit 1

(preprocessed) AD-converted CCD signal bit 0

digital ground 3 for input buffers, predrivers and the digital core

CCD9

CCD8

CCD7

CCD6

CCD5

CCD4

CCD3

CCD2

CCD1

CCD0

DGND3

V_DDD2

STDBY

STROBE

SCLK

I

digital supply voltage 2 for input buffers, predrivers and the digital core

standby control output to TDA8786 or TDA8784

strobe to TDA8786 or TDA8784

O

serial clock to TDA8786 or TDA8784

SDATA

serial data to TDA8786 or TDA8784

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

handbook, full pagewidth

M2

M1

1

2

3

4

5

6

7

8

9

75 FH1

74 FH2

73 OFDX

M0

AGND10

KNOB4

KNOB3

KNOB2

KNOB1

KNOB0

RESET

72

71

V

DDA8

70 V4X

69 VH3X

68

67

V3X

V2X

SCLE 10

66 VH1X

65 V1X

V

11

12

13

SDAE

AGND1

64

63

DDA7

XOUT

SAA8113HL

V

DDA1

SCL 14

SDA 15

62 XIN

AGND9

61

60

59

58

57

16

17

18

AGND8

T1

V

CDACOUT

RBIASCDAC

DDA2

VDOBCVBS

V

AGND2 19

AGND3 20

AGND4 21

DDA6

56 DGND2

V

55

DDD1

DECREF

22

23

54 DGND1

53 INT1

V

DDA3

MICIAB 24

52

51

EA

V

25

LED

COMAB

FCE313

Fig.2 Pin configuration.

9

1999 Sep 27

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8

FUNCTIONAL DESCRIPTION

Black offset preprocessing

advantage of the full code range. Otherwise, the black

level is fixed by settings that are downloaded through the

serial interface.

8.1

The CCD signal contains additional pixels outside the

active window, which are used to measure the reference

black level. These pixels are located in the optical black

window, whose position can be set through the serial

interface. The optical black level can be adjusted by the

microcontroller in order to proceed rapidly. In this case, the

microcontroller directly adjusts the analog preprocessing

clamp included in the TDA8786 or TDA8784 and takes

8.2

Y, C_Rand C_Bseparation

For each pixel value, this block (see Fig.3) generates the

three components: the luminance signal Y and the two

colour signals C_R(2R − G) and C_B(2B − G). Two line

memories are required for this function. This block also

provides vertical contour and white clip information.

handbook, full pagewidth

LINE

Y

MEMORY

C

R

RGB

COLOUR

C

B

LINE

MEMORY

SEPARATION

white clip

Y

CCD inputs

10

vertical contour

FCE314

Fig.3 Y, C_Rand C_Bseparation diagram.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8.3

RGB processing

• Separate gain controls for R and B signals dedicated to

white balance control. The colour temperature can be

adjusted independently of the colour matrix.

The RGB processing (see Fig.4) includes several features:

• Colour space matrix to handle different types of colour

sensors. The result is an optimum colour reproduction

through the minimization of colour errors. The default

matrix coefficients (positive or negative) can be adjusted

through an external interface.

• Knee function (compression factor and knee point are

adjustable).

• Adjustable gamma function to compensate for the

non-linearity of display devices.

• Separate and adjustable black offsets for

R, G and B signals.

The RGB path has a reduced bandwidth (less than

1 MHz), which is required for CVBS output.

R

black

gain

handbook, full pagewidth

LPF

KNEE

GAMMA

Y

R

G

B

+

×

G

black

COLOUR

MATRIX

C

+

B

black

gain

GAMMA

C

+

×

B

FCE315

Fig.4 RGB processing diagram.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8.4

Y processing

• Black offset

• Pre-gain control to adjust the Y signal with respect to the

gamma range

The separate Y processing (see Fig.5) includes the

following features:

• Knee function (compression factor and knee point are

adjustable)

• Saturation concealment to reduce the typical saturation

distortion

• Adjustable gamma function

• Gain control.

• Contour processing to improve picture sharpness

• Noise reduction

handbook, full pagewidth

CONTOUR PROCESSING

AND

NOISE REDUCTION

Y

vertical contour

Y

gain

black

pre-gain

SATURATION

CONCEALMENT

KNEE

GAMMA

Y

+

×

FCE316

Fig.5 Y processing diagram.

8.5

RGB to UV conversion

8.7

Display function

After R, G and B processing, the data path is converted to

U and V signals (see Fig.1). As a result of the reduced

bandwidth, the Y signal is only used as an input for control

loop purposes (measurement engine).

As an optional feature and for software debugging, it is

possible to visualize:

• Eight display bars (assigned via the microcontroller)

• Several measurement engine inputs.

8.6

UV processing

The chrominance processing consists of a noise reduction

by coring and the UV gain control.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8.8

Analog output processing

twice the pixel clock and digitally prefiltered to keep the

external analog filter simple. The block also contains an

adjustable luminance clipper.

The analog output processing (see Fig.6) contains a

PAL/NTSC encoder to transform the YUV data path to the

CVBS output. The YUV input signals are up-sampled to

handbook, full pagewidth

Y

C

Y

U

V

PAL/NTSC

ENCODER

VDOBCVBS

VDAC

MIX

FCE317

sync, blank, scaling, levels

Fig.6 Analog output processing.

8.9

Measurement engine

8.10 VH reference and window timing and control

The measurement engine performs data measurements

on a field basis to get inputs for the AE and AWB control

loops of the microcontroller. Up to 16 programmable

windows can be used for the measurement. There are two

down-samplers to prepare the data for two separate

accumulators. It is possible to proceed with eight different

measurements per field (odd and even fields separately).

An internal RAM workspace is used for data handling

operation.

This block generates internal control signals for different

purposes:

• Vertical, horizontal and field references (V_D, H_Dand F_I)

for PAL or NTSC sensors

• Specification of the active window and the optical black

window

• Specification of the measurement window grid with

respect to the active window

• Specification of the vertical position of the display bars,

see Section 8.7.

All these specifications can be controlled through the serial

interface.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8.11 Pulse pattern generator

The PPG is dedicated to the medium resolution sensors

with complementary mosaic colour filters (512 × 492

NTSC and 512 × 582 PAL) described in Table 1.

Figs. 11 and 12 show the PPG outputs.

The PPG generates timing pulses (Figs. 7 to 10) for

driving the CCD sensor (including the vertical driver) and

pulses for the preprocessor TDA8786 or TDA8784

(correlated double sampling and black clamping).

Table 1 Medium resolution CCD sensors driven by the internal PPG; note 1

BRAND FORMAT

TYPE

SHARP

PAL 1/4”

LZ2423A

NTSC 1/4”

PAL 1/5”

LZ2413A

LZ2523

NTSC 1/5”

PAL 1/4”

LZ2513

TOSHIBA

TCD5391AP

TCD5381AP

LZ2425

NTSC 1/4”

PAL 1/4”

SHARP low voltage

PANASONIC

NTSC 1/4”

PAL 1/4”

LZ2415

MN37210FP

MN37201FP

MN37110FP

MN37101FP

PAL 1/4”

NTSC 1/4”

Note

1. All sensors are used with the vertical driver: NEC µPD16510.

The PPG includes special features:

• A charge reset is possible in every active line during the horizontal line blanking and multiple times during the vertical

blanking

• A fast shutter interface is available.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

4 × f

handbook, full pagewidth

pixel

XIN

FH1

FH2

FCDS

FS_narrow

FS_wide

FR_wide

FR_narrow

delay (typ. 7 ns)

FR_narrow_delayed

FR_wide_delayed

FCE318

Fig.7 High speed pulse timing (CCD sensor and preprocessor).

15

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

NTSC line 17

PAL line 19

NTSC line 18

PAL line 20

handbook, full pagewidth

HD

V1X

V2X

V3X

V4X

VH1X

VH3X

NTSC line 279

PAL line 331

NTSC line 280

PAL line 332

HD

V1X

V2X

V3X

V4X

VH1X

VH3X

FCE319

Fig.8 SHARP and TOSHIBA CCD sensors/vertical drivers.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

NTSC line 17

PAL line 19

NTSC line 18

PAL line 20

handbook, full pagewidth

HD

V1X

V2X

V3X

V4X

VH3X

NTSC line 279

PAL line 331

NTSC line 280

PAL line 332

HD

V1X

V2X

V3X

V4X

VH3X

FCE320

Fig.9 SHARP low-voltage CCD sensors/vertical drivers.

1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

NTSC line 17

PAL line 19

NTSC line 18

PAL line 20

handbook, full pagewidth

HD

V1X

V2X

V3X

V4X

VH1X

VH3X

OFDX

NTSC line 279

PAL line 331

NTSC line 280

PAL line 332

HD

V1X

V2X

V3X

V4X

VH1X

VH3X

OFDX

FCE321

Fig.10 PANASONIC CCD sensors/vertical drivers.

18

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

handbook, full pagewidth

HD

V1X

V2X

V3X

V4X

OFDX

BCP

DCP

FCE322

Fig.11 SHARP, all types, PPG output.

handbook, full pagewidth

HD

V1X

V2X

V3X

V4X

OFDX

BCP

DCP

FCE323

Fig.12 PANASONIC PPG output.

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1999 Sep 27

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

8.12 Miscellaneous functions

• A 3-wire serial bus transfers the settings from the

microcontroller to the preprocessor (TDA8786 or

TDA8784).

• Power consumption: it is possible to switch the DSP off

without switching off the microcontroller.

• Oscillator frequency: a 7-bit CDAC tunes the oscillator

frequency according to the external quartz frequency to

guarantee the typical value of 38 MHz.

8.13 Mode control

This block controls the operational modes of the

SAA8113HL: application or test modes, see Table 2. For a

smooth adaptability, it is possible to bypass the main

modules.

The control digital value is downloaded through the

serial interface.

Table 2 Mode control

M2

0

M1

0

M0

0

EA

MODE

EA; note 1 application mode

0

1

−

0

application mode with bypassed PPG

application mode with bypassed microcontroller

application mode with bypassed PPG and microcontroller

0

1

0

1

Note

1. EA can be high or low, according to the application (high is for internal ROM access, low for external access).

8.14 Microcontroller

The microcontroller includes the following features:

• 16 kbyte internal ROM

The embedded microcontroller is basically an 80C654

core (80C51 family) with four ports. Its functionality is

standard, except that the core has no clock divided by 2

and the ports are dedicated input, output or I/O ports.

Ports P0 and P2 are available for connection to a

debugger or to an external program EPROM. The

microcontroller controls the AOB, the AE and the AWB

loops and downloads the settings for the DSP registers

from EEPROM at power-up or reset. Table 3 lists the

80C51 Standard Function Registers.

• 256 byte RAM

• Hardware I²C-bus interface for communication with

external microcontroller: SDA and SCL

• Software I²C-bus interface for communication with

external EEPROM containing DSP settings: SDAE and

SCLE

• Four I/O pins which can be used as human interface

(knobs): P1.0, P1.1, P1.2 and P1.3.

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Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 3 80C51 Standard Function Registers

SFR

NAME

SFR

ADDRESS

DATA DATA DATA DATA DATA DATA DATA DATA

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DESCRIPTION

B

B register

accumulator

SIADR serial interface address

F0H

E0H

DBH

DAH

D9H

D8H

D0H

C7H

B8H

B0H

A8H

A0H

90H

8DH

8CH

8BH

8AH

89H

88H

87H

83H

82H

81H

80H

B7

B6

B5

B4

B3

B2

B1

B0

ACC

ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0

SA6

SD7

ST7

SA5

SD6

ST6

SA4

SD5

ST5

STA

F0

SA3

SD4

ST4

STO

RS1

−

SA2

SD3

ST3

SI

SA1

SD2

0

SA0

SD1

0

GC

SD0

0

SIDAT

SISTA

serial interface data

serial interface status

SICON serial interface control

CR2 ENS1

AA

CR1

−

CR0

P

PSW

P4

program status word

port 4

CY

−

AC

−

RS0

−

OV

−

STBY

PX0

CRST

EX0

AD8

P1.0

−

IP

interrupt priority

port 3

−

IP6

IP5

T1

IP4

T0

PT1

INT1

ET1

PX1

INT0

EX1

PT0

FI

P3

RDN WRN

EA IE6

IE

interrupt enable

port 2

IE5

IE4

ET0

AD9

P1.1

−

P2

AD15 AD14 AD13 AD12 AD11 AD10

P1

port 1

SDA

SCL SDAE SCLE P1.3

P1.2

−

TH1

TH0

TL1

TL0

timer HIGH 1

timer HIGH 0

timer LOW 1

timer LOW 0

−

TMOD timer mode

TCON timer control

PCON power control

GATE

TF1

−

C/T

TR1

−

M1

TF0

−

M0

TR0

−

Gate

IE1

−

C/T

IT1

−

M1

IE0

PD

−

M0

IT0

IDL

−

DPH

DPL

SP

data pointer HIGH

−

data pointer LOW

stack pointer

port 0

−

SP7

AD7

SP6

AD6

SP5

AD5

SP4

AD4

SP3

AD3

SP2

AD2

SP1

AD1

SP0

AD0

P0

8.16 I²C-bus interface

Table 4 gives the command list of the I²C-bus interface.

8.15 Audio ampliﬁer

An analog audio amplifier is integrated in the SAA8113HL.

Its gain can be adjusted between a high (45 dB typical)

and a low (13 dB typical) value through the serial interface.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 4 Command list

ADD

NAME

CONTROL0

FUNCTION

see Table 5 for explanation

FORMAT

RANGE

0

byte

6 bits

4 bits

byte

4 bits

6 bits

2 bits

byte

n.a.

1

CONTROL1

see Table 7 for explanation

n.a.

2

CONTROL2

see Table 8 for explanation

n.a.

3

OB_STARTL_F0

OB_STARTL_F1

OB_STARTP

OB_PE_F0

ﬁrst line optical black window in ﬁeld 0

ﬁrst line optical black window in ﬁeld 1

ﬁrst pixel optical black window

ﬁxed optical black level for even pixel in ﬁeld 0

ﬁxed optical black level for odd pixel in ﬁeld 0

ﬁxed optical black level for even pixel in ﬁeld 1

ﬁxed optical black level for odd pixel in ﬁeld 1

colour matrix coefﬁcient p11

colour matrix coefﬁcient p12

colour matrix coefﬁcient p13

colour matrix coefﬁcient p21

colour matrix coefﬁcient p22

colour matrix coefﬁcient p23

colour matrix coefﬁcient p31

colour matrix coefﬁcient p32

colour matrix coefﬁcient p33

ﬁxed R-black level offset

[0 to 255]

4

256 + [0 to 255]

[0 to 255]

5

6

[0 to 127]

7

OB_PO_F0

[0 to 127]

8

OB_PE_F1

[0 to 127]

9

OB_PO_F1

[0 to 127]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

COL_MAT_P11

COL_MAT_P12

COL_MAT_P13

COL_MAT_P21

COL_MAT_P22

COL_MAT_P23

COL_MAT_P31

COL_MAT_P32

COL_MAT_P33

R_BLACK

[−128 to 127]/16

[−128 to 127]

[0 to 255]/128

[0 to 255]/64

[0 to 255]

G_BLACK

ﬁxed G-black level offset

B_BLACK

ﬁxed B-black level offset

COL_MAT_RGAIN

COL_MAT_BGAIN

THR_LUM

colour matrix R-gain factor

colour matrix B-gain factor

threshold luminance for fader

threshold colour for fader

THR_COLOR

Y_BLACK

[0 to 255]

ﬁxed Y-black level offset

[−128 to 127]

[0 to 255]/128

[0 to 255]

K1

gain correction for Y path

RGB_KNEE_OFFSET

Y_KNEE_OFFSET

offset for RGB knee

offset for Y knee

[0 to 255]

RGB_GAMMA_BALANCE gamma multiplication factor (for RGB data path)

[0 to 63]/64

[0 to 7]/8

Y_GAMMA_BALANCE

KCOMB

gamma multiplication factor (for Y data path)

vertical contour comb ﬁlter coefﬁcient (MS)

vertical contour gain (LS)

VCGAIN

[0 to 15]/16

[0 to 255]/2

[0 to 15]/16

[0 to 63]

33

34

CLDLEV

contour level dependency level

horizontal contour BPF low gain (LS)

horizontal contour BPF high gain (MS)

contour noise coring level

HCLGAIN

HCHGAIN

CNCLEV

35

36

37

CONGAIN

VU_VALUE 1

contour gain factor; see Table 9

length of VU_Bar 1

[0 to 63]/16

2 × [0 to 255]

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

ADD

NAME

VU_VALUE 2

FUNCTION

FORMAT

RANGE

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

length of VU_Bar 2

length of VU_Bar 3

length of VU_Bar 4

length of VU_Bar 5

length of VU_Bar 6

length of VU_Bar 7

length of VU_Bar 8

byte

6 bits

byte

4 bits

byte

2 × [0 to 255]

4 × [0 to 255]

[0 to 255]/4

[0 to 255]/128

[0 to 255]

VU_VALUE 3

VU_VALUE 4

VU_VALUE 5

VU_VALUE 6

VU_VALUE 7

VU_VALUE 8

Y_DISPLAY_OFFSET

UNCLEV

display offset (to be used with D_Contour)

U (chrominance) noise coring level

V (chrominance) noise coring level

Y (luminance) gain factor

VNCLEV

YGAIN

UGAIN

U (B-Y) gain factor

VGAIN

V (R-Y) gain factor

CTR_UPD_LINE

BURST_LEVEL

A

number of line for DB-update control registers

burst level colour burst

[0 to 255]

AWB_A (Measurement Engine)

AWB_B (Measurement Engine)

AWB_C (Measurement Engine)

AWB_D (Measurement Engine)

AWB_E (Measurement Engine)

AWB_F (Measurement Engine)

highlight threshold (Measurement Engine)

ME sync + ME result scale (ME); see Table 10

control bits for display function; see Table 11

luminance display level in display function

[−128 to 127]/128

[0 to 63]

B

C

D

E

F

[0 to 63]

HIGHLIGHTTHR

ME_RESSCALE

DISP_CNTRL

YDISPLEV

DMWSEL

[0 to 255]

n.a.

[0 to 255]

display measurement window select;

see Table 13

n.a.

64

65

66

ANA_WHITECLIP

PRE_SI_LSB

white clip limiter level for analog outputs

control data for analog processing

byte

256 + [0 to 255]

[0 to 255]

PRE_SI_MSB

control data and address for analog processing;

see Table 14

5 bits

[0 to 63]

67

68

69

70

71

72

73

74

75

76

SMP_CNTRL

CDAC_DATA

BLANKLEV

control for switch mode power supply

CDAC data (7-bit); see Table 15

blanking level in analog output

setup level in analog output

control compensation delay w.r.t. preprocessing

B clamp pulse start

byte

7 bits

byte

4 bits

byte

[0 to 255]

[0 to 127]

[0 to 255]

[0 to 15]

BL-SETUP

PRE_PROC_DEL

BCP_START

BCP_STOP

[0 to 255]

B clamp pulse stop

DCP_START

DCP_STOP

D clamp pulse start

D clamp pulse stop

EE_CONTROL_LSB

E Exposure LSB

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

ADD

77

78

79

80

81

82

83

84

85

86

NAME

EE_CONTROL_MSB

MISC_CONTROL

FPIX_ACT

FUNCTION

FORMAT

RANGE

[0 to 255]

[0 to 31]

[0 to 255]

n.a.

E Exposure MSB

byte

5 bits

byte

5 bits

miscellaneous control bits; see Table 16

number of ﬁrst active pixel on a line

number of last active pixel on a line

number of ﬁrst active line in ﬁeld 0

number of last active line in ﬁeld 0

number of ﬁrst active line in ﬁeld 1

number of last active line in ﬁeld 1

MSBs of active line numbers; see Table 17

LPIX_ACT_LSB

FLINE_ACT_F0

LLINE_ACT_F0

FLINE_ACT_F1

LLINE_ACT_F1

ACT_LINES_MSB

PPG_POL_SEL

select polarity of the PPG output signals;

see Table 18

128 ME_DPCC_A0_H_F1

129 ME_DPCC_A0_L_F1

130 ME_DPCC_B0_H_F1

131 ME_DPCC_B0_L_F1

132 ME_DPCC_A1_H_F1

133 ME_DPCC_A1_L_F1

134 ME_DPCC_B1_H_F1

135 ME_DPCC_B1_L_F1

136 ME_DPCC_A2_H_F1

137 ME_DPCC_A2_L_F1

138 ME_DPCC_B2_H_F1

139 ME_DPCC_B2_L_F1

140 ME_DPCC_A3_H_F1

141 ME_DPCC_A3_L_F1

142 ME_DPCC_B3_H_F1

143 ME_DPCC_B3_L_F1

144 ME_DPCC_A0_H_F2

145 ME_DPCC_A0_L_F2

146 ME_DPCC_B0_H_F2

147 ME_DPCC_B0_L_F2

148 ME_DPCC_A1_H_F2

149 ME_DPCC_A1_L_F2

150 ME_DPCC_B1_H_F2

151 ME_DPCC_B1_L_F2

152 ME_DPCC_A2_H_F2

153 ME_DPCC_A2_L_F2

154 ME_DPCC_B2_H_F2

155 ME_DPCC_B2_L_F2

156 ME_DPCC_A3_H_F2

157 ME_DPCC_A3_L_F2

ME data path control code A 0_H ﬁeld 1

ME data path control code A 0_L ﬁeld 1

ME data path control code B 0_H ﬁeld 1

ME data path control code B 0_L ﬁeld 1

ME data path control code A 1_H ﬁeld 1

ME data path control code A 1_L ﬁeld 1

ME data path control code B 1_H ﬁeld 1

ME data path control code B 1_L ﬁeld 1

ME data path control code A 2_H ﬁeld 1

ME data path control code A 2_L ﬁeld 1

ME data path control code B 2_H ﬁeld 1

ME data path control code B 2_L ﬁeld 1

ME data path control code A 3_H ﬁeld 1

ME data path control code A 3_L ﬁeld 1

ME data path control code B 3_H ﬁeld 1

ME data path control code B 3_L ﬁeld 1

ME data path control code A 0_H ﬁeld 2

ME data path control code A 0_L ﬁeld 2

ME data path control code B 0_H ﬁeld 2

ME data path control code B 0_L ﬁeld 2

ME data path control code A 1_H ﬁeld 2

ME data path control code A 1_L ﬁeld 2

ME data path control code B 1_H ﬁeld 2

ME data path control code B 1_L ﬁeld 2

ME data path control code A 2_H ﬁeld 2

ME data path control code A 2_L ﬁeld 2

ME data path control code B 2_H ﬁeld 2

ME data path control code B 2_L ﬁeld 2

ME data path control code A 3_H ﬁeld 2

ME data path control code A 3_L ﬁeld 2

byte

[0 to 255]

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

ADD

NAME

FUNCTION

FORMAT

RANGE

158 ME_DPCC_B3_H_F2

159 ME_DPCC_B3_L_F2

160 ME_RES_A0_H

ME data path control code B 3_H ﬁeld 2

ME data path control code B 3_L ﬁeld 2

ME data path result accuA 0_H

ME data path result accuA 0_L

ME data path result accuB 0_H

ME data path result accuB 0_L

ME data path result accuA 1_H

ME data path result accuA 1_L

ME data path result accuB 1_H

ME data path result accuB 1_L

ME data path result accuA 2_H

ME data path result accuA 2_L

ME data path result accuB 2_H

ME data path result accuB 2_L

ME data path result accuA 3_H

ME data path result accuA 3_L

ME data path result accuB 3_H

ME data path result accuB 3_L

ME data path sub-result accuA 0_H

ME data path sub-result accuA 0_L

ME data path sub-result accuB 0_H

ME data path sub-result accuB 0_L

ME data path sub-result accuA 1_H

ME data path sub-result accuA 1_L

ME data path sub-result accuB 1_H

ME data path sub-result accuB 1_L

ME data path sub-result accuA 2_H

ME data path sub-result accuA 2_L

ME data path sub-result accuB 2_H

ME data path sub-result accuB 2_L

ME data path sub-result accuA 3_H

ME data path sub-result accuA 3_L

ME data path sub-result accuB 3_H

ME data path sub-result accuB 3_L

simple window 0 (Vstart, Hstart)

simple window 0 (Vstop, Hstop)

simple window 1 (Vstart, Hstart)

simple window 1 (Vstop, Hstop)

simple window 2 (Vstart, Hstart)

simple window 2 (Vstop, Hstop)

simple window 3 (Vstart, Hstart)

byte

4 bits

[0 to 255]

[0 to 15]

161 ME_RES_A0_L

162 ME_RES_B0_H

163 ME_RES_B0_L

164 ME_RES_A1_H

165 ME_RES_A1_L

166 ME_RES_B1_H

167 ME_RES_B1_L

168 ME_RES_A2_H

169 ME_RES_A2_L

170 ME_RES_B2_H

171 ME_RES_B2_L

172 ME_RES_A3_H

173 ME_RES_A3_L

174 ME_RES_B3_H

175 ME_RES_B3_L

176 ME_SUBRES_A0_H

177 ME_SUBRES_A0_L

178 ME_SUBRES_B0_H

179 ME_SUBRES_B0_L

180 ME_SUBRES_A1_H

181 ME_SUBRES_A1_L

182 ME_SUBRES_B1_H

183 ME_SUBRES_B1_L

184 ME_SUBRES_A2_H

185 ME_SUBRES_A2_L

186 ME_SUBRES_B2_H

187 ME_SUBRES_B2_L

188 ME_SUBRES_A3_H

189 ME_SUBRES_A3_L

190 ME_SUBRES_B3_H

191 ME_SUBRES_B3_L

192 ME_WIN_START_0

193 ME_WIN_STOP_0

194 ME_WIN_START_1

195 ME_WIN_STOP_1

196 ME_WIN_START_2

197 ME_WIN_STOP_2

198 ME_WIN_START_3

[0 to 15]

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

ADD

NAME

FUNCTION

FORMAT

RANGE

199 ME_WIN_STOP_3

200 ME_WIN_START_4

201 ME_WIN_STOP_4

202 ME_WIN_START_5

203 ME_WIN_STOP_5

204 ME_WIN_START_6

205 ME_WIN_STOP_6

206 ME_WIN_START_7

207 ME_WIN_STOP_7

208 ME_WIN_START_8

209 ME_WIN_STOP_8

210 ME_WIN_START_9

211 ME_WIN_STOP_9

212 ME_WIN_START_10

213 ME_WIN_STOP_10

214 ME_WIN_START_11

215 ME_WIN_STOP_11

216 ME_WIN_START_12

218 ME_WIN_STOP_12

219 ME_WIN_START_13

220 ME_WIN_STOP_13

221 ME_WIN_START_14

222 ME_WIN_STOP_14

223 ME_RAM_DUMMY_H

simple window 3 (Vstop, Hstop)

simple window 4 (Vstart, Hstart)

simple window 4 (Vstop, Hstop)

simple window 5 (Vstart, Hstart)

simple window 5 (Vstop, Hstop)

simple window 6 (Vstart, Hstart)

simple window 6 (Vstop, Hstop)

simple window 7 (Vstart, Hstart)

simple window 7 (Vstop, Hstop)

simple window 8 (Vstart, Hstart)

simple window 8 (Vstop, Hstop)

simple window 9 (Vstart, Hstart)

simple window 9 (Vstop, Hstop)

simple window 10 (Vstart, Hstart)

simple window 10 (Vstop, Hstop)

simple window 11 (Vstart, Hstart)

simple window 11 (Vstop, Hstop)

simple window 12 (Vstart, Hstart)

simple window 12 (Vstop, Hstop)

simple window 13 (Vstart, Hstart)

simple window 13 (Vstop, Hstop)

simple window 14 (Vstart, Hstart)

simple window 14 (Vstop, Hstop)

4 bits

byte

[0 to 15]

n.a.

dummy read/write (additional RAM storage for

80C51)

224 ME_RAM_DUMMY_L

dummy read/write (additional RAM storage for

80C51)

byte

n.a.

225 HIGHLIGHTCOUNT_H

226 HIGHLIGHTCOUNT_L

227 AWBCOUNT_H

highlight counter H

highlight counter L

AWB counter H

AWB counter L

byte

[0 to 255]

[0 to 127]

228 AWBCOUNT_L

229 ME_OB_PO_F0

measured optical black pixel odd ﬁeld 0;

see Table 19

230 ME_OB_PE_F0

231 ME_OB_PO_F1

232 ME_OB_PE_F1

measured optical black pixel even ﬁeld 0;

see Table 20

byte

[0 to 127]

measured optical black pixel odd ﬁeld 1;

see Table 21

measured optical black pixel even ﬁeld 1;

see Table 22

254 DUMMY_READ

255 DUMMY_WRITE

dummy read

dummy write

byte

[0 to 255]

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 5 Register details: address 0 CONTROL0

BIT

NAME

FUNCTION

CONTROL0.0

CONTROL0.1

CONTROL0.2

CONTROL0.3

CONTROL0.4

CONTROL0.5

CONTROL0.6

CONTROL0.7

not used

RGB_KNEE_K

PIX_PHASE

compression factor for RGB_KNEE; see Table 6

toggle phase for pixel in colour separation

toggle phase for line in colour separation

toggle colour ﬁlter structure (interline)

not used

LINE_PHASE

INTERLINE_PHASE

not used

Table 6 Truth table for bits CONTROL0.1 and CONTROL0.2

BIT NUMBER

COMPRESSION FACTOR

2

1

0

1

0

1

0

1

1/8

1/4

3/8

1/2

Table 7 Register details: address 1 CONTROL1

BIT

NAME

FR_WIDE

FUNCTION

CONTROL1.0

CONTROL1.1

CONTROL1.2

CONTROL1.3

CONTROL1.4

CONTROL1.5

CONTROL1.6

CONTROL1.7

FR wide/narrow

FR_SHIFT

FS_WIDE

FR shifted/unshifted

FS wide/narrow

DUALPOWER

SHARP

SHARP dual power/other sensor select

SHARP/PANASONIC sensor select

choose between PAL/NTSC

PAL_NTSC

BCP_MODE

CP_TOGGLE

select BCP mode 1/0

carrier phase toggle/not toggle

Table 8 Register details: address 2 CONTROL2

BIT

NAME

CATCH_CCD

FUNCTION

catch CCD data/normal operation

high frequency enhancer bypass/active

CONTROL2.0

CONTROL2.1

CONTROL2.2

CONTROL2.3

CONTROL2.4

CONTROL2.5

CONTROL2.6

CONTROL2.7

HFE_BYPASS

Y_TEST

select y_test from RGB2(Y)UV instead of Yon/off

chrominance modulator bypass/active

scale chrominance with factor 2 on/off

select as luminance input (F0) Yae/y_n

switch vertical contour LPF on/off

MOD_BYPASS

DOUBLE_C

Y_SEL

VCONTOUR_LPF

FADER IMPL

select fader implementation n1/n2

1999 Sep 27

27

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 9 Register details: address 36 CONGAIN

NAME

FUNCTION

CONGAIN.0 to CONGAIN.5

CONGAIN.6

contour gain factor (0 to 63/16)

contour gain fading off/on

Table 10 Register details: address 60 ME_RESSCALE

NAME

ME_RESSCALE.0 to ME_RESSCALE.2 ME result scaler selection (0, 2, 4, 8 and 16)

MECNTRL.3 ME synchronization (synchronize ﬁeld/frame toggle of Measurement

Engine)

Table 11 Register details: address 61 DISP_CNTRL

NAME

FUNCTION

DISP_CNTRL.0 and DISP_CNTRL.1

DISP_CNTRL.2 and DISP_CNTRL.3

DISP_CNTRL.4

V display level

U display level

contrast reduction/level insertion

DISP_CNTRL.5 to DISP_CNTRL.7

display signal selection code; see Table 12

Table 12 Truth table for bits DISP_CNTRL5 to DISP_CNTRL7]

BIT NUMBER

SELECT CODE

7

6

5

0

1

0

1

0

1

0

1

0

1

0

1

X

no display

D_VU

D_WC

D_AWBVAL

D_HIGHLIGHT

D_MWG

D_CONTOUR

Table 13 Register details: address 63 DMWSEL

NAME

FUNCTION

display measurement window A for line 0

display measurement window B for line 0

DMWSEL.0

DMWSEL.1

DMWSEL.2

DMWSEL.3

DMWSEL.4

DMWSEL.5

DMWSEL.6

DMWSEL.7

display measurement window A for line 1

display measurement window B for line 1

display measurement window A for line 2

display measurement window B for line 2

display measurement window A for line 3

display measurement window B for line 3

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 14 Register details: address 66 PRE_SI_MSB

NAME

FUNCTION

PRE_SI_MSB.0 and PRE_SI_MSB.1

PRE_SI_MSB.2 to PRE_SI_MSB.4

control data bits d8 and d9

control address bits a0 to a2

Table 15 Register details: address 68 CDAC_DATA

NAME

FUNCTION

CDAC_DATA.0 to CDAC_DATA.6

CDAC data bits 0 to 6

Table 16 Register details: address 78 MISC_CONTROL

NAME

MISC_CONTROL.0

LED off/on

MISC_CONTROL.1

audio on/off

MISC_CONTROL.2

audio gain low (13 dB), high (45 dB)

select 1 kΩ mode (output impedance)

standby on/off

MISC_CONTROL.3

MISC_CONTROL.4

MISC_CONTROL.5 to MISC_CONTROL.7

reserved for miscellaneous additional functions

Table 17 Register details: address 85 ACT_LINES_MSB

NAME

FUNCTION

ACT_LINES_MSB.0 and ACT_LINES_MSB.1 bits 8 and 9 for last active pixel number on a line

ACT_LINES_MSB.2 and ACT_LINES_MSB.3 bits 8 and 9 for last active line number in ﬁeld 0

ACT_LINES_MSB.4 and ACT_LINES_MSB.5 bits 8 and 9 for ﬁrst active line number in ﬁeld 1/frame

ACT_LINES_MSB.6 and ACT_LINES_MSB.7 bits 8 and 9 for last active line number in ﬁeld 1/frame

Table 18 Register details: address 86 PPG_POL_SEL

Name

FUNCTION

PPG_POL_SEL.0

PPG_POL_SEL.1

PPG_POL_SEL.2

PPG_POL_SEL.3

PPG_POL_SEL.4

select polarity of PPG output FR as inverted/non-inverted

select polarity of PPG output FS as inverted/non-inverted

select polarity of PPG output FCDS as inverted/non-inverted

select polarity of PPG output FH1 as inverted/non-inverted

select polarity of PPG output FH2 as inverted/non-inverted

Table 19 Register details: address 229 ME_OB_PO_F0

FUNCTION

CCD_CATCH = 0

NAME BIT NO

CCD_CATCH = 1

CCD2 to CCD8

CCD9

ME_OB_PO_F0.0 to ME_OB_PO_F0.6

ME_OB_PO_F0.7

ME_OB_PO_F00 to ME_OB_PO_F06

0

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

Table 20 Register details: address 230 ME_OB_PE_F0

FUNCTION

NAME BIT NO

CCD_CATCH = 0

CCD_CATCH = 1

ME_OB_PE_F0.0 and ME_OB_PE_F0.1

ME_OB_PE_F0.2 to ME_OB_PE_F0.6

ME_OB_PE_F0.7

ME_OB_PE_F00 and ME_OB_PE_F01

ME_OB_PE_F02 to ME_OB_PE_F06

KNOB4

CCD0 and CCD1

0

Table 21 Register details: address 231 ME_OB_PO_F1

FUNCTION

NAME BIT NO

CCD_CATCH = 0

CCD_CATCH = 1

ME_OB_PO_F1.0 to ME_OB_PO_F1.6

ME_OB_PO_F1.7

ME_OB_PO_F16 to ME_OB_PO_F10

0

‘undeﬁned’

Table 22 Register details: address 232 ME_OB_PE_F1

FUNCTION

CCD_CATCH = 01

NAME BIT NO

CCD_CATCH = 1

ME_OB_PE_F1.0 to ME_OB_PE_F1.6

ME_OB_PE_F1.7

ME_OB_PE_F16 to ME_OB_PE_F10

0

‘undeﬁned’

9

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); note 1 unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS MIN.

MAX.

+4.0

UNIT

V_DDDn

digital supply voltages 1 and 2 for input buffer and

pre-drivers

−0.5

V

V_DDAn

analog supply voltages 1, 5, 8 and 9 for output buffers

analog supply voltage 2 for DAC output buffer

analog supply voltage 3 for analog DAC core and band gap

analog supply voltage 4 for audio buffer

−0.5

+4.0

V

V_DDA2

V_DDA3

V_DDA4

V_DDA6

analog supply voltage 6 for CDAC

V_DDA7

analog supply voltage 7 for 38 MHz crystal oscillator

digital grounds 1, 2, and 3 for input buffer and predrivers

analog grounds 1, 7, 10 and 11 for output buffers

analog ground 2 for DAC output buffer

DGNDn

AGNDn

AGND2

AGND3

analog ground 3 for analog DAC core and band gap,

connected to substrate

AGND4

analog ground 4 for analog DAC core and band gap, not

connected to substrate

−0.5

+4.0

V

AGND6

AGND5

AGND8

AGND9

analog ground 6 for audio buffer connected to substrate

analog ground 5 for audio buffer not connected to substrate

analog ground 8 for CDAC

−0.5

+4.0

V

analog ground 9 for 38 MHz crystal oscillator

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

PARAMETER

CONDITIONS MIN.

MAX.

UNIT

V_I, V_O

input or output voltage

−0.5

V_DD+ 0.5 V

note 2

−0.5

−55

0

+5.5

+150

70

V

T_stg

T_amb

T_j

storage temperature

ambient temperature

junction temperature

°C

−40

+125

Notes

1. Stress beyond these levels may cause permanent damage to the device.

2. For 5 V-tolerant buffers.

10 THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

in free air

56

K/W

11 OPERATING CHARACTERISTICS

V_DDD= V_DDA= 3.3 V ±10%; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

General supplies

V_DDD

V_DDA

DGND

AGND

I_DDD

digital supply voltage

analog supply voltage

3.0

3.3

0.0

45

3.6

V

3.6

+0.3

−

V

digital ground

−0.3

−

V

analog ground

V

digital supply current

analog supply current

ambient temperature

T_amb= 25 °C

mA

°C

I_DDA

−

15

−

T_amb

0

25

70

Data and control inputs or I/Os (CCD9 to CCD0, M2 to M0, KNOB4 to KNOB0, RESET, EA, T1, INT1 and

P0.7 to P0.0)

V_IL

V_IH

LOW-level input voltage

HIGH-level input voltage

−

0.2V_DDD

V

0.8V_DDD

−

Data and control outputs or I/Os (SMP, LED, OUTBVEN, OUTGAIN, SDATA, SCLK, SDAE, SCLE, STROBE,

STNDBY, FR, OFDX, AD14 to AD8 and P0.7 to P0.0)

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

0

−

0.4

V

0.85V_DDD

V_DDD

Control outputs (FH1, FH2, FS, FCDS and CLK1)

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

note 1

note1

−

0.8

V

2.2

−

Control outputs (V1X, V2X, V3X, V4X, VH1X and VH3X)

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

notes 2 and 3

−

0.8

V

2.6

−

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Control outputs (BCP and DCP)

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

−

0.6

V

2.2

−

V

Switch Mode Pulse for DC-to-DC power supply (SMP)

I_Ooutput current

Output to drive the LED (LED)

3

5

mA

I_O

output current

Notes

1. Connected to HCT (lab resources) with V_IH(min)= 2.0 V and V_IL(max)= 0.8 V.

2. Connected to NEC µPD16510 with V_IH(min)= 0.8V_DDand V_IL(max)= 0.3V_DD

.

3. Connected to ACT/HCT (lab resources) with V_IH(min)= 2.0 V and V_IL(max)= 0.8 V.

12 ELECTRICAL CHARACTERISTICS

V_DDD= V_DDA= 3.3 V ±10%; T_amb= 0 to 70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX. UNIT

CDAC speciﬁcations

LOAD

R_L

C_L

load resistance

load capacitance

10

−

kΩ

−

100

pF

TRANSFER FUNCTION

V_O

DC output voltage

at code ‘0’

−

0.00

0.05

V

at code ‘127’

V

−

_DDD− 0.2 V_DDD− 0.12 V_DDD

V

RES

DNL

INL

CR

B_A

resolution

7

−

bit

differential non-linearity

integral non-linearity

conversion rate

−

1/2

1

LSB

Hz

Ω

−

60

−

analog bandwidth

output resistance

−

R_o

13

SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP

t_PD

t_st1

propagation delay time

settling time

to 50% value

−

75

ns

10% to 90%

full-scale

120

t_st2

settling time

to ±1 LSB

−

156

ns

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX. UNIT

VDAC speciﬁcations

LOAD

R_L

load resistance

with high

0.8

1

−

kΩ

impedance

(1 kΩ mode)

C_L

load capacitance

with high

−

5

pF

impedance

(1 kΩ mode)

TRANSFER FUNCTION

V_o(0)

DC output voltage at code ‘0’

DC output voltage at code ‘436’

0.15

1.45

1.15

0.212

1.55

0.30

1.75

1.6

V

V_o(436)

VRL_(p-p)

output voltage (436 to 0)

(peak-to-peak value)

note 1

1.288

RES

DNL

INL

CR

resolution

−

9

−

bit

1

differential non-linearity

integral non-linearity

conversion rate

−

⁄

LSB

MHz

dB

2

−

1

−

19

6.5

46

−50

2

−

f_CLK

B_A

clock frequency

−

analog bandwidth

signal-to-noise ratio

total harmonic distortion

output resistance

−

S/N

THD

R_o

dynamic

43

−

−42

3

dB

−

Ω

SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP

t_PD

t_st1

propagation delay time

settling time

to 50% value

−

13

15

ns

10% to 90%

full-scale

t_st2

settling time

to ±1 LSB

−

50

ns

Audio ampliﬁer speciﬁcations

LOAD

R_L

C_L

load resistance

5

−

kΩ

load capacitance

−

5

pF

TRANSFER FUNCTION

V_i(p-p)

A1

nominal input level (peak-to-peak value)

−

5.6

−

mV

dB

ampliﬁcation at high level

43

141.2

11

3.5

−

44.8

173.7

12.5

4.2

47

223.8

14

5.0

−

A2

ampliﬁcation at low level

dB

V

V_OH(p-p)

nominal output level at high level

(peak-to-peak value)

0.97

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX. UNIT

V_OL(rms)

nominal output level at high level

(RMS value)

−

0.34

23.5

8.3

−

V

V_o2(p-p)

V_o2(rms)

nominal output level at low level

(peak-to-peak value)

mV

nominal output level at low level

(RMS value)

V_o(max)(p-p)maximum output level (peak-to-peak value)

2

−

V

S/N

THD

Z_i

signal-to-noise ratio

40

−

dB

kΩ

Ω

total harmonic distortion at high level

input impedance

−60

−

−50

−

5

Z_o

output impedance

−

100

20

B_{-3 dB}

frequency range (−3 dB)

0.1

−

kHz

BIASSING

I_ref

reference current

−

25

−

µA

Data input/output timing; (see Fig.13)

DATA INPUTS RELATED TO XIN (CCD9 TO CCD0 AND KNOB4)

t_su(i)(D)

t_h(i)(D)

data input setup time

data input hold time

note 2

9.5

−

ns

10.5

DATA OUTPUTS RELATED TO XIN (OUTBVEN, OUTGAIN, SMP, LED, SDATA, SCLK, STROBE AND STNDBY)

t_h(o)(D)

t_d(o)(D)

data output delay time

data output hold time

note 2

−

5

3

7

ns

5.5

PPG high speed pulse timing; C_L= 10 pF (see Fig.14)

t_d1

FH2 fall time delay w.r.t. the rising edge of

FH1

−3

0

+3

2

ns

t_d2

FH2 rise time delay w.r.t. the falling edge of

FH1

0

t_d3

FR fall time delay w.r.t. the rising edge of

FH1

1

t_{d3_delayed}

t_{d4_wide}

t_{d4_narrow}

t_d5

FR_delayed fall time delay w.r.t. the rising

edge of FH1

7

8

10

3

FCDS fall time delay w.r.t. the rising edge of

FR_wide

1

2

FCDS fall time delay w.r.t. the rising edge of

FR_narrow

14

0

15

1

16

2

FH1 fall time delay w.r.t. the rising edge of

FCDS

t_{d6_wide}

t_{d6_narrow}

t_d7

FH1 rise time delay w.r.t. the rising edge of

FS_wide

0

1

2

FH1 rise time delay w.r.t. the rising edge of

FS_narrow

14

0

15

1

16

2

CLK1 fall time delay w.r.t. the rising edge of

FH1

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

SYMBOL

t_d8

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX. UNIT

CLK1 rise time delay w.r.t. the falling edge of

FH1

0

1

2

ns

t_wFH1

t_rFH1

FH1 pulse width

FH1 rise time

−

53

4

−

ns

t_fFH1

FH1 fall time

4

t_wFH2

t_rFH2

FH2 pulse width

FH2 rise time

53

4

t_fFH2

FH2 fall time

4

t_{wFR_wide}

FR_wide pulse width

26

13

4

t_{wFR_narrow}FR_narrow pulse width

t_rFR

FR rise time

t_fFR

FR fall time

4

t_wFCDS

t_rFCDS

t_fFCDS

t_{wFS_wide}

t_{wFS_narrow}

t_rFS

FCDS pulse width

FCDS rise time

FCDS fall time

FS_wide pulse width

FS_narrow pulse width

FS rise time

26

4

40

26

4

t_fFS

FS fall time

4

t_wCLK1

CLK1 pulse width

53

Notes

1. Full code swing of colour bar with maximum headroom of 16.4%. Above code ‘436’, the DAC works but the settling

time will decrease gradually.

2. The internal clock signal used in the DSP core is derived from XIN: XIN divided by 4.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

t

r

handbook, full pagewidth

f

90%

XIN

50%

10%

t

h(i)(D)

su(i)(D)

data input

t

d(o)(D)

h(o)(D)

90%

10%

90%

10%

data output

FCE324

Fig.13 Data input/output timing.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

handbook, full pagewidth

t

wFH1

50%

d1

50%

FH1

FH2

t

d2

50%

t

wFH2

50%

FCDS

t

wFS

t

d6_wide

wFCDS

d5

FS_wide

FS_narrow

t

d6_narrow

t

d3

t

wFR

d4_wide

50%

t

FR_wide

d4_narrow

50%

FR_narrow

t

d3_delayed

50%

FR_wide_delayed

FR_narrow_delayed

CLK1

50%

t

d7

d8

50%

t

wCLK1

FCE325

Fig.14 PPG high speed pulse timing diagram.

37

1999 Sep 27

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

13 APPLICATION INFORMATION

handbook, full pagewidth

SAA8113HL

analog

preprocessing

optics

CCD sensor

CDS,

AGC

AND

ADC

PAL/NTSC

(medium

resolution)

DIGITAL

SIGNAL

PROCESSING

analog

(CVBS)

LPF

VDAC

PREPROCESSING,

parallel

interface

TIMING AND

CONTROL

program

PROM

DRIVERS

SENSOR,

TIMING AND

CONTROL

serial

interface

settings

EEPROM

MODE CONTROL

AND

CLOCK GENERATOR

MICRO-

CONTROLLER

2

I C-bus

interface

80C51

CDAC

HUMAN INTERFACE

AUDIO AMPLIFIER

FCE326

Fig.15 Application block diagram.

38

1999 Sep 27

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

14 PACKAGE OUTLINE

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.20 1.5

0.05 1.3

0.28 0.18 14.1 14.1

0.16 0.12 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1.0

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-12-19

97-08-04

SOT407-1

1999 Sep 27

39

Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

15 SOLDERING

If wave soldering is used the following conditions must be

observed for optimal results:

15.1 Introduction to soldering surface mount

packages

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population densities. In these situations reflow

soldering is often used.

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

15.2 Reﬂow soldering

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

15.4 Manual soldering

15.3 Wave soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

Digital PC-camera signal processor

SAA8113HL

15.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE

REFLOW⁽¹⁾

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽²⁾

PLCC⁽³⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽³⁾⁽⁴⁾

not recommended⁽⁵⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

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16 DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

18 PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

1999 Sep 27

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Philips Semiconductors

Preliminary speciﬁcation

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SAA8113HL

NOTES

1999 Sep 27

43

Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Brazil: see South America

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,

Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Czech Republic: see Austria

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

Tel. +27 11 471 5401, Fax. +27 11 471 5398

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

South America: Al. Vicente Pinzon, 173, 6th floor,

04547-130 SÃO PAULO, SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 821 2382

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,

Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),

Tel. +39 039 203 6838, Fax +39 039 203 6800

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Vietnam: see Singapore

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

68

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545006/25/01/pp44

Date of release: 1999 Sep 27

Document order number: 9397 750 04816


型号：	SAA8113HL
厂家：	NXP
描述：	Digital PC-camera signal processor 数字PC的相机信号处理器 PC
文件：	总44页 (文件大小：158K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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