SAA8116ET [NXP]
Digital PC-camera signal processor including microcontroller and USB interface; 数码电脑摄像头信号处理器包括微控制器和USB接口
| 型号： | SAA8116ET |
| 厂家： | 
NXP |
| 描述： | Digital PC-camera signal processor including microcontroller and USB interface |
| 文件： | 总60页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA8116
Digital PC-camera signal processor
including microcontroller and USB
interface
Product specification
2001 May 04
Supersedes data of 2000 Dec 6
File under Integrated Circuits, IC22
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
FEATURES
• Embedded microcontroller (80C51 core based) for
control loops Auto Optical Black (AOB), Auto White
Balance (AWB), Auto Exposure (AE) and USB interface
control
• Compliant for VGA CCD and VGA CMOS sensors
(RGB Bayer)
• USB 1.1 compliant bus-powered USB device with
integrated power management and POR circuit
• RGB processing
APPLICATION
• Optical black processing
• USB PC-camera (video and audio).
• Defect pixel concealment
• Programmable colour matrix
GENERAL DESCRIPTION
• RGB to YUV transform
The SAA8116 is a highly integrated third generation
USB PC-camera ICs. It is the successor to the
SAA8112HL and SAA8115HL. It processes the digitized
sensor data and converts it to a high quality, compressed
YUV signal. Together with the audio signal, this video
signal is then properly formatted in USB packets.
• Programmable gamma correction (including knee)
• Programmable edge enhancement
• Video formatter with SIF/QSIF downscaler
• Compression engine
• Flexible Measurement Engine (ME) with up to eight
measurements per frame
In addition, an 80C51 microcontroller derivative with five
I/O ports, I2C-bus, 512 bytes of RAM and 32 kbytes of
program memory is embedded in the SAA8116. The
microcontroller is used in combination with the
• Internal Pulse Pattern Generator (PPG) for wide range
of VGA CCDs (Sony, Sharp and Panasonic) and frame
rate selection
programmable statistical measurement capabilities to
provide advanced AE, AWB and AOB. The microcontroller
is also used to control the USB interface.
• Programmable H and V timing for the support of CMOS
sensors
• Programmable output pulse for switched mode power
supply of the sensor
• 3-wire interface to control an external pre-processor IC,
such as the TDA8787A: Correlated Double
Sampling (CDS), Automatic Gain Control (AGC) and
10-bit ADC
• Analog microphone/audio input to USB: Low DropOut
(LDO) supply filter, microphone supply, low noise
amplifier, programmable amplifier, PLL and ADC
• Integrated analog USB driver (ATX)
• Integrated main oscillator, including a clock PLL, which
derives 48 MHz main system clock from a 12 or 48 MHz
fundamental crystal.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA8116HL LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
SOT407-1
SAA8116ET TFBGA112 plastic thin fine-pitch ball grid array package; 112 balls; body 7 × 7 × 0.8 mm SOT630-1
2001 May 04
2
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
QUICK REFERENCE DATA
Measured over full voltage and temperature range: VDD = 3.3 V ±10% and Tamb = 0 to 70 °C; unless specified.
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
3.0
TYP.
3.3
85(1)
MAX.
3.6
105(2)
UNIT
VDD
IDD(tot)
Vi
V
total supply current
input voltage
VDD = 3.3 V; Tamb = 25 °C (typ.)
3.0 V < VDD < 3.6 V
3.0 V < VDD < 3.6 V
note 3
−
mA
V
low voltage TTL compatible
low voltage TTL compatible
Vo
output voltage
V
f(i)xtal
δ
crystal input frequency
crystal frequency duty factor
−
12 or 48
−
MHz
%
−
50
280
−
−
Ptot
Tstg
Tamb
Tj
total power dissipation; note 1 VDD = 3.3 V; Tamb = 25 °C (typ.)
storage temperature
−
350
+150
70
mW
°C
°C
°C
−55
0
ambient temperature
25
−
junction temperature
Tamb = 70 °C
−40
+125
Notes
1. Typical: VGA at 15 fps.
2. Maximum: SIF at 30 fps.
3. The crystal input frequency can be 12 or 48 MHz, depending on the use of the internal CPLL (selectable via
pin XSEL).
2001 May 04
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
FV3, FV4
FV1, FV2 FH1, FH2
ROG
RG
BCP, DCP
SMP RESERVED1
RESERVED2, RESERVED3
H
V
ASCLK PCLK
10
CRST FS, FCDS
95
96
9
1, 2 3, 98 91, 90 93 97 92
5, 6 23, 24 94
64
83, 84
VSP
ANALOG MODULES
57
58
59
LDOIN
LDO
SUPPLY
FILTER
WINDOW TIMING AND
CONTROL REFERENCE TIMING
MODE
DECODER
PULSE PATTERN GENERATOR
LDOFIL
LDOOUT
11, 12,
13, 14,
15, 16,
17, 18,
19, 20
Y
MICROPHONE
SUPPLY
60
MICSUPPLY
PROCESSING
4 : 2 : 2
FORMATTER
PRE-
PROCESSING
RGB
RGB
PROCESSING
RGB TO
YUV
PXL9 to PXL0
RECONSTRUCTION
UV
AUDIO
LOW NOISE
AMPLIFIER
61
62
MICIN
PROCESSING
LNAOUT
25
27
26
STROBE
SDATA
SCLK
PRE-PROCESSING
MEASUREMENT ENGINE
INTERFACE
PROGRAMMABLE
AUDIO GAIN
63
PGAININ
AMPLIFIER
AUDIO PLL
AUDIO ADC
65,
66,
67
34
70
71
4
89
28
29
33, 32
V
GPI1
GPI2
GPI3
ref1,
ref2,
ref3
VIDEO
FORMATTER
COMPRESSION
ENGINE
TRANSFER
BUFFER
V
V
AUDIO
DECIMATION
3
LED
85
74
73
XSEL
XIN
XOUT
FULLPOWER
SNAPRES
PRIVRES
SDA, SCL
OSCILLATOR
AND CPLL
VFC
80C51
MICROCONTROLLER
54
49, 50
80
79
82
USB
INTERFACE
ATXDP
ATXDN
DELAYATT
EA
ALE, PSEN
ATX
48, 51, 47,
52, 46, 53,
45
86
69
AD14 to AD8
P0.7 to P0.0
SAA8116
PSEL
POWER
MANAGEMENT
39, 38, 40,
37, 41, 35,
42, 36
POR
PORE
2
3
2
6
8
8, 31, 44, 77,
88, 100, 55, 22
7, 30, 43,
76, 87, 99
72, 81
75, 78, 68
56, 21
FCE673
V
V
V
to
AGND1 to
AGND3
GND1 to
GND8
DDA1,
DDD1,
DD1
V
V
V
DDA2
DDD2
DD6
Fig.1 Block diagram (LQFP100).
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
FV3, FV4
FV1, FV2 FH1, FH2
ROG
RG
BCP, DCP
SMP RESERVED1
RESERVED2, RESERVED3
H
V
ASCLK PCLK
E3 E1
CRST FS, FCDS
A4
C4
D4, C2,
B1 A3
B5,
C6
C5 B3 A5
D2, K2,
D1 L1
B4
G10
A8,
B8
VSP
ANALOG MODULES
J12
J10
H11
LDOIN
LDO
SUPPLY
FILTER
WINDOW TIMING AND
CONTROL REFERENCE TIMING
MODE
DECODER
PULSE PATTERN GENERATOR
LDOFIL
LDOOUT
F2, F1,
G3, G1,
G2, H3,
H1, H2,
J3, J1
Y
MICROPHONE
SUPPLY
H12
MICSUPPLY
PROCESSING
4 : 2 : 2
FORMATTER
PRE-
PROCESSING
RGB
RGB
PROCESSING
RGB TO
YUV
PXL9 to PXL0
RECONSTRUCTION
UV
H10
G11
AUDIO
LOW NOISE
AMPLIFIER
MICIN
PROCESSING
LNAOUT
J4
STROBE
SDATA
SCLK
K3
M2
PRE-PROCESSING
MEASUREMENT ENGINE
INTERFACE
PROGRAMMABLE
AUDIO GAIN
G12
PGAININ
AMPLIFIER
AUDIO PLL
AUDIO ADC
M5
F12,
F11,
E12
GPI1
GPI2
GPI3
D12
D11
C1
A6
M3
V
ref1,
ref2,
ref3
VIDEO
FORMATTER
COMPRESSION
ENGINE
TRANSFER
BUFFER
V
V
AUDIO
DECIMATION
LED
3
FULLPOWER
SNAPRES
PRIVRES
SDA, SCL
C7
B12
C11
XSEL
XIN
XOUT
L3
K5, L4
OSCILLATOR
AND CPLL
VFC
80C51
MICROCONTROLLER
K11
EA
K10, M11
A9
A10
ALE, PSEN
USB
INTERFACE
ATXDP
ATXDN
DELAYATT
M10, M12,
L10, J9,
K9, L12,
M9
ATX
C8
AD14 to AD8
P0.7 to P0.0
A7
SAA8116
PSEL
POWER
MANAGEMENT
M7, L7, K7,
L6, L8, L5,
M8, K6
POR
D10
PORE
2
3
2
6
8
E2, M4, L9, A11,
B6, A2, K12, K1
D3, K4, K8,
B11, B7, C3
C12, B9
D9, C10, E11 J11, J2
MGU263
V
V
V
to
DD1
AGND1 to
AGND3
GND1 to
GND8
DDA1,
DDD1,
V
V
V
DDA2
DDD2
DD6
Fig.2 Block diagram (TFBGA112).
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
PINNING
SYMBOL
FV1
PIN(1) BALL(2) TYPE(3)
DESCRIPTION
1
2
D4
B1
C2
C1
D2
D1
D3
E2
E1
E3
O
O
O
O
O
O
P
P
I
vertical CCD transfer pulse output (or general purpose output)
vertical CCD transfer pulse output (or general purpose output)
vertical CCD transfer pulse output (or general purpose output)
output to drive LED
FV2
FV3
3
LED
4
FS
5
data sample-and-hold pulse output to TDA8787A (SHD)
preset sample-and-hold pulse output to TDA8787A (SHP)
supply voltage 1 for output buffers
FCDS
VDD1
GND1
PCLK
ASCLK
6
7
8
ground 1 for output buffers
9
pixel input clock
10
O
clock 1 (pixel clock) or clock 2 (2 × pixel clock) output for ADC or CMOS
sensor
PXL9
PXL8
PXL7
PXL6
PXL5
PXL4
PXL3
PXL2
PXL1
PXL0
VDDD2
GND8
BCP
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
F2
F1
G3
G1
G2
H3
H1
H2
J3
I
I
pixel data input; bit 9
pixel data input; bit 8
I
pixel data input; bit 7
I
pixel data input; bit 6
I
pixel data input; bit 5
I
pixel data input; bit 4
I
pixel data input; bit 3
I
pixel data input; bit 2
I
pixel data input; bit 1
J1
I
pixel data input; bit 0
J2
P
P
O
O
O
supply voltage 2 for the digital core
ground 8 for input buffers and predrivers
optical black clamp pulse output to TDA8787A
dummy clamp pulse output to TDA8787A
K1
K2
L1
J4
DCP
STROBE
strobe signal output to TDA8787A or general purpose output of the
microcontroller
SCLK
26
27
M2
K3
O
O
serial clock output to TDA8787A or general purpose output of the
microcontroller
SDATA
serial data output to TDA8787A or general purpose output of the
microcontroller
SNAPRES
PRIVRES
VDD2
28
29
30
31
32
33
34
35
36
M3
L3
I
snapshot input or remote wake-up trigger input (programmable)
privacy shutter input or remote wake-up trigger input (programmable)
supply voltage 2 for input buffers and predrivers
ground 2 for input buffers and predrivers
I2C-bus clock input/output (master/slave)
I2C-bus data input/output (master/slave)
I
K4
M4
L4
P
GND2
SCL
P
I/O
I/O
I
SDA
K5
M5
L5
GPI1
general purpose input 1 (Port 4; bit 6)
P0.2
I/O
I/O
microcontroller Port 0 bidirectional (data - address); bit 2
microcontroller Port 0 bidirectional (data - address); bit 0
P0.0
K6
2001 May 04
6
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
SYMBOL
P0.4
PIN(1) BALL(2) TYPE(3)
DESCRIPTION
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
L6
L7
I/O
I/O
I/O
I/O
I/O
I/O
P
microcontroller Port 0 bidirectional (data - address); bit 4
microcontroller Port 0 bidirectional (data - address); bit 6
microcontroller Port 0 bidirectional (data - address); bit 7
microcontroller Port 0 bidirectional (data - address); bit 5
microcontroller Port 0 bidirectional (data - address); bit 3
microcontroller Port 0 bidirectional (data - address); bit 1
supply voltage 3 for output buffers
P0.6
P0.7
P0.5
P0.3
P0.1
VDD3
GND3
AD8
M7
K7
L8
M8
K8
L9
P
ground 3 for output buffers
M9
K9
O
microcontroller Port 2 output (address); bit 0
microcontroller Port 2 output (address); bit 2
microcontroller Port 2 output (address); bit 4
microcontroller Port 2 output (address); bit 6
address latch enable output for external latch
program store enable output for external memory (active LOW)
microcontroller Port 2 output (address); bit 5
microcontroller Port 2 output (address); bit 3
microcontroller Port 2 output (address); bit 1
AD10
AD12
AD14
ALE
O
L10
M10
K10
M11
M12
J9
O
O
O
PSEN
AD13
AD11
AD9
O
O
O
L12
K11
O
EA
I
external access select input; internal (HIGH) or external (LOW)
program memory
GND7
55
56
57
58
59
K12
J11
J12
J10
H11
P
P
P
−
ground 7 for input buffers and predrivers
supply voltage 1 for the digital core
VDDD1
LDOIN
LDOFIL
LDOOUT
analog supply voltage for LDO supply filter
external capacitor connection (filter of LDO)
−
external capacitor connection (internal analog supply voltage for PLL;
amplifier and ADC)
MICSUPPLY
MICIN
LNAOUT
PGAININ
RESERVED1
Vref1
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
H12
H10
G11
G12
G10
F12
F11
E12
E11
D10
D12
D11
C12
C11
B12
D9
O
I
microphone supply output
microphone input
O
I
low noise amplifier output
programmable gain amplifier input
test pin 1 (should be floating)
O
I
reference voltage 1 (used in the amplifier and the ADC)
reference voltage 2 (used in the ADC)
reference voltage 3 (used in the ADC)
analog ground 3 for PLL; amplifier and ADC
external Power-on reset
Vref2
I
Vref3
I
AGND3
PORE
GPI2
P
I
I
general purpose input 2 (Port 1; bit 4)
general purpose input 3 (Port 3; bit 5)
analog supply voltage for crystal oscillator (12 MHz, fundamental)
oscillator output
GPI3
I
VDDA1
P
O
I
XOUT
XIN
oscillator input
AGND1
P
analog ground 1 for crystal oscillator
2001 May 04
7
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
SYMBOL
VDD4
PIN(1) BALL(2) TYPE(3)
DESCRIPTION
76
77
78
79
80
81
82
B11
A11
C10
A10
A9
P
P
supply voltage 4 for input buffers and predrivers
ground 4 for input buffers and predrivers
analog ground 2 for ATX transceiver
GND4
AGND2
ATXDN
ATXDP
VDDA2
P
I/O
I/O
P
negative driver of the differential data pair input/output (ATX)
positive driver of the differential data pair input/output (ATX)
analog supply voltage 2 for ATX transceiver
B9
DELAYATT
C8
O
delayed attach control output; connected with pull-up resistor on ATXDP
(USB)
RESERVED2
RESERVED3
XSEL
PSEL
VDD5
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
A8
B8
C7
A7
B7
B6
A6
C6
B5
A5
C5
B4
A4
C4
B3
A3
C3
A2
I
I
test pin 2 (should be connected to GND)
test pin 3 (should be connected to GND)
crystal selection input
I
I
POR selection input
P
P
O
O
O
O
O
O
O
I/O
O
O
P
P
supply voltage 5 for output buffers
ground 5 for output buffers
GND5
FULLPOWER
FH2
full power signal output (active LOW)
horizontal CCD transfer pulse output
horizontal CCD transfer pulse output
reset output for CCD output amplifier gate
vertical CCD load pulse output
FH1
RG
ROG
SMP
switch mode pulse output for CCD supply
horizontal synchronization pulse output
vertical synchronization pulse input/output
CCD charge reset output for shutter control
vertical CCD transfer pulse output
supply voltage 6 for output buffers
ground 6 for output buffers
H
V
CRST
FV4
VDD6
GND6
Notes
1. Pinning related to LQFP100 package.
2. Pinning related to TFBGA112 package.
3. I = input; O = output and P = power supply.
2001 May 04
8
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
FV1
FV2
1
2
3
4
5
6
7
8
9
AGND1
75
74 XIN
73 XOUT
V
FV3
LED
FS
72
71
DDA1
GPI3
FCDS
70 GPI2
V
PORE
69
68
67
66
65
64
63
DD1
GND1
PCLK
AGND3
V
ref3
V
ASCLK 10
PXL9 11
PXL8 12
PXL7 13
PXL6 14
PXL5 15
PXL4 16
PXL3 17
PXL2 18
PXL1 19
PXL0 20
ref2
V
ref1
RESERVED1
PGAININ
SAA8116
62 LNAOUT
MICIN
61
60
59
MICSUPPLY
LDOOUT
58 LDOFIL
LDOIN
57
56
V
DDD1
V
21
55 GND7
54 EA
DDD2
GND8 22
BCP 23
AD9
53
52
DCP 24
AD11
STROBE 25
51 AD13
FCE674
Fig.3 Pin configuration (LQFP100).
9
2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
FCE778
handbook, halfpage
M
L
K
J
H
G
SAA8116ET
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12
Fig.4 Ball configuration; bottom view of ball array (TFBGA112).
2001 May 04
10
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Pinning for TFBGA112
BALL
SYMBOL
BALL
SYMBOL
BALL
SYMBOL
D2
D3
FS
J12
K1
LDOIN
GND8
BCP
A1
A2
n.c.
VDD1
FV1
GND6
FV4
D4
K2
A3
D9
AGND1
PORE
GPI3
K3
SDATA
VDD2
SDA
A4
H
D10
D11
D12
E1
K4
A5
RG
K5
A6
FULLPOWER
PSEL
RESERVED2
ATXDP
ATXDN
GND4
n.c.
GPI2
K6
P0.0
A7
PCLK
GND1
ASCLK
n.c.
K7
P0.5
A8
E2
K8
VDD3
AD10
ALE
A9
E3
K9
A10
A11
A12
B1
E10
E11
E12
F1
K10
K11
K12
L1
AGND3
Vref3
EA
GND7
DCP
FV2
PXL8
B2
n.c.
F2
PXL9
L2
n.c.
B3
CRST
SMP
F3
n.c.
L3
PRIVRES
SCL
B4
F10
F11
F12
G1
n.c.
L4
B5
FH1
Vref2
L5
P0.2
B6
GND5
VDD5
Vref1
L6
P0.4
B7
PXL6
L7
P0.6
B8
RESERVED3
VDDA2
n.c.
G2
PXL5
L8
P0.3
B9
G3
PXL7
L9
GND3
AD12
n.c.
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
G10
G11
G12
H1
RESERVED1
LNAOUT
PGAININ
PXL3
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
VDD4
XIN
AD9
LED
n.c.
FV3
H2
PXL2
SCLK
SNAPRES
GND2
GPI1
n.c.
VDD6
H3
PXL4
V
H10
H11
H12
J1
MICIN
LDOOUT
MICSUPPLY
PXL0
ROG
FH2
XSEL
DELAYATT
n.c.
P0.7
J2
VDDD2
PXL1
P0.1
J3
AD8
AGND2
XOUT
VDDA1
FCDS
J4
STROBE
AD11
AD14
PSEN
AD13
J9
J10
J11
LDOFIL
VDDD1
2001 May 04
11
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
FUNCTIONAL DESCRIPTION
The HV timing module can serve both as master or slave.
When serving as a slave, the V pulse only is needed since
the H pulse is internally derived from V by programming
the number of pixels per line.
The SAA8116 video processor has a very high level of
programmability: 118 (8-bit) registers are dedicated for the
Video Signal Processor (VSP), including Pulse Pattern
Generator (PPG) and Measurement Engine (ME), plus
23 registers for the Video Formatter and
VIDEO WINDOWS
Compressor (VFC). The SAA8116 can accept 8 to 10-bit
digital data from various VGA sensors: CCD (progressive)
or CMOS, with or without colour filters (see Table 1).
Several registers allow the definition of the optical black
window, the active video input window, the active video
output window and the measurement windows.
Synchronization and video windows
Table 1 Typical SAA8116 compatible sensors
CCD SENSOR PULSE PATTERN GENERATOR
SENSOR
TYPE
BRAND
PART NUMBER
The SAA8116 incorporates a PPG function, which can be
used for VGA CCD sensors, see Table 1.
VGA CCD
Sony
ICX098AK
Panasonic MN37771PT
Depending on the sensor type, an external inverter driver
is required to convert the 3.3 V pulses to a voltage suitable
for the CCD sensor used.
Sharp
LZ24BP
VGA CMOS
Philips
UPA1021
HV7131B
PB-0320
Hyundai
Photobit
The active video size is 640 × 480 for VGA. The total H × V
size is 823 × 486 for VGA.
Other sensors all sensors that fulfil the following
criteria:
A total of 19 internal registers make a high level of
flexibility available for the PPG.
• B and W; RGB Bayer colour filter
• 8-bit, 9-bit or 10-bit output
• CMOS or CCD sensors
• progressive
FLEXIBLE HV TIMING
The PPG module is not used with CMOS sensors. The
SAA8116 provides some flexibility on the frame size to
increase the range of applicable sensors (see Table 1). It
is possible to program the position, width and polarity of
the H and V signals. The output clock for the CMOS
sensor is selectable between single and double pixel
clock, including a programmable polarity.
2001 May 04
12
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Video signal processor
DEFECT PIXEL CONCEALMENT
OPTICAL BLACK PROCESSING
Up to 128 Defect Pixel Coordinates (DPC) can be taken
into account for concealment. The method is based either
on a horizontal linear interpolation, or on a copy of a
neighbouring pixel of the same colour.
The first processing block of the SAA8116 is a digital
clamp (denoted as PRE-PROCESSING in Fig.1). It is used
to align the optical black level to zero or to any arbitrary
value.
RGB COLOUR RECONSTRUCTOR
The average value of the black is measured in the
programmable optical black window and sent to the
microcontroller for adjustment, if necessary. The value
fixed by the microcontroller is subtracted from the
incoming data stream.
In the RGB colour reconstructor (denoted as RGB
RECONSTRUCTION in Fig.1), an RGB triplet is
interpolated for every pixel on a 3 × 3 neighbourhood
matrix.
With B and W sensors, the RGB colour reconstructor can
be disabled, thus maintaining the full sensor resolution.
The optical black window has a fixed size of 16 pixels
(horizontally) by 128 (vertically); the position of this
window is fully programmable.
Vertical contours and video level information (white clip)
are extracted at this stage (see Fig.5).
Each of the four colour filter inputs has its own offset and
gain.
LINE
MEMORY
R
G
RGB
B
COLOUR
LINE
MEMORY
SEPARATION
White clip
CCD inputs
10
Edges
FCE340
Fig.5 RGB reconstructor diagram.
2001 May 04
13
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
COLOUR MATRIX
A programmable 3 × 3 colour matrix (see Fig.6) is used to convert the extracted colour information, R, G and B from the
sensor colour space to a standard RGB colour space.
With B and W sensors, a unity matrix is used.
To control the white balance, the gain of the red and blue stream can be changed.
Gamma and knee are combined in one function with adjustable gain.
R
gain
R or (2R-G)
G or Y
R
G
×
GAMMA/
KNEE
COLOUR
MATRIX
B
gain
B
B or (2B-G)
×
FCE742
Fig.6 RGB processing diagram.
YUV PROCESSING
The chrominance processing consists of a colour killer
(white clip) and a UV gain control (see Fig.8). Processing
is done on the multiplexed two-times-downsampled
UV chrominance signals. The sensor input is used to kill
the colour of over-exposed pixels. It is possible to adjust
the number of pixels on which the correction is applied.
Following the RGB processing, the R, G and B signals are
converted to YUV 4 : 2 : 2 by a fixed matrix (see Fig.7).
Then, the luminance and chrominance signals are
processed separately.
The luminance processing consists of edge enhancement.
This feature is very flexible. First, it is possible to adjust the
bandwidth and the level of the edge detection. Secondly,
the amount of edge enhancement can be independently
adjusted for the horizontal or vertical edge or for the high
or low frequency edge.
The YUV processing block concludes with separate gain
controls on the Y, U and V signals. These gains can be
used to fine tune the Y, U and V colour balance and also
to adjust the luminance and saturation without disturbing
the AE and AWB control loops.
R
G
B
Y
handbook, halfpage
UV GAIN
CONVERSION
MATRIX
WHITE CLIP
UV
UV
DOWN-
SAMPLING
AND MUX
CONTROL
UV
FCE743
FCE342
Fig.7 RGB to YUV conversion.
Fig.8 UV processing.
2001 May 04
14
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
MEASUREMENT ENGINE
Table 2 Scaler modes
The ME extracts statistical information from the video
stream. These measurements are used for the
auto-control loops in the microcontroller (AWB, AE
and AGC). They can also be used for other purposes, such
as colour detection. The measurements are performed on
pre-formatted Y, U and V streams. It is possible to
measure the accumulated value of the Y, U or V samples
either in the full active video window or in a simple
programmable window.
SENSOR
TYPE
OUTPUT
FORMAT
SCALER MODES
VGA
SIF 320 × 240
scaled half horizontally
and vertically
QSIF 160 × 120 scaled quarter
horizontally and vertically
Compression engine
The compression engine module (see Fig.9) can process
VGA, SIF and QSIF, based on a Philips proprietary
algorithm. The compression ratio is continuously
programmable by setting a maximum bit cost limit. Input
data can also be a raw RGB sensor data to perform
optimum snapshot processing in the host software.
Five parallel measurements of the luminance can be done
for the auto exposure, each based on a proper window.
Y, U and V can be measured independently for the auto
white balance, all based on the same window.
During each frame, the microcontroller has access to the
measured values of the previous frame.
The compression engine uses several strategies and
Q-tables for optimum performance at a wide range of
compression ratios (up to 8×). The required table must be
selected via software. One table is optimized for
compressing the raw VGA data.
Video formatter
This block is used to convert the YUV 4 : 2 : 2 format to
4 : 2 : 0 required by the compression engine. The
incoming 4 : 2 : 2 data is vertically filtered. In raw mode,
this block is bypassed to create a full resolution snapshot.
Real time decoding can be done in software on any
Pentium or AMD-K6 platform.
The formatter can also perform downscaling to SIF and
QSIF (see Table 2).
To avoid aliasing, this formatter also contains horizontal
and vertical low pass pre-filters before downscaling.
PREFILTER_SEL_UV
PREFILTER_SEL_Y
to
DATA FORMATTER
COMPRESSION
transfer
YUV7 to
YUV0
HORIZONTAL
DOWNSCALING
PREFILTER
+
ENGINE
buffer
VERTICAL
DOWN SAMPLING
VF_LIMITER
TABLE_SELECT
LDC
SCALE_DATA
C_BITCOST_MSB
C_BITCOST_LSB
C_THRESHOLD_MSB
C_THRESHOLD_LSB
FCE744
Fig.9 The video formatter and compression engine.
15
2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 3 gives the available output formats and frame rates.
Table 3 Video formats
FORMAT
FRAME RATE
COMPRESSION MODE
VGA
SIF
5
raw; compressed
compressed
compressed
compressed
compressed
5
10
15
30
5
compressed and uncompressed
compressed
10
15
20
24
30
5
compressed
compressed
compressed
compressed
QSIF
compressed and uncompressed
compressed and uncompressed
compressed and uncompressed
compressed and uncompressed
compressed and uncompressed
compressed and uncompressed
10
15
20
24
30
The compressed data is streamed into a video FIFO, ready to be packed into USB formatted data blocks.
2001 May 04
16
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Universal serial bus 1.1 core
The video FIFO size allows demarcation of the video
frames using one or more 0-length packets.
The USB core combines all functionalities for a USB 1.1
compliant full speed device. It formats the actual packets
(video and audio) that are transferred to the USB and
passes the incoming packets to the right end-point buffer.
The end-point setup is composed of control, generic and
isochronous types (see Table 4). All end-points can be
enabled or disabled, except control end-points.
The core also includes VID class support for the video
end-point: headers and trailers enable data to be attached
to the video frames that are passed over the USB. Eight
1-byte registers are dedicated for the headers, while four
registers comprise the trailers. Each of the registers can be
programmed by the microcontroller. An extra register,
TR_HT_CONTROL, specifies how many bytes are
inserted before or after the video data.
All enabled end-points generate interrupts to the
embedded microcontroller when they need to be serviced.
The microcontroller can then use a set of commands via
the internal parallel interface.
Table 4 Mapping of logical to physical end-point numbers for the end-points
LOGICAL
END-POINT
PHYSICAL
END-POINT
DOUBLE
BUFFERED
END-POINT TYPE
DIRECTION BUFFER SIZE
0
1
0
1
2
3
4
5
6
7
control
control
out
in
16
16
8
no
no
no
no
no
no
yes
generic
out
in
generic
8
2
3
4
5
generic
in
8
generic
in
8
isochronous
isochronous
in
92
in
programmable multi-buffered
ATX interface
A parallel interface is used to communicate with all internal
modules, based on the MOVX@DPTR instruction.
The SAA8116 contains an analog bus driver, called
the ATX. This driver incorporates a differential amplifier
and two single-ended buffers for the receiver part and two
single-ended buffers for the transmitter part.
The microcontroller includes the following features:
• 32 kbytes internal ROM
• 512 bytes RAM
The interface to the bus consists of a differential data pair
(ATXDN and ATXDP).
• Hardware multi-master I2C-bus interface (the
microcontroller can be used either as slave or master):
P1.7 and P1.6
Microcontroller
• Power-down mode
• Two timers
The embedded microcontroller is an 80C654 core (80C51
family). Ports P0 and P2 (plus ALE and PSEN) are
available for connection to an emulator or to an external
program EPROM (32 kbytes max.).
• P0 and P2 are pull-up ports
• Three pins are available as general purpose inputs:
GPI1 (P4.6), GPI2 (P1.4) and GPI3 (P3.5).
The microcontroller can control the AOB, AE and AWB
loops, and can download the settings for the internal
registers from an optional EEPROM at power-up or reset.
2001 May 04
17
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 5 80C51 Special Function Registers (SFR)
DATA BIT
SFR
NAME
SFR
ADDRESS
DESCRIPTION
7
6
5
4
3
2
1
0
B
B register
accumulator
F0H
E0H
DBH
DAH
D9H
D8H
D0H
C0H
B8H
B0H
A8H
A0H
99H
98H
90H
8DH
8CH
8BH
8AH
89H
88H
87H
83H
82H
81H
80H
B7
B6
B5
B4
B3
B2
B1
B0
ACC
ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
SIADR serial interface address
SIDAT serial interface data
SISTA serial interface status
SICON serial interface control
SA6
SD7
ST7
CR2
CY
SA5
SD6
ST6
ENS1
AC
SA4
SD5
ST5
STA
F0
SA3
SD4
ST4
STO
RS1
P4.4
IP4
SA2
SD3
ST3
SI
SA1
SD2
0
SA0
SD1
0
GC
SD0
0
AA
CR1
−
CR0
P
PSW
P4
IP
program status word
Port 4
RS0
P4.3
PT1
INT1
ET1
OV
P4.7
−
P4.6
IP6
P4.5
IP5
P4.2
PX1
INT0
EX1
P4.1
PT0
TXD
ET0
AD9
−
P4.0
PX0
RXD
EX0
AD8
−
interrupt priority
Port 3
P3
IE
RD
WR
T1
T0
interrupt enable
Port 2
EA
IE6
IE5
IE4
P2
(AD15) AD14 AD13 AD12 AD11 AD10
SBUF serial data buffer
SCON serial controller
−
SM0
SDA
−
−
SM1
SCL
−
−
SM2
P1.5
−
−
REN
P1.4
−
−
TB8
P1.3
−
−
RB8
P1.2
−
T1
R1
P1.0
−
P1
Port 1
P1.1
−
TH1
TH0
TL1
TL0
timer high 1
timer high 0
timer low 1
timer low 0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TMOD timer mode
TCON timer control
PCON power control
GATE
TF1
−
C/T
TR1
−
M1
TF0
−
M0
TR0
−
GATE
IE1
−
C/T
IT1
−
M1
IE0
PD
−
M0
IT0
IDL
−
DPH
DPLl
SP
data pointer high
data pointer low
stack pointer
Port 0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
SP7
P0.7
SP6
P0.6
SP5
P0.5
SP4
P0.4
SP3
P0.3
SP2
P0.2
SP1
P0.1
SP0
P0.0
P0
Audio
The PLL converts the 48 MHz to 256fs (fs = audio sample
frequency). There are three modes for the PLL to achieve
the sample frequencies of 48, 44.1 and 32 kHz or their
derivatives (see Table 6).
The SAA8116 contains a microphone supply, including a
low-drop electronic supply filter, and an amplifier circuit
composed of two stages: a Low Noise Amplifier (LNA) and
a variable gain amplifier (VGA). The LNA has a fixed gain
of 30 dB while the VGA can be programmed between
0 and 30 dB in steps of 2 dB. The frequency transfer
characteristic of the audio path must be controlled via
external high-pass or low-pass filters.
The bitstream ADC samples the mono audio signal. It runs
at an oversample rate of 256 times the base sample rate.
A decimator filter transforms the bitstream output to 16-bit
samples.
A digital mute option is available.
2001 May 04
18
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 6 ADC clock frequencies and sample frequencies
CLOCK PLL
The SAA8116 runs on an internal master clock of 48 MHz,
which can be derived from either a 48 or 12 MHz
fundamental crystal. When it is derived from a 12 MHz
fundamental crystal, an internal clock PLL transfers the
12 MHz to 48 MHz, with a 50% duty cycle.
SAMPLE
FREQUENCY
(kHz)
CLOCK
(MHz)
DIVIDING
NUMBER
ADC CLOCK
(MHz)
8.1920
1
2
4
8
1
2
4
8
1
2
4
8
32
16
4.096
2.048
1.042
note 1
5.6448
2.8224
1.4112
0.7056
6.144
3.072
1.536
0.768
A 48 MHz third overtone crystal can also be used but
requires an external LC circuit.
8
note 1
44.1
22.05
11.025
5.5125
48
11.2896
12.2880
RING OSCILLATOR
To generate several time constants for power state
switching, a digital counter running on an integrated ring
oscillator is incorporated, thus saving pins and commonly
used external RC components.
24
POWER-ON RESET (POR)
12
A POR function is integrated to generate a reset during the
start-up of the power supply and during a power fail. It
includes a fixed threshold detector (2.6 V) and a reset
generator. The reset output has a built-in delay with a
duration determined by the ring oscillator (around 100 ms).
6
Note
1. Not supported.
An external POR can be used.
Power management
USB requires the device to switch power states. The
SAA8116 contains a power management module since
the complete camera may not consume more than 500 µA
during the SUSPEND power state. This requires that even
the crystal oscillator must be switched off. The SAA8116 is
not functional except for some logic that enables the IC to
wake up the camera.
MODE CONTROL
Two pins are dedicated to control the operational modes of
the SAA8116 (see Table 7).
Table 7 Mode control
XS
PS
MODE
The SAA8116 incorporates remote wake-up (on two pins)
to signal the host to resume operation when triggered.
0
0
application mode (48 MHz crystal;
internal POR)
The power management module also sets a flag in register
POWERMGT_STATUS. After a reset, the microcontroller
should check this register and find the cause of the
wake-up. Different causes may require different start-up
routines.
0
1
1
1
0
1
application mode (48 MHz crystal;
external POR)
application mode (12 MHz crystal;
internal POR)
application mode (12 MHz crystal;
external POR)
Miscellaneous functions
Some additional functions are integrated in the SAA8116
to provide a cost effective application.
SERIAL INTERFACE WITH THE PRE-PROCESSOR
With CCD image sensors, the pre-processor (e.g.
TDA8787A) is controlled over a 3-wire serial interface. It is
adapted to shift out 16 bit settings. For flexibility, the output
pins can also be programmed as three general output pins
using register PIN_CONFIG_1.
2001 May 04
19
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
CONTROL REGISTER DESCRIPTION
of the modules (via Port 2), while register addresses and
data are exchanged via Port 0.
This specification gives an overview of all internal
registers. Several modules (VSP, VFC, PPG, USB, audio
and power management) communicate with the internal
microcontroller via a common parallel interface. The
protocol is based on a standard MOVX@DPTR
VSP, VFC and PPG registers
A first MOVX@DPTR instruction enables to select the
module (via DPH) and the register address. A second one
communicates the data (read or write).
instruction. A relative address (DPH) is used to select one
Table 8 Register list
ADDRESS
NAME
FUNCTION
FORMAT
RANGE
Write registers
0
1
2
0x00H VSP_CONTROL0
0x01H VSP_CONTROL1
control register for VSP data path see Table 9 n.a.
control register for VSP data path see Table 10 n.a.
0x02H OB_K1
0x03H OB_K2
0x04H OB_K3
0x05H OB_K4
fixed optical black level for
K1 pixel
byte
byte
byte
byte
[−128 to 127]
[−128 to 127]
[−128 to 127]
[−128 to 127]
3
4
5
fixed optical black level for
K2 pixel
fixed optical black level for
K3 pixel
fixed optical black level for
K4 pixel
6
7
8
9
0x06H PRE_MAT_K1
0x07H PRE_MAT_K2
0x08H PRE_MAT_K3
0x09H PRE_MAT_K4
pre-gain for K1 pixel
byte
byte
byte
byte
byte
pre-gain for K2 pixel
pre-gain for K3 pixel
pre-gain for K4 pixel
10 0x0AH WHITE_CLIP_THR
11 0x0BH reserved
threshold for white clip detector
768 + [0 to 255]
12 0x0CH COL_MAT_P11
13 0x0DH COL_MAT_P12
14 0x0EH COL_MAT_P13
15 0x0FH COL_MAT_P21
16 0x10H COL_MAT_P22
17 0x11H COL_MAT_P23
18 0x12H COL_MAT_P31
19 0x13H COL_MAT_P32
20 0x14H COL_MAT_P33
21 0x15H COL_MAT_RGAIN
colour matrix coefficient p11
colour matrix coefficient p12
colour matrix coefficient p13
colour matrix coefficient p21
colour matrix coefficient p22
colour matrix coefficient p23
colour matrix coefficient p31
colour matrix coefficient p32
colour matrix coefficient p33
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[−128 to 127]/16
[0 to 255]/128
red gain for white balance
correction
22 0x16H COL_MAT_BGAIN
blue gain for white balance
correction
byte
[0 to 255]/64
23 0x17H GAMMA_KNEE
24 0x18H VC_CNTRL
25 0x19H CLDLEV
control of gamma/knee level
vertical contour control
see Table 11 n.a.
see Table 12 n.a.
contour level dependency level
byte
[0 to 255]/2
2001 May 04
20
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ADDRESS
NAME
FUNCTION
FORMAT
nibble
RANGE
26 0x1AH HCLGAIN/HCHGAIN
horizontal contour BPF low gain
(MS)/horizontal contour BP high
gain (LS)
[0 to 15]/16
27 0x1BH CNCLEV
28 0x1CH CONGAIN
29 0x1DH YGAIN
30 0x1EH UGAIN
31 0x1FH VGAIN
32 0x20H AWB_A
33 0x21H AWB_B
34 0x22H AWB_C
35 0x23H AWB_D
36 0x24H AWB_E
37 0x25H AWB_F
38 0x26H reserved
39 0x27H DMWSEL
contour noise coring level
contour gain factor
Y gain factor (luminance)
U (B - Y) gain factor
V (R - Y) gain factor
AWB_A (ME)
6 bits
6 bits
byte
byte
byte
byte
byte
byte
byte
byte
byte
[0 to 63]/2
[0 to 63]/16
[0 to 255]/128
[0 to 255]/128
[0 to 255]/128
[−128 to 127]/128
[−128 to 127]/128
[−128 to 127]/128
[−128 to 127]/128
[0 to 255]
AWB_B (ME)
AWB_C (ME)
AWB_D (ME)
AWB_E (ME)
AWB_F (ME)
[0 to 255]
display measurement window
select
see Table 13 n.a.
see Table 14 n.a.
40 0x28H DISPLEV
display level in use with several
display functions
41 0x29H DIG_SETUP
42 0x2AH PRE_SI_LSB
setup in digital output
byte
byte
[0 to 255]
control data (LS byte) for analog
processing
[0 to 255]
[0 to 255]
[0 to 255]
43 0x2BH PRE_SI_MSB
control data (MS byte) for analog byte
processing
44 0x2CH PIXCNT_PRESET_LSB
45 0x2DH NLINE_PRESET_MSB
46 0x2EH LINECNT_PRESET_LSB
preset value of pixel counter (by
default = 0)
byte
number of lines per frame + MSBs see Table 15 n.a.
of preset register (by default = 6)
preset value for line counter; line byte
number 0 is undefined (by
default = 1)
[1 to 255]
47 0x2FH NPIX
number of pixels per line (by
default = 55)
byte
768 + [0 to 255]
48 0x30H CTR_UPD_LINE
number of line for double buffer
update control registers
byte
1 + 2 × [0 to 255]
49 0x31H OB_STARTLINE
first line optical black window
first pixel optical black window
byte
byte
4 bits
2 × [0 to 255]
4 × [0 to 255]
[0 to 15]
50 0x32H OB_STARTPIXEL
51 0x33H PIX_START_ACTWIN_ME
starting position of the active
window defining the ME windows
(by default = 15)
52 0x34H HREFSTART
position of positive edge of HREF 4 bits
on a line (by default = 3)
2 × [0 to 15]
53 0x35H HOUT_PE_LSB
position of positive edge of HOUT byte
[0 to 255]
2001 May 04
21
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ADDRESS
NAME
FUNCTION
FORMAT
byte
RANGE
54 0x36H HOUT_NE_LSB
55 0x37H VOUT_HPE_LSB
56 0x38H VOUT_VPE_LSB
57 0x39H VOUT_HNE_LSB
58 0x3AH VOUT_VNE_LSB
59 0x3BH VHOUT_MSB_1
60 0x3CH VHOUT_MSB_2
61 0x3DH HOUTWIN_VPE_LSB
62 0x3EH HOUTWIN_VNE_LSB
63 0x3FH XSEL
position of negative edge of
HOUT
[0 to 255]
horizontal position of positive
edge of VOUT
byte
byte
byte
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
vertical position of positive edge
of VOUT
horizontal position of negative
edge of VOUT
vertical position of negative edge byte
of VOUT
MSB of VHOUT position
definitions (part 1)
see Table 16 n.a.
MSB of VHOUT position
definitions (part 2)
see Table 17 n.a.
vertical position of positive edge
of HOUT window
byte
[0 to 255]
[0 to 255]
vertical position of negative edge byte
of HOUT window
selects the number of extended
active pixels (by default = 0)
see Table 18 n.a.
64 0x40H ME_WIN_START_AWB
65 0x41H ME_WIN_STOP_AWB
66 0x42H ME_WIN_START_AE_0
67 0x43H ME_WIN_STOP_AE_0
68 0x44H ME_WIN_START_AE_1
69 0x45H ME_WIN_STOP_AE_1
70 0x46H ME_WIN_START_AE_2
71 0x47H ME_WIN_STOP_AE_2
72 0x48H ME_WIN_START_AE_3
73 0x49H ME_WIN_STOP_AE_3
74 0x4AH ME_WIN_START_AE_4
75 0x4BH ME_WIN_STOP_AE_4
76 0x4CH DPCRAMPTR
AWB_window (Vstart; Hstart)
AWB_window (Vstop; Hstop)
byte
byte
AE_window no. 0 (Vstart; Hstart) byte
AE_window no. 0 (Vstop; Hstop) byte
AE_window no. 1 (Vstart; Hstart) byte
AE_window no. 1 (Vstop; Hstop) byte
AE_window no. 2 (Vstart; Hstart) byte
AE_window no. 2 (Vstop; Hstop) byte
AE_window no. 3 (Vstart; Hstart) byte
AE_window no. 3 (Vstop; Hstop) byte
AE_window no. 4 (Vstart; Hstart) byte
AE_window no. 4 (Vstop; Hstop)
RAM write pointer for DPC RAM
RAM write data DPC RAM
byte
byte
byte
3 × [0 to 127]
77 0x4DH DPCRAMDATA
[0 to 255]
78 0x4EH reserved
79 0x4FH reserved
80 0x50H TR_HEADER #0
81 0x51H TR_HEADER #1
82 0x52H TR_HEADER #2
83 0x53H TR_HEADER #3
84 0x54H TR_HEADER #4
85 0x55H TR_HEADER #5
86 0x56H TR_HEADER #6
data for header byte no. 0
data for header byte no. 1
data for header byte no. 2
data for header byte no. 3
data for header byte no. 4
data for header byte no. 5
data for header byte no. 6
byte
byte
byte
byte
byte
byte
byte
2001 May 04
22
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ADDRESS
NAME
FUNCTION
FORMAT
byte
RANGE
87 0x57H TR_HEADER #7
88 0x58H TR_TRAILER #0
89 0x59H TR_TRAILER #1
90 0x5AH TR_TRAILER #2
91 0x5BH TR_TRAILER #3
92 0x5CH TR_HT_CONTROL
93 0x5DH SMP_PERIOD
data for header byte no. 7
data for trailer byte no. 0
data for trailer byte no. 1
data for trailer byte no. 2
data for trailer byte no. 3
header trailer control
byte
byte
byte
byte
see Table 19 n.a.
SMP period in
byte
1 + [0 to 255]
units 4 × clk48_period
94 0x5EH SMP_LOWTIME
SMP low time in units
byte
1 + [0 to 255]
4 × clk48_period
95 0x5FH reserved
96 0x60H PPG_CONTROL_0
PPG control register 0
(by default = 0)
see Table 20 n.a.
see Table 21 n.a.
see Table 22 n.a.
97 0x61H PPG_CONTROL_1
98 0x62H PPG_H_CTRL
99 0x63H PPG_V_INV
PPG control register 1
(by default = 64)
controls mode of FH1; FH2
and RG (by default = 0)
controls inversion of vertical FV1; see Table 23 n.a.
FV2; FV3; FV4 and ROG signals
(by default = 0)
100 0x64H PPG_H_INV
controls inversion of horizontal
signals (by default = 0)
see Table 24 n.a.
101 0x65H PPG_MISC_INV
controls inversion of misc. signals see Table 25 n.a.
and sets additional mode controls
(by default = 0)
102 0x66H PPG_SHUTTERSPEED_V_LSB shutter speed line number
(by default = 0)
see Table 26
103 0x67H PPG_SHUTTERSPEED_H_LSB shutter speed CRST start
(by default = 0)
see Table 27
104 0x68H PPG_SHUTTERSPEED_MSB
MSB for shutter speed control
(line number; CRST start)
(by default = 0)
see Table 28 n.a.
105 0x69H PPG_BCP_START_LSB
106 0x6AH PPG_BCP_STOP_LSB
107 0x6BH PPG_DCP_START_LSB
108 0x6CH PPG_DCP_STOP_LSB
109 0x6DH PPG_BCP_DCP_MSB
starting position control for BCP
pulse (by default = 0)
see Table 29
stopping position control for BCP see Table 30
pulse (by default = 0)
starting position control for DCP
pulse (by default = 0)
see Table 31
stopping position control for DCP see Table 32
pulse (by default = 0)
MSB for start/stopping position
control for BCP/DCP pulses
(by default = 0)
see Table 33
110 0x6EH PPG_ROG1_START_LSB
2001 May 04
starting position control for ROG1 see Table 34
pulse (by default = 0)
23
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ADDRESS
NAME
FUNCTION
FORMAT
see Table 35
RANGE
111 0x6FH PPG_ROG1_STOP_LSB
112 0x70H PPG_ROG2_START_LSB
113 0x71H PPG_ROG2_STOP_LSB
114 0x72H PPG_ROG1_2_MSB
stopping position control for
ROG1 pulse (by default = 0)
starting position control for ROG2 see Table 36
pulse (by default = 0)
stopping position control for
ROG2 pulse (by default = 0)
see Table 37
MSB for start/stopping position
control for ROG1/2 pulses
(by default = 0)
see Table 38
115 0x73H VFC_CONTROL_0
116 0x74H VFC_CONTROL_1
control register for video formatter see Table 39 n.a.
and compression module
(by default = 1)
control register for video formatter see Table 40 n.a.
and compression module
(by default = 0)
117 0x75H VF_LIMITER
sets value for limiter output of
video formatter (by default = 0)
byte
byte
byte
byte
[0 to 255]
118 0x76H C_bitcost_MSB
119 0x77H C_bitcost_LSB
120 0x78H C_THRESHOLD_MSB
bit cost for compression module
(MSB) (by default = 0)
28 × [0 to 255]
[0 to 255]
bit cost for compression module
(LSB) (by default = 0)
fixed length coding threshold for
compression module (MSB)
(by default = 0)
28 × [0 to 255]
121 0x79H C_THRESHOLD_LSB
fixed length coding threshold for
compression module (LSB)
(by default = 0)
byte
[0 to 255]
122 0x7AH TR_CONTROL
control register for transfer module bit
(video processing) (by default = 0)
n.a.
123 0x7BH VFC_VS_V_SHFT
V_shift of internal line counter
3 bits
[0 to 7]
w.r.t. the VS pulse (by default = 0)
124 0x7CH reserved
125 0x7DH reserved
126 0x7EH PIN_CONFIG_0
127 0x7FH PIN_CONFIG_1
control pin configuration
control pin configuration
see Table 41 n.a.
see Table 42 n.a.
Read registers
192 0xC0H ME_AWB_Y_MSB
193 0xC1H ME_AWB_U_MSB
194 0xC2H ME_AWB_V_MSB
195 0xC3H ME_AE_#0_MSB
196 0xC4H ME_AE_#1_MSB
197 0xC5H ME_AE_#2_MSB
198 0xC6H ME_AE_#3_MSB
199 0xC7H ME_AE_#4_MSB
MSB part of ME_AWB_Y
MSB part of ME_AWB_U
MSB part of ME_AWB_V
MSB part of ME_AE_no. 0
MSB part of ME_AE_no. 1
MSB part of ME_AE_no. 2
MSB part of ME_AE_no. 3
MSB part of ME_AE_no. 4
byte
byte
byte
byte
byte
byte
byte
byte
[0 to 31]
[0 to 31]
[0 to 31]
[0 to 31]
[0 to 31]
[0 to 31]
[0 to 31]
[0 to 31]
2001 May 04
24
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ADDRESS
NAME
FUNCTION
FORMAT
byte
RANGE
200 0xC8H ME_AWB_Y_ISB
201 0xC9H ME_AWB_U_ISB
202 0xCAH ME_AWB_V_ISB
203 0xCBH ME_AE_#0_ISB
204 0xCCH ME_AE_#1_ISB
205 0xCDH ME_AE_#2_ISB
206 0xCEH ME_AE_#3_ISB
207 0xCFH ME_AE_#4_ISB
208 0xD0H ME_AWB_Y_LSB
209 0xD1H ME_AWB_U_LSB
210 0xD2H ME_AWB_V_LSB
211 0xD3H ME_AE_#0_LSB
212 0xD4H ME_AE_#1_LSB
213 0xD5H ME_AE_#2_LSB
214 0xD6H ME_AE_#3_LSB
215 0xD7H ME_AE_#4_LSB
216 0xD8H ME_OB_LEVEL
217 0xD9H READBACK_RGAIN
ISB part of ME_AWB_Y
ISB part of ME_AWB_U
ISB part of ME_AWB_V
ISB part of ME_AE_no. 0
ISB part of ME_AE_no. 1
ISB part of ME_AE_no. 2
ISB part of ME_AE_no. 3
ISB part of ME_AE_no. 4
LSB part of ME_AWB_Y
LSB part of ME_AWB_U
LSB part of ME_AWB_V
LSB part of ME_AE_no. 0
LSB part of ME_AE_no. 1
LSB part of ME_AE_no. 2
LSB part of ME_AE_no. 3
LSB part of ME_AE_no. 4
measured optical black level
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
[0 to 255]
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
read back of double-buffered
RGAIN
218 0xDAH READBACK_BGAIN
read back of double-buffered
BGAIN
byte
[0 to 255]
Table 9 Register CONTROL 0 (address: 0x00H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
EN_CLK_DPC_RAM: control defect pixel concealment RAM clock
0
1
disabled
enabled
EN_DPC: control defect pixel concealment
0
1
disabled
enabled
CLK_IF_RESET: control clk1/clk2 interface
free running (by default)
reset
0
1
X
toggle phase for line in colour separation
toggle phase for pixel in colour separation
reserved
X
X
FORCE_AWBVAL: control AWB window
enabled
0
1
disabled (integral AWB measurement)
reserved
X
2001 May 04
25
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 10 Register CONTROL 1 (address: 0x01H)
BIT
PARAMETER
DISP_CNTRL: select display signal
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
no display
D_WC (white clipped pixels)
D_AWBVAL (pixels according to AWBVAL)
D_MWG (measurement windows)
RGB_SEP_OFF: RGB reconstructor for raw data mode
enabled (normal RGB mode)
disabled (raw data mode)
reserved
0
1
X
X
VCF_GAIN: vertical contour filter gain
double
0
1
normal
WH_CL_MAP: white clip mapping on UV-grid
[0 0 1 0 0] spreading filter
[0 1 1 1 0] spreading filter
[1 1 1 1 1] spreading filter
0
0
X
0
1
X
Table 11 Register GAMMA_KNEE (address: 0x17H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
control scaler (5/8 gain)
disabled (transparent mode)
enabled (normal operation)
control knee
0
1
0
1
disabled
enabled
X
X
X
X
X
X
gamma balance [0 to 63]/64
Table 12 Register VC_CNTRL (address: 0x18H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
control vertical contour horizontal low pass filter
disabled
0
1
enabled
X
X
X
vertical contour COMB filter gain [0 to 7]/8
vertical contour gain [0 to 15]/16
X
X
X
X
2001 May 04
26
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 13 Register DMWSEL (address: 0x27H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
undefined
display measurement window #A for line #3
0
1
disabled
enabled
display measurement window #B for line #2
0
1
disabled
enabled
display measurement window #A for line #2
0
1
disabled
enabled
X
undefined
display measurement window #A for line #1
0
1
disabled
enabled
display measurement window #B for line #0
0
1
disabled
enabled
display measurement window #A for line #0
0
1
disabled
enabled
Table 14 Register DISPLEV (address: 0x28H)
BIT
PARAMETER
7
X
X
6
X
X
5
X
X
4
X
X
3
2
1
0
X
X
X
X
set defect pixel display level in defect pixel display mode [4 × [0 to 255]]
set Y (luminance) display level to other display modes [16 × [0 to 15]]
set U display level to other display modes [64 × [−2 to 1]]
X
X
X
X
set V display level to other display modes [64 × [−2 to 1]]
Table 15 Register NLINE_PRESET_MSB (address: 0x2DH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
bits 8 and 9 for PIXCNT_PRESET (by default = 0)
bit 8 for LINECNT_PRESET (by default = 0; note 1)
number of lines in a frame [480 + [0 to 31]] (by default = 6)
X
X
X
X
X
X
Note
1. Internal LINECNT range is [1 to 511]; no line zero.
2001 May 04
27
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 16 Register VHOUT_MSB_1 (address: 0x3BH)
BIT
PARAMETER
bits 8 and 9 for VOUT_HNE; note 1
7
6
5
4
3
2
1
0
X
X
X
X
bits 8 and 9 for VOUT_HPE; note 1
bits 8 and 9 for HOUT_NE
X
X
X
X
bits 8 and 9 for HOUT_PE
Note
1. Internal LINECNT range is [1 to 511]; no line zero.
Table 17 Register VHOUT_MSB_2 (address: 0x3CH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
reserved
X
select HOUT polarity
X
bit 8 for HOUTWIN_VNE; note 1
bit 8 for HOUTWIN_VPE; note 1
bit 8 for VOUT_VNE; note 1
bit 8 for VOUT_VPE; note 1
X
X
X
Note
1. Internal LINECNT range is [1 to 511]; no line zero.
Table 18 Register XSEL (address: 0x3FH)
BIT
PARAMETER
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
reserved
X
X
X
X
X
mode control for pixel extender
Table 19 Register TR_HT_CONTROL (address: 0x5CH
BIT
7
6
5
4
3
2
1
0
X
undefined
HEAD_ENA: control header transfer
disabled
0
1
enabled
X
X
X
HEAD_LEN: header length
TRAIL_ENA: control trailer transfer
disabled
0
1
enabled
X
X
TRAIL_LEN: trailer length
2001 May 04
28
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 20 Register PPG_CONTROL_0 (address: 0x60H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
undefined
SHUTTER_UPDATE_BUFFER: control shutter speed
immediate (by default)
0
1
buffered during vertical blanking
select PPG power mode
0
1
operational (by default)
resume
select PPG timing mode (VGA sensor)
frame rate = 30 fps (LLC = 24.0 MHz)
frame rate = 24 fps (LLC = 19.2 MHz)
frame rate = 20 fps (LLC = 16.0 MHz)
frame rate = 15 fps (LLC = 12.0 MHz)
frame rate = 10 fps (LLC = 8.0 MHz)
frame rate = 5 fps (LLC = 4.0 MHz)
undefined
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
2001 May 04
29
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 21 Register PPG_CONTROL_1 (address: 0x61H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
reserved
select frequency for compression clock CLK_C
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
off
2.0 MHz
2.4 MHz
4.0 MHz
4.8 MHz
6.0 MHz
8.0 MHz
9.6 MHz
12 MHz (by default)
16 MHz
19.2 MHz
24 MHz
reserved
select VGA sensor type
reserved
0
1
1
X
0
1
VGA type 1 (Sharp LZ24BP; Sony ICX098AK)
VGA type 2 (Panasonic MN37771PT)
reserved
X
2001 May 04
30
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 22 Register PPG_H_CTRL (address: 0x62H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
reserved
set RG pulse width
nominal value
0
1
RG_SHORT: half of nominal value
FH2_CTRL; note 1
0
0
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
blanked to HIGH; starts LOW
blanked to LOW; starts HIGH
blanked to LOW; starts LOW
blanked to HIGH; starts HIGH
no horizontal blanking; pulse inverted
no horizontal blanking
FH1_CTRL; note 1
0
0
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
blanked to LOW; starts HIGH
blanked to HIGH; starts LOW
blanked to HIGH; starts HIGH
blanked to LOW; starts LOW
no horizontal blanking; pulse inverted
no horizontal blanking
Note
1. If bits [5 to 3] equal bits [2 to 0] then FH2 is the inverse of FH1.
2001 May 04
31
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 23 Register PPG_V_INV (address: 0x63H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
FV4_INV
0
1
negative pulses
positive pulses
FV3_INV
0
1
negative pulses
positive pulses
FV2_INV
0
1
positive pulses
negative pulses
FV1_INV
0
1
positive pulses
negative pulses
ROG1_INV; note 1
negative pulses
positive pulses
ROG2_INV; note 1
negative pulses
positive pulses
reserved
0
1
0
1
X
X
Note
1. ROG1_INV and ROG2_INV are related to ROG_SEL (see Table 41; PIN_CONFIG_0[0]). If ROG_SEL = 0, then
ROG2_INV is activated (with Sony or Sharp CCD applications) and ROG1_INV is disabled. If ROG_SEL = 1, then
ROG1_INV is activated (with Panasonic CCD applications) and ROG2_INV is disabled.
2001 May 04
32
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 24 Register PPG_H_INV (address: 0x64H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
CLK2_INV
0
1
nominal pulses
inverted pulses
CLK1_INV
0
1
nominal pulses
inverted pulses
FS_INV
0
1
negative pulses
positive pulses
FCDS_INV
0
1
negative pulses
positive pulses
RG_INV
0
1
negative pulses
positive pulses
reserved
X
FH2_INV
0
1
positive pulses
negative pulses
FH1_INV
0
1
positive pulses
negative pulses
2001 May 04
33
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 25 Register PPG_MISC_INV (address: 0x65H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
reserved
SELECT_FV3
FV3 equals FV2
0
1
FV3 equals FV4 (with VGA type 1 sensors)
reserved
X
CRST_INV
0
1
negative pulses
positive pulses
BCP_INV
0
1
positive pulses
negative pulses
DCP_INV
0
1
positive pulses
negative pulses
H_INV
0
1
positive pulses
negative pulses
V_INV
0
1
positive pulses
negative pulses
Table 26 Register PPG_SHUTTERSPEED_V_LSB (address: 0x66H)
BIT
PARAMETER
8 LSBs of line number (9 bits) on which shutter speed is updated
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
Table 27 Register PPG_SHUTTERSPEED_H_LSB (address: 0x67H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) on which shutter speed is updated
2001 May 04
34
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 28 Register PPG_SHUTTERSPEED_MSB (address: 0x68H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
reserved
SENSOR_TYPE
Sharp
0
1
Sony
X
X
2 MSBs of pixel number (10 bits)
MSB of line number (9 bits)
X
Table 29 Register PPG_BCP_START_LSB (address: 0x69H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where BCP starts
Table 30 Register PPG_BCP_STOP_LSB (address: 0x6AH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where BCP stops
Table 31 Register PPG_DCP_START_LSB (address: 0x6BH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where DCP starts
Table 32 Register PPG_DCP_STOP_LSB (address: 0x6CH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where DCP stops
Table 33 Register PPG_BCP_DCP_MSB (address: 0x6DH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
2 MSBs of PPG_DCP_STOP
2 MSBs of PPG_DCP_START
2 MSBs of PPG_BCP_STOP
2 MSBs of PPG_BCP_START
X
X
X
X
X
X
2001 May 04
35
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 34 Register PPG_ROG1_START_LSB (address: 0x6EH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where ROG1 starts
Table 35 Register PPG_ROG1_STOP_LSB (address: 0x6FH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where ROG1 stops
Table 36 Register PPG_ROG2_START_LSB (address: 0x70H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where ROG2 starts
Table 37 Register PPG_ROG2_STOP_LSB (address: 0x71H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
8 LSBs of pixel number (10 bits) where ROG2 stops
Table 38 Register PPG_ROG1_2_MSB (address: 0x72H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
2 MSBs of PPG_ROG2_STOP
2 MSBs of PPG_ROG2_START
2 MSBs of PPG_ROG1_STOP
2 MSBs of PPG_ROG1_START
X
X
X
X
X
X
2001 May 04
36
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 39 Register VFC_CONTROL_0 (address: 0x73H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
RESET_VP_C: reset compression module of video processing
RESET_VP_VF: reset video formatter of video processing
X
SCALE_DATA: limits the number of bits of the video formatter output
0
0
1
1
0
1
0
1
8 bits
7 bits
6 bits
undefined
PREFILTER_SEL_UV: select horizontal UV downscaling prefilter
no prefilter (bypass)
0
0
1
1
0
1
0
1
prefilter for downscaling to SIF with 3 taps
prefilter for downscaling to QSIF with 5 taps
undefined
PREFILTER_SEL_Y: select horizontal Y downscaling prefilter
no prefilter (bypass)
0
0
1
1
0
1
0
1
prefilter for downscaling to SIF with 3 taps
prefilter for downscaling to QSIF with 5 taps
undefined
2001 May 04
37
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 40 Register VFC_CONTROL_1 (address: 0x74H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
Q_TABLE_SELECT: select quantization table for the compression engine
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
compression ratio = 2 (raw mode table) (by default)
compression ratio = 3
compression ratio = 4
compression ratio = 5
compression ratio = 6; with one bit shift
compression ratio = 7; with one bit shift
compression ratio = 7.5; with one bit shift
compression ratio = 8; with one bit shift
LDC: length of DC coefficient used in the compression engine
6 bits
0
0
1
1
0
1
0
1
7 bits
8 bits
undefined
VOF: select video output format
SIF compressed (by default)
SIF uncompressed
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
QSIF compressed
QSIF uncompressed
VGA compressed
VGA raw compressed
undefined
undefined
2001 May 04
38
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 41 Register PIN_CONFIG_0 (address: 0x7EH)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
reserved
P4_SEL: when enabled; pins are configured as general purpose outputs; otherwise
they are connected to FV1; FV2 and FV3
0
1
disabled
enabled (by default)
ROG_SEL: select ROG signal according to CCD type
PPG output ROG1 (Sony and Sharp CCD application) (by default)
PPG output ROG2 (Panasonic CCD application)
0
1
Table 42 Register PIN_CONFIG_1 (address: 0x7FH)
BIT
PARAMETER
PR_DISABLE: control remote wake-up 2
7
6
5
4
3
2
1
0
0
1
enabled
disabled (by default)
SR_DISABLE: control remote wake-up 1
enabled
0
1
disabled (by default)
SPIF_SEL: select interface between sensor and preprocessor
use serial interface (by default)
0
1
use port P4[2 to 0]
ASCLK_SEL: select ASCLK clock
ASCLK = single pixel clock (by default)
ASCLK = double pixel clock
0
1
VSP_VH_SEL: select connection type of VSP pins V and H
V = external V pulse (input); H = PPG_HD (output); VSP_VIN = PPG_VD
0
0
0
1
V = external V pulse (input); H = VSP_HOUT (output);
VSP_VIN = external V pulse
1
1
0
1
V = PPG_VD (output); H = PPG_HD (output); VSP_VIN = PPG_VD
V= VSP_VOUT (output); H = VSP_HOUT (output); VSP_VIN = 0
PCLK_INV: control pixel clock
0
1
normal (by default)
inverted
VSP_CLK_SEL: select VSP clock
VSP_CLK = CLK1 from PPG (by default)
VSP_CLK = PCLK
0
1
2001 May 04
39
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Audio and power-management registers
A first MOVX@DPTR instruction enables to select the module (via DPH) and send the command. A second one
communicates the data (read or write).
Table 43 Register list
ADDRESS
NAME
FUNCTION
FORMAT
Write registers
0
1
2
3
4
5
0x00H AUDIO_CLOCKS
0x01H RSTGEN
audio clocks control
reset generator control
analog power control
see Table 44
see Table 45
see Table 46
byte
0x02H ANALOG_POWER
0x03H POWERMGT_N1
0x04H POWERMGT_N2
0x05H AUDIO
timer N1 (by default = 24)
timer N2 (by default = 57)
audio properties control
byte
see Table 47
Read register
0x06H POWERMGT_STATUS power management status bits (read register)
6
see Table 48
Table 44 Register AUDIO_CLOCKS (address: 0x00H)
BIT
PARAMETER
SET_DIVIDE: set clock dividers for ADC
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
divide by 1 (by default)
divide by 2
divide by 4
divide by 8
X
reserved
DIS_CLK_AD: disable 48 MHz clock (ADC)
enabled (by default)
disabled
0
1
X
reserved
FCODE: set the PLL frequency
256 × 44.1 KHz (by default)
256 × 32 KHz
0
0
1
1
0
1
0
1
256 × 48 KHz
256 × 44.1 KHz
X
reserved
2001 May 04
40
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 45 Register RSTGEN (address: 0x01H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
UPC_RST_AUD26: reset generator for USB (aud26) module
0
1
controlled by the power management (by default)
forced
X
reserved
UPC_RST_ADIF: reset generator for audio module
0
1
controlled by the power management (by default)
forced
X
X
X
X
X
reserved
Table 46 Register ANALOG_POWER (address: 0x02H)
BIT
PARAMETER
UPC_OSC_OFF: set power safe mode
7
6
5
4
3
2
1
0
0
1
disabled (by default)
enabled
X
reserved
UPC_PLL_OFF: control PLL power
0
1
enabled (by default)
disabled
X
reserved
UPC_ADL_OFF: control ADC power (left channel)
0
1
enabled (by default)
disabled
X
X
X
reserved
2001 May 04
41
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 47 Register AUDIO (address: 0x05H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
HP_EN: set high pass filter
disabled
0
1
enabled (by default)
reserved
X
MUTE_ON: set audio mute
mute is off (by default)
mute is on
0
1
X
reserved
gain control; 0 to 30 dB in steps of 2 dB
0
0
0
0
0
0
0
1
0 dB (by default)
2 dB
....
1
1
1
1
1
1
0
1
28 dB
30 dB
Table 48 Register POWERMGT_STATUS (address: 0x06H)
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
STATUS_POWERUPBIT: set to 1 after a Power-on reset (by default = 1)
STATUS_BUSRESETBIT: set to 1 after a bus reset (by default = 0)
STATUS_RESUMEBIT: set to 1 after a resume (by default = 0)
STATUS_RW_BIT: set to 1 after remote wake-up is triggered (by default = 0)
reserved
X
X
X
X
X
X
X
2001 May 04
42
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
USB registers
A first MOVX@DPTR instruction enables module selection (via DPH) and command transmission. A second MOVX
communicates the data (read or write).
Table 49 Register list
ADDRESS
NAME
FUNCTION
FORMAT
Write registers
208 0xD0H SET_ADDRESS
216 0xD8H SET_EP_ENABLE
243 0xF3H GETSET_MODE
set address
set EP enable
set mode
see Table 50
see Table 51
see Table 52
Read registers
0
1
2
3
4
5
0x00H SELECT_EP0_out
0x01H SELECT_EP0_in
0x02H SELECT_EP1_OUT
0x03H SELECT_EP1_IN
0x04H SELECT_EP2
select EP 0 out
select EP 0 in
select EP 1 out
select EP 1 in
select EP 2
see Table 53
see Table 53
see Table 53
see Table 53
see Table 53
see Table 53
byte
0x05H SELECT_EP3
select EP 3
242 0xF2H SET_BUFFER_FE
244 0xF4H GET_INTERRUPT
245 0xF5H GET_FRAMENUMBER
250 0xFAH VALIDATE_BUFFER
253 0xFDH GET_CHIPID
clear selected EP buffer
read interrupt register
read current frame number
validate selected EP
read chip identifier
see Table 54
note 1
byte
note 2
Read/write registers
64 0x40H SELECT_EP0_OUT_STATUS select EP; clear interrupt and get information of EP 0
(out)
byte
65 0x41H SELECT_EP0_IN_STATUS
select EP; clear interrupt and get information of EP 0 (in) byte
66 0x42H SELECT_EP1_OUT_STATUS select EP; clear interrupt and get information of EP 1
(out)
byte
67 0x43H SELECT_EP1_IN_STATUS
68 0x44H SELECT_EP2_STATUS
69 0x45H SELECT_EP3_STATUS
70 0x46H SELECT_EP4_STATUS
71 0x47H SELECT_EP5_STATUS
240 0xF0H RW_DATA
select EP; clear interrupt and get information of EP 1 (in) byte
select EP; clear interrupt and get information of EP 2
select EP; clear interrupt and get information of EP 3
clear interrupt and get information of EP 4
get information of EP 5
byte
byte
byte
byte
note 3
byte
read selected EP buffer
254 0xFEH GETSET_DEVICE_STATUS
set device status
Notes
1. The GET_FRAMENUMBER command returns the frame number of the last received Start Of Frame (SOF). The
frame number is 11 bits wide; therefore two consecutive reads are needed to get the complete value. The first byte
provides the LSBs; the second byte (bits 0 to 2) provides the 3 MSBs. Note: it is possible to read the first byte only.
2. The GET_CHIPID command is followed by two reads since the chip identification is 16 bits wide (see Tables 55
and 56).
3. The RW_DATA command can be followed by up to ‘n + 2’ bytes read or write (n is the number of data bytes in the
selected EP buffer). With read, it returns the contents of the selected EP data buffer. With write, it loads the data
buffer of the selected EP.
2001 May 04
43
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 50 Register SET_ADDRESS (address: 0xD0H)
Detailed description of the write (1 byte) following command 0xD0H
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
ENABLE_ADD: enable the function (by default = 0)
X
X
X
X
X
X
X
DEVICE_address: set the USB assigned address (by default = 0)
Table 51 Register SET_EP_ENABLE (address: 0xD8H)
Detailed description of the write (1 byte) following command 0xD8H
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
reserved
ENABLE_EP: enable end-point
0
Non-control end-points are disabled (by default)
Non-control end-points are enabled
10
Table 52 Register GETSET_MODE (address: 0xF3H)
Detailed description of the write (one byte) following command 0xF3H; notes 1, 2 and 3
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
reserved
FIFO_ACTIVE: set the video FIFO status
0
1
FIFO is inactive; only zero-length packet are sent upstream
functional mode (by default)
ALWAYS_PLLCLOCK: control internal clock signals
clocks and PLL are stopped whenever not needed (e.g. suspend mode)
clocks and PLL are always running even in suspend mode (by default)
INTERRUPT_ONNAK: control transaction reporting
only successful transactions are reported
0
1
0
1
NAK is reported and generates an interrupt (by default)
Notes
1. GETSET_MODE command can write from 1 to 4 consecutive bytes. The detailed description above concerns byte 0.
2. GETSET_MODE bytes 1 and 2 are used to set the size of the isochronous video packets. Byte 1 corresponds to the
LSB to define the packet size. Bits 0 and 1 of byte 2 set the 2 MSBs. By default, the two bytes are forced to 0.
3. GETSET_MODE byte 3 sets the FIFO offset.
2001 May 04
44
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 53 Register SELECT_EP0_OUT (address: 0x00H)
Detailed description of the optional read (1 byte) following command 0x00H; note 1
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
reserved
SENT_NAK:
0
1
a NAK is not sent (by default)
a NAK is sent by the device
PACKET_OVERWRITTEN:
not overwritten (by default)
0
1
the previously received packet was overwritten by a setup packet
SETUP_PACKET: give the status of the last received packet
not a setup packet (by default)
0
1
last received packet for the selected EP was a setup packet
STALL_PACKET: give the status of the selected EP
not stall (by default)
0
1
stall
BUFFER_STATUS: give the EP buffer status; note 2; this bit is cleared by
executing the SET_BUFFER_FE command
0
1
buffer not full (by default)
buffer of the selected EP is full
Notes
1. The SELECT_EPX_XX command selects the corresponding EP buffer. It can be followed optionally by a data read,
which provides the EP status to the microcontroller (see the detailed description above). Whatever the EP (from 0
to 3) or its direction, the sequence is the same. Note that isochronous EP cannot be selected in this way.
2. BUFFER_STATUS: in case of an IN endpoint; this bit is set by the VALIDATE_BUFFER command.
Table 54 Register GET_INTERRUPT (address: 0xF4H)
Detailed description of the read (1 byte) following command 0xF4H
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
DEVICE_EVENT: an event occurred in the device
X
PHYSICAL_EP6: interrupt signal comes from (logic) EP4
PHYSICAL_EP5: interrupt signal comes from (logic) EP3
PHYSICAL_EP4: interrupt signal comes from (logic) EP2
PHYSICAL_EP3: interrupt signal comes from (logic) EP1 in
PHYSICAL_EP2: interrupt signal comes from (logic) EP1 out
PHYSICAL_EP1: interrupt signal comes from (logic) EP0 in
PHYSICAL_EP0: interrupt signal comes from (logic) EP0 out
X
X
X
X
X
X
2001 May 04
45
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 55 Register GET_CHIP_ID BYTE 0 (address: 0xFDH)
Detailed description of the read (byte 0) following command 0xFDH
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
PRODUCT_ID: 5 LSBs of the product identification (by default = 10011)
REVISION_NB: revision number (by default = 001)
X
X
X
Table 56 Register GET_CHIP_ID BYTE 1 (address: 0xFDH)
Detailed description of the read (byte 1) following command 0xFDH
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
CUSTOMER_ID: customer identification (by default = 110011)
X
X
PRODUCT_ID: 2 MSBs of the product identification (by default = 00)
2001 May 04
46
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
supply voltage
+4.0
V
Vn
voltage on
pins GND and AGND
all other pins
−0.5
−0.5
−55
0
+4.0
V
VDD + 0.5
V
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
+150
70
°C
°C
°C
−40
+125
Note
1. Stress beyond these levels may cause permanent damage to the device.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to ambient in free air
53
K/W
2001 May 04
47
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
CHARACTERISTICS
VDD = VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C; unless otherwise specified; note 1.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
3.0
3.3
3.6
V
V
V
VDDD
VDDA
IDDD(tot)
supply voltage for digital core
analog supply voltage
3.0
3.0
−
3.3
3.6
3.3
65(2)
3.6
85(3)
total digital supply current
VDD = VDDD = 3.3 V;
mA
Tamb = 25 °C
IDDA(tot)
total analog supply current
VDDA = 3.3 V; Tamb = 25 °C −
VDDA = 3.3 V; Tamb = 25 °C −
16
−
mA
IDDQ(susp) total suspend current
−
400(3)
µA
Digital data and control inputs
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.8
V
V
2
−
Digital data and control outputs
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
0
−
−
0.1VDD
VDD
V
V
0.9VDD
LDO supply filter
Vref
VO
IO
reference voltage
at 0.5VDDA
−
1.50
3.0
5
−
V
output voltage on pin LDOUT
output current on pin LDOUT
VDDA = 3.0 V
−
−
−
V
10
mA
Microphone supply
IDDA
Vref
VO
IO
supply current
reference voltage
−
−
−
−
0.85
1.50
2.7
−
1.2
−
mA
V
at 0.5VDDA
output voltage on pin MICSUPPLY VDDA = 3.0 V
output current on pin MICSUPPLY
−
V
2.0
mA
Audio low noise amplifier
TRANSFER FUNCTION
Ri
input resistance
3.5
−
5.0
0.85
30
−
kΩ
mA
dB
IDDA
A
supply current
1.2
31
amplification
29
−
THD
Vo(rms)
VOO
total harmonic distortion
output voltage (RMS value)
output offset voltage
note 4
−77
−
−70
800
1.0
dB
−
mV
mV
−
0.0
BIASING
Iref
reference current
−
10
−
µA
2001 May 04
48
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Programmable audio gain amplifier
TRANSFER FUNCTION
Ri
input resistance
supply current
7.0
10.5
25
kΩ
IDDA
VOO
−
0.45
1.0
14
0.6
2.0
30
mA
mV
mV
dB
output offset voltage
A = 0 dB
−
A = 30 dB
−
A
amplification
0.2
−
−
32
THD
total harmonic distortion
A = 0 dB; note 4
A = 30 dB; note 4
−89
−66
−85
−62
dB
−
dB
BIASING
Iref
reference current
−
10
−
µA
Audio phase-locked loop
fi(clk)
clock input frequency
−
−
−
−
−
−
48
−
−
−
−
−
−
MHz
MHz
MHz
MHz
kHz
fo(clk)
clock output frequency
note 5
8.1920
11.290
12.288
2.3
B
bandwidth
ζ
damping coefficient
0.98
Audio ADC (∑∆ converter)
INPUTS
fi
input signal frequency
input voltage (RMS value)
1
−
20
kHz
mV
Vi(rms)
−
800
−
TRANSFER FUNCTION
N
order of the ∑∆
−
−
−
−
−
−
−
3
−
−
−
−
Nbit
Nbit(eq)
DRi
fclk
number of output bits
1
equivalent output resolution (bit)
dynamic range at input
clock frequency
16
96.6
−
note 6
dB
5.6448 MHz
δ
clock frequency duty factor
total harmonic distortion
50
−73
−
%
THD
−60
dB
ATX transceiver full speed mode: pins ATXDP and ATXDN
DRIVER CHARACTERISTICS
tt(rise)
tt(fall)
tt(match)
Vcr
rise transition time
CL = 50 pF
CL = 50 pF
note 7
4
−
−
−
−
−
20
ns
ns
%
V
fall transition time
4
20
transition time matching
output signal crossover voltage
driver output impedance
90
1.3
30
110
2.0
42
Zo
steady state drive
Ω
2001 May 04
49
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RECEIVER CHARACTERISTICS
fi(D)
data input frequency rate
frame interval
−
−
12.00
1.000
−
−
Mbits/s
ms
tframe
Notes
1. Including the current through the external 1.5 kΩ resistor connected to ATXDP.
2. Typical: VGA at 15 fps.
3. Maximum: SIF at 30 fps.
4. The distortion is measured at HIGH level; 1 kHz and Vo = 800 mV (RMS).
5. Frequencies depend on PLL settings; see also Table 6.
input voltage
6. Defined here as: 20 × log
------------------------------------------------------------------------------
equivalent input noise voltage
t
7. Transition time matching: t t(match)
=
t(rise) × 100%
-------------
tf(fall)
2001 May 04
50
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
TIMING
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C.
SYMBOL
PARAMETER
CONDITIONS MIN.
TYP. MAX. UNIT
Data input related to ASCLK for CCD sensors; (see Fig.10)
PINS PXL0 TO PXL7
tsu(i)(D)
th(i)(D)
data input set-up time
data input hold time
1.5
1.5
−
−
−
−
ns
ns
PPG high-speed pulses for SONY ICX098AK VGA CCD sensor at 30 fps; (see Fig.11)
td1
td2
td3
td4
td5
td6
delay between falling edge FH2 and rising edge FH1
delay between rising edge FH2 and falling edge FH1
delay between falling edge FH1 and rising edge FCDS
delay between rising edge FH1 and rising edge FS
delay between rising edge FH1 and falling edge RG
−4
0
−2
0
ns
ns
ns
ns
ns
ns
1.5
12
3
10.5
10
0
13.5
15
4
12.5
2
delay between falling edge ASCLK and rising
edge FH1
−3
−1.5
0
td7
delay between rising edge ASCLK and falling
edge FH1
2
6
10
ns
tWH(FH1)
tWL(FH2)
FH1 pulse width HIGH
FH2 pulse width LOW
38
41
6
39.5
42.5
7
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
tWL(FCDS) FCDS pulse width LOW
tWL(FS)
tWL(RG)
FS pulse width LOW
RG pulse width LOW
18
20
40
20.5
21.5
43.5
tWL(ASCLK) ASCLK pulse width LOW
tr rise time
pulse FH1
note 1
−
−
−
−
−
4
4
4
4
4
−
−
−
−
−
ns
ns
ns
ns
ns
pulse FH2
pulse RG
pulse FCDS
pulse FS
tf
fall time
note 1
pulse FH1
pulse FH2
pulse RG
pulse FCDS
pulse FS
−
−
−
−
−
4
4
4
4
4
−
−
−
−
−
ns
ns
ns
ns
ns
Note
1. CL = 11 pF; Tamb = 25 °C.
2001 May 04
51
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
ASCLK
t
su(i)D
t
h(i)D
PXL[9:0]
FCE746
Fig.10 Data input timing.
t
WH(FH1)
FH1
50%
50%
50%
t
t
d1
d2
50%
FH2
50%
t
WL(FH2)
50%
50%
FCDS
t
t
d3
d4
t
t
WL(FCDS)
WL(FS)
50%
50%
FS
RG
t
WL(RG)
t
d5
50%
d6
50%
t
t
d7
ASCLK
50%
50%
t
FCE745
WL(ASCLK)
Fig.11 PPG high-speed pulses for Sony ICX098AK VGA CCD sensor.
52
2001 May 04
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
APPLICATION INFORMATION
In the event that the internal ROM is used (pin EA set HIGH), it is strongly recommended to connect pins P0.0 to P0.7
to ground to avoid any leakage that would increase the current in suspend mode.
EPROM
EEPROM
(optional)
12 MHz
PCLK
XSEL
ASCLK
PXL9 to PXL0
SDATA
LED
SNAPRES
PRIVRES
PORE
CCD
SENSOR
TDA8787A
SCLK
PSEL
SAA8116
DELAYATT
STROBE
ATXDP
ATXDN
USB
5V
BUS
V-DRIVER
FS, FCDS, DCP, BCP
FH1, FH2, RG, ROG
LDO
LDO
FV1, FV2, FV3, FV4, CRST
SMP
FCE675
3.3 V
3.3 V
Fig.12 CCD sensor application.
2001 May 04
53
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
EPROM
EEPROM
(optional)
12 MHz
XSEL
LED
SNAPRES
PRIVRES
PORE
V
CMOS
SENSOR
ASCLK
PCLK
PSEL
SAA8116
DELAYATT
PXL7 to PXL0
ATXDP
ATXDN
USB
5V
BUS
LDO
LDO
FCE676
3.3 V
3.3 V
Fig.13 CMOS sensor application.
2001 May 04
54
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
PACKAGE OUTLINES
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v M
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.15 1.45
0.05 1.35
0.27 0.20 14.1 14.1
0.17 0.09 13.9 13.9
16.25 16.25
15.75 15.75
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.08 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
00-01-19
00-02-01
SOT407-1
136E20
MS-026
2001 May 04
55
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
TFBGA112: plastic thin fine-pitch ball grid array package; 112 balls; body 7 x 7 x 0.8 mm
SOT630-1
D
B
A
ball A1
index area
A
2
A
E
A
1
detail X
A
e
v M
B
1
y
v
A
e
b
w M
v M
A
M
L
K
J
e
H
G
F
e
1
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
1
y
y
1
D
E
v
w
1
2
max.
0.28 0.84 0.37
0.16 0.76 0.27
7.1
6.9
7.1
6.9
mm 1.12
0.12
0.1
0.5
5.5
0.1
0.15
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
EIAJ
00-07-20
SOT630-1
MO-195
2001 May 04
56
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2001 May 04
57
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not suitable(2)
suitable
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(3)(4) suitable
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
DEFINITIONS
STATUS(2)
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Product data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 May 04
58
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
DEFINITIONS
DISCLAIMERS
Life support applications
Short-form specification
The data in a short-form
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 May 04
59
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4728 6600, Fax. +33 1 4728 6638
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,
Tel: +36 1 382 1700, Fax: +36 1 382 1800
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Tel. +39 039 203 6838, Fax +39 039 203 6800
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
Middle East: see Italy
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
72
SCA
© Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/03/pp60
Date of release: 2001 May 04
Document order number: 9397 750 08198
相关型号：
©2020 ICPDF网 联系我们和版权申明