TDA5153BG [NXP]
Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads; 对于硬盘驱动器HDD前置放大器MR-读/写感应头
| 型号： | TDA5153BG |
| 厂家： | 
NXP |
| 描述： | Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| 文件： | 总28页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA5153
Pre-amplifier for Hard Disk Drive
(HDD) with MR-read/inductive write
heads
1997 Jul 02
Preliminary specification
File under Integrated Circuits, IC11
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
CONTENTS
1
2
3
4
5
6
7
8
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
8.1
Read mode
8.2
Write mode
8.3
Sleep mode
8.4
8.5
Standby mode
Active mode
8.6
8.7
Bi-directional serial interface
Addressing
8.8
8.9
Programming data
Reading data
Operation of the serial interface
Configuration
Power control
Head select
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Servo write
Test
8.10.5.1 MR head test
8.10.5.2 Temperature monitor
8.10.5.3 Thermal asperity detector
8.10.6
8.10.7
8.10.8
8.10.9
8.10.10
8.11
Write amplifier programmable capacitors
High frequency gain attenuator pole register
High frequency gain boost register
Settle pulse
Address registers
Head unsafe
8.12
HUS survey
9
LIMITING VALUES
HANDLING
10
11
12
THERMAL RESISTANCE
RECOMMENDED OPERATION
CONDITIONS
13
14
15
16
17
CHARACTERISTICS
PACKAGE OUTLINE
SOLDERING
DEFINITION
LIFE SUPPORT APPLICATIONS
1997 Jul 02
2
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
1
FEATURES
3
GENERAL DESCRIPTION
• Designed for 4 (TDA5153BG) or 6 dual-stripe
MR-read/inductive write heads
The 5.0 V pre-amplifier for HDD described here is
designed for five terminals, dual stripe Magneto-Resistive
(MR)-read/inductive-write heads. The disks of the disk
drive are connected to ground. To avoid voltage
break-through between the heads and the disk, the MR
elements of the heads are also connected to ground. The
symmetry of the dual-stripe head-amplifier combination
automatically distinguishes between the differential
signals such as signals and the common-mode effects like
interference. The latter are rejected by the amplifier.
• Current bias-current sense architecture
• Single supply voltage (5.0 V ±10%); a separate write
drivers supply pin can be biased from VCC to 8 V +10%
• MR elements connected to ground (GND)
• Equal bias currents in the two MR stripes of each head
• On-chip AC couplings eliminate MR head DC offset
• 3-wire serial interface for programming
The IC incorporates read amplifiers, write amplifiers, serial
interface, digital-to-analog converters, reference and
control circuits which operate on a single supply voltage of
5 V ±10%. The output drivers have a separate supply
voltage pin which can be connected to a higher supply
voltage of up to 8 V +10%. The complementary output
stages of the write amplifier allow writing with near
rail-to-rail peak voltages across the inductive write head.
• Programmable high-frequency zero-pole gain boost
• Programmable write driver compensation capacitance
• Programmable MR bias currents and write currents
• 1-bit programmable read gain
• Sleep, standby, active and test modes available
• Measurement of head resistances in test mode
• In test mode, one MR bias current may be forced to a
minimum current
The read amplifier has a low input impedance. The DC
offset between the two stripes of the MR head is eliminated
using on-chip AC coupling. Fast settling features are used
to keep the transients short. As an option, the read
amplifier may be left biased during writing so as to reduce
the duration of these transients even more. Series
inductance in the leads between the amplifier and MR
heads influences the bandwidth which can be
compensated by using a programmable high-frequency
gain-boost (HF zero). HF noise and bandwidth can be
attenuated using a programmable high-frequency
gain-attenuator (HF pole).
• Short write current rise and fall times with near rail-to-rail
voltage swing
• Head unsafe pin for signalling of abnormal conditions
and behaviour
• Low supply voltage write-current inhibit (active or
inactive)
• Supports servo writing
• Provides temperature monitor
• Thermal asperity detection with programmable
On-chip digital-to-analog converters for MR bias currents
and write currents are programmed via a 3-wire serial
interface. Head selection, mode control, testing and servo
writing can also be programmed using the serial interface.
In sleep mode the CMOS serial interface is operational.
Figure 1 shows the block diagram of the device.
threshold level
• Requires only one external resistor.
2
APPLICATIONS
• Hard Disk Drive (HDD).
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
−
TDA5153X
−
naked die
TDA5153AG;
TDA5153BG
LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
1997 Jul 02
3
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
5
QUICK REFERENCE DATA
SYMBOL
VCC
VCC(WD)
F
PARAMETER
CONDITIONS
MIN.
4.5
TYP.
5.0
MAX.
5.5
UNIT
supply voltage
V
write drivers supply voltage
noise figure
VCC
8.0
3.0
8.8
3.2
V
R
MR = 28 Ω; IMR = 10 mA;
−
dB
Tamb = 25 °C; f = 20 MHz
Vnir
input referred noise voltage; see RMR = 28 Ω; IMR = 10 mA;
−
0.9
1.0
nV/√Hz
note 3 in Chapter 13
Tamb = 25 °C; f = 20 MHz
Gv(dif)
differential voltage gain
from head inputs to RDx, RDy;
R
MR = 28 Ω; IMR = 10 mA
d4 = logic 0
−
−
−
160
226
220
−
−
−
d4 = logic 1
B−3 db
−3 dB frequency bandwidth
upper bandwidth without gain
boost (4 nH lead inductance)
MHz
CMRR
common mode rejection ratio;
IMR = 10 mA; f < 1 MHz
−
−
−
−
45
25
80
50
−
−
−
−
dB
dB
dB
dB
R
MR mismatch <5%
I
MR = 10 mA; f < 100 MHz
PSRR
tr, tf
power supply rejection ratio
(input referred);
RMR mismatch <5%
f < 1 MHz
f < 100 MHz
rise/fall times (10% to 90%)
Lh = 150 nH; IWR = 35 mA;
f = 20 MHz
V
V
CC(WD) = 8.0 V
CC(WD) = 6.5 V
−
−
−
−
−
1.8
2.1
20.5
51
ns
−
ns
IMR(PR)
programming MR bias current
Rext = 10 kΩ
Rext = 10 kΩ
5
mA
mA
IWR(PR)(b-p) programming write current
range (base-to-peak)
20
fSCLK
serial interface clock rate
−
−
25
MHz
1997 Jul 02
4
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
6
BLOCK DIAGRAM
V
V
CC(WD)
CC
(5 to 8 V)
48
11
TDA5153
2
WDlx
3
(2)
15 , 20, 26,
(3)
(2)
6
33, 39, 44
nWy
nWx
WDly
WRITE DRIVER
INPUT
FF
(1)
IWDlx
(2)
(3)
14 , 19, 25,
6
(1)
IWDly
(2)
32, 38, 43
1
HEAD UNSAFE
INDICATOR
HUS
(3)
6
LOW SUPPLY
VOLTAGE
INDICATOR
WRITE
CURRENT
SOURCE
12
R
ext
WRITE DRIVER
AND
READ PREAMP
VOLTAGE
REFERENCE
(3)
(6×)
+V
CC
TAS
DETECTOR
4
7
5
R/W
4
SERIAL
INTERFACE
SCLK
5
SEN
3
6
(3)
20 kΩ
6
head select
SDATA
R
MR
CURRENT
SOURCE
5
(2)
18 , 23, 29,
4
4
(3)
(3)
(3)
(2)
6
6
6
36, 42, 47
nRy
(2)
17 , 22, 28,
9
RDx
RDy
(2)
35, 41, 46
nGND
10
(2)
16 , 21, 27,
(2)
34, 40, 45
nRx
8, 13
GND n
MGK422
Pin numbers correspond to TDA5153AG and TDA5153BG only. See Fig.3 and Chapter 7 for pinning of TDA5153X.
(1) Only available on naked die.
(2) Absent on TDA5153BG (4 channel version).
(3) 4 on TDA5153BG.
Fig.1 Block diagram.
1997 Jul 02
5
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
7
PINNING
PIN
PAD
SYMBOL
DESCRIPTION
TDA5153AG TDA5153BG TDA5153X
HUS
WDIx
WDIy
IWDIx
IWDIy
R/W
SEN
SDATA
SCLK
GND1
RDx
RDy
GND3
VCC
1
2
1
2
1
2
head unsafe output
write data input (differential; voltage input)
write data input (differential; voltage input)
write data input (differential; current input)
write data input (differential; current input)
read/write (read = HIGH; write = LOW)
serial bus enable
3
3
3
−
−
4
−
−
5
4
4
6
5
5
7
6
6
8
serial bus data
7
7
9
serial bus clock
8
8
10
11
12
13
14
15
16
17
18
19
20
21
−
ground connection 1
9
9
read data output (differential x − y)
read data output (differential x − y)
ground connection 3
10
−
10
−
11
12
13
14
15
16
17
18
−
11
12
13
−
supply voltage
Rext
10 kΩ external resistor
GND2
0Wx
0Wy
0Rx
ground connection 2
inductive write head connection for head H0 (differential x − y)
inductive write head connection for head H0 (differential x − y)
MR-read head connection for head H0 (differential x − y)
ground connection for head H0
−
−
0GND
0Ry
−
−
MR-read head connection for head H0 (differential x − y)
not connected
n.c.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
n.c.
−
−
not connected
n.c.
−
−
not connected
n.c.
−
−
not connected
n.c.
−
−
not connected
1Wx
1Wy
1Rx
19
20
21
22
23
24
25
26
27
28
29
30
22
23
24
25
26
−
inductive write head connection for head H1 (differential x − y)
inductive write head connection for head H1 (differential x − y)
MR-read head connection for head H1 (differential x − y)
ground connection for head H1
1GND
1Ry
MR-read head connection for head H1 (differential x − y)
not connected
n.c.
2Wx
2Wy
2Rx
27
28
29
30
31
−
inductive write head connection for head H2 (differential x − y)
inductive write head connection for head H2 (differential x − y)
MR-read head connection for head H2 (differential x − y)
ground connection for head H2
2GND
2Ry
MR-read head connection for head H2 (differential x − y)
not connected
n.c.
1997 Jul 02
6
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
PIN
PAD
SYMBOL
DESCRIPTION
TDA5153AG TDA5153BG TDA5153X
n.c.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
−
31
32
33
34
35
36
37
38
39
40
41
42
−
−
not connected
3Wx
3Wy
3Rx
32
33
34
35
36
−
inductive write head connection for head H3 (differential x − y)
inductive write head connection for head H3 (differential x − y)
MR-read head connection for head H3 (differential x − y)
ground connection for head H3
3GND
3Ry
MR-read head connection for head H3 (differential x − y)
not connected
n.c.
4Wx
4Wy
4Rx
37
38
39
40
41
42
43
44
45
46
−
inductive write head connection for head H4 (differential x − y)
inductive write head connection for head H4 (differential x − y)
MR-read head connection for head H4 (differential x − y)
ground connection for head H4
4GND
4Ry
MR-read head connection for head H4 (differential x − y)
inductive write head connection for head H5 (differential x − y)
inductive write head connection for head H5 (differential x − y)
MR-read head connection for head H5 (differential x − y);
ground connection for head H5
5Wx
5Wy
5Rx
−
−
5GND
5Ry
−
−
MR-read head connection for head H5 (differential x − y)
not connected
n.c.
43
44
45
46
47
48
−
n.c.
−
−
not connected
n.c.
−
−
not connected
n.c.
−
−
not connected
n.c.
−
−
not connected
VCC(WD)
GND4
48
−
47
48
supply voltage for the write drivers
ground connection 4
1997 Jul 02
7
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
1
2
36 3Ry
35
HUS
WDIx
WDIy
R/W
3GND
34 3Rx
33
3
4
3Wy
32 3Wx
31
SEN
5
6
SDATA
SCLK
GND1
RDx
n.c.
TDA5153AG
7
30 n.c.
29 2Ry
28 2GND
27 2Rx
8
9
RDy
10
11
12
26
V
2Wy
CC
R
25 2Wx
ext
MGK424
1
2
3
4
5
6
7
8
9
36 3Ry
HUS
WDIx
WDIy
R/W
35
3GND
34 3Rx
33
3Wy
SEN
32 3Wx
31 n.c.
SDATA
SCLK
GND1
RDx
TDA5153BG
n.c.
30
29 2Ry
2GND
28
RDy
27 2Rx
10
26
V
2Wy
11
12
CC
R
25 2Wx
ext
MGK420
Fig.2 Pin configurations.
8
1997 Jul 02
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
GND4
HUS
48
1
3Ry
36
35
34
33
32
47 46 45 44 43 42 41 40 39 38 37
3GND
3Rx
WDIx
WDIy
IWDIx
IWDIy
R/W
2
3Wy
3Wx
3
4
5
6
SEN
7
TDA5153X
SDATA
SCLK
GND1
RDx
8
9
10
11
12
13
14
15
31
30
29
28
27
2Ry
RDy
2GND
2Rx
GND3
V
2Wy
2Wx
CC
16 17 18 19 20 21 22 23 24 25 26
R
ext
MGK421
Fig.3 TDA5153X pad configuration.
1997 Jul 02
9
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
read, sleep and standby modes. In write mode, a
8
FUNCTIONAL DESCRIPTION
Read mode
programmable current is forced through the selected two
terminals inductive write head. The push-pull output
drivers yield near rail-to-rail voltage swing for fast current
polarity switching.
8.1
The read mode disables the write circuitry to save power
while reading. The read circuitry is de-activated for write,
sleep and standby modes. The read circuitry may also be
biased during write mode to shorten transients.
The selected head is connected to a multiplexed low-noise
read amplifier. The read amplifier has low-impedance
inputs nRx and nRy (n is the number of the head) and
low-impedance outputs RDx and RDy. The signal polarity
is non-inverting from x and y inputs to x and y outputs.
The differential write data input WDIx − WDIy is PECL
(Positive Emitter Coupled Logic) compatible. The write
data flip-flop can either be used or passed-by. In the case
that the write data flip-flop is used, current polarity is
toggled at the falling edges of the Vdata = VWDIx − VWDIy
.
Switching to Write Mode initializes the data flip-flop so that
the write current flows in the write head from x to y. In the
case that the write data flip-flop is not used, the signal
polarity is non-inverting from x and y inputs to x and y
outputs.
Ambient magnetic fields at the MR elements result in a
relative change in MR resistance
∆RMR
---------------
RMR
The write current magnitude is controlled through on-chip
DACs. The write current is defined as follows:
This change produces a current variation
10 kΩ
Rext
IWR
=
(20 + 16 d4 + 8 d3 + 4 d2 + 2 d1 + d0)
---------------
∆RMR
∆ I MR = IMR
×
,
---------------
RMR
(in mA) where d4 to d0 are bits (either logic 0 or logic 1).
The adjustable range of the write current is 20 mA to
51 mA. At power-up, the default values
where IMR is the bias current in the MR element.
The current variation is amplified to form the read data
output signal voltage, which is available at RDx − RDy.
AC coupling between MR elements and amplifier stages
prevents the amplifier input stages from overload by DC
voltages across the MR elements. A fast settling
procedure shortens DC settling transients.
d4 = d3 = d2 = d1 = d0 = logic 0 are initialized,
corresponding to IWR = 20 mA. IWR is the current provided
by the write drivers: the current in the write coil and in the
damping resistor together. The static current in the write
coil is
IWR
,
----------------
An on-chip generated stable temperature reference
voltage (1.32 V), available at the Rext pin, is dropped
across an external resistor (10 kΩ) to form a global
reference current for the write and the MR bias currents.
The MR bias current DACs are programmed through the
serial interface according to the following formula
Rh
1 +
------
Rd
where Rh is the resistance of the coil including leads and
Rd is the damping resistor.
8.3
Sleep mode
10 kΩ
2 Rext
I MR
=
(10 + 16 d4 + 8 d3 + 4 d2 + 2 d1 + d0)
------------------
In sleep mode, the device is accessible via the serial
interface. All circuits are inactive, except the circuits of the
CMOS serial interface and the circuit which forces the data
registers to their default values at power-up and which
fixes the DC level of RDx − RDy (required when operating
with more than one amplifier). Typical static current
consumption is −30 µA. Dynamic current consumption
during operation of the serial interface in the sleep mode
and owing to external activity at the inputs to the serial
interface is not included. In all modes including the sleep
mode, data registers can be programmed. Sleep is the
default mode at power-up. Switching to other modes takes
less than 0.1 ms.
(in mA), where d4 to d0 are bits (either logic 0 or logic 1).
At power-up, all bits are set to logic 0, which results in a
default MR current of 5 mA. The adjustable range of the
MR currents is 5 mA to 20.5 mA. The MR bias currents are
equal for the two stripes of each head. The gain amplifier
is 1-bit programmable. The amplifier gain can be set to its
nominal value or to the nominal value +3 dB.
8.2
Write mode
To minimize power dissipation, the read circuitry may be
disabled in write mode. The write circuitry is disabled in
1997 Jul 02
10
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
8.4
Standby mode
8.7
Addressing
The circuit can be put in standby mode using the serial
interface. In standby mode, typical DC current
When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0, starting with a0, are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data.
SEN should go HIGH at least 5 ns before the first rising
edge of SCLK. Data should be valid at least 5 ns before
and after a rising edge of SCLK. The bits a7 to a4
constitute the register address.To validate the
consumption is 330 µA. Transients from standby mode to
active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switching times are
summarized in the switching characteristics.
communication with the preamplifier, bits a1, a2 and a3
have to be programmed as (1, 0, 0).
8.5
Active mode
Active mode is either read mode or write mode depending
on the R/W pin.
If bit a0 = logic 0, a programming sequence starts.
If bit a0 = logic 1, reading data from the pre-amplifier can
start.
8.6
Bi-directional serial interface
The serial interface is used for programming of the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/W) are CMOS inputs. The logic
input R/W has an internal 20 kΩ pull-up resistor and the
SEN logic input has an internal 20 kΩ pull-down resistor.
Thus, in case the SEN line is opened, no data will be
registered and in case the R/W line is opened, the device
will never be in write mode.
8.8
Programming data
If a0 = logic 0, the last eight bits d7 to d0 before SEN goes
LOW are shifted into an input register. Bits d6 and d7 are
don’t care. When SEN goes LOW, the communication
sequence is ended and the data in the input register is
copied in parallel to the data register that corresponds to
the decoded address a7 to a4. SEN should go LOW at
least 5 ns after the last rising edge of SCLK.
8.9
Reading data
SDATA: serial data; bi-directional data interface. In all
circumstances, the LSB is transmitted first.
Immediately after the IC detects that a0 = logic 1, data
from the data register (address a7 to a4) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored.
SCLK: serial clock; 25 MHz clock frequency.
SEN: serial enable; data transfer takes place when SEN is
HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.
Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.
1997 Jul 02
11
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
>5 ns
>5 ns
SEN
SCLK
SDATA
0
a1
a2
a3
a4
a5
a6
a7
d0
d1
d2
d3
data
d4
d5
d6
d7
address
MGK423
Fig.4 Timing diagram of the serial interface operation; writing sequence (a0 = 0).
SEN
SCLK
SDATA
1
a1 a2 a3 a4 a5 a6 a7
address
d0 d1 d2 d3 d4 d5
data
wait
cycles
MGK419
Fig.5 Timing diagram of the serial interface operation; reading sequence (a0 = 1).
12
1997 Jul 02
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
If d1 = d0 = logic 1, the circuit goes in active mode, (read
or write mode depending on the R/W input).
8.10 Operation of the serial interface
8.10.1 CONFIGURATION
d0
8.10.3 HEAD SELECT
By default (d0 = logic 0), write data passes from the
write data input via the data flip-flop to the write driver.
The write driver toggles the current in the head at the
falling edges of
d2, d1 and d0 are used to select head H0 to H5 for the
6 channel version and to select head H1 to H4 for the
4 channel version.
8.10.4 SERVO WRITE
V
WDIx – VWDIy
=
-------------------------------------
Vdata
2
The circuit is prepared for servo writing. However, the chip
will not be guaranteed.
When d0 = logic 1, the flip-flop is not used. The signal
polarity is non-inverting from WDIx and WDIy to Wx and
Wy.
8.10.5 TEST
d1
d2 = d1 = d0 = logic 0. The circuit is not in test mode. This
is the default situation.
By default (d1 = logic 0) the pre-amplifier senses PECL
write signals at WDIx and WDIy. d1 should remain
logic 0.
8.10.5.1 MR head test
d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the
voltages at Rx and Ry (at the top of the MR elements) of
the selected head are fed to RDx and RDy outputs. By
measuring the output voltages single-ended at two
different IMR currents, the MR resistance can be accurately
measured according to the following formula:
d2
By default, (d2 = logic 0) the write current is inhibited
under low supply voltage conditions. The write current
inhibit is made inactive by programming d2 to logic 1.
d3
By default (d3 = logic 0), in write mode low supply
voltage, open head, and other conditions are monitored
and flagged at HUS. If d3 = logic 1, HUS is LOW in write
mode and HIGH in read mode.
V
RDx1 – VRDx2
RMRx
=
for the x side for instance.
--------------------------------------
MRx1 – IMRx2
I
Open head and head short-circuited to ground conditions
can therefore be detected.
d4
d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before,
with the difference that IMR2 is fixed to a minimum constant
value of 5 mA. Measuring in the same way as above with
IMR1 > 5 mA, enables the detection of MR elements
connected together.
The amplifier read gain may be programmed in the
configuration register. By default (d4 = logic 0), the read
gain is typically 160 with RMR = 28 Ω. If d4 = logic 1, the
read amplifier typical gain is 3 dB higher (i.e. 226 if
RMR = 28 Ω).
d5
8.10.5.2 Temperature monitor
In order to minimize the write-to-read recovery times,
the first stage of the read amplifier may be kept biased
during write mode. By default, (d5 = logic 0) the read
amplifier is powered-down during write mode, and the
fast settling procedure is activated after write-to-read
switching. If d5 = logic 1 the read amplifier is kept biased
during write mode, and the fast settling procedure still
occurs if the head is changed or the MR current is
re-programmed.
d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature
monitor voltages are connected to RDx and RDy. The
output differential voltage depends on the temperature
according to: dV = –0.00364 × T + 1.7 , 0 < T < 140 °C
The temperature may be measured with a typical precision
of 5 °C.
8.10.2 POWER CONTROL
By default d0 = d1 = logic 0, the pre-amplifier powers-up in
sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1,
d0 = logic 0 the circuit goes in standby mode.
1997 Jul 02
13
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
attenuator provides a pole which limits the bandwidth and
reduces the high-frequency noise. The HF pole can be
used in combination with the HF zero in order to boost the
HF gain locally and yet limit the very high frequency noise
enhancement.
8.10.5.3 Thermal asperity detector
d2 = logic 1, d1 = don’t care, d0 = either logic or 1. Unlike
the above tests, the thermal asperity detection does not
use the RDx to RDy outputs. Thus, the reader is fully
operational. In case a thermal asperity is detected, it is
flagged at the HUS pin.
8.10.8 HIGH FREQUENCY GAIN BOOST REGISTER
The threshold voltage for the thermal asperity detection is
2-bit programmable. These 2 bits consist of d0 (LSB) of
the test mode register (address = 0XXX0110), as the
MSB, and b2 of the compensation register
(address = 0XXX0111).
By default (d3 = d2 = d1 = d0 = logic 0), the high
frequency gain boost is not active. The gain boost provides
a zero which allows to optimize the bandwidth of the read
amplifier and to correct for attenuation caused by series
inductances in the leads between the MR-heads and the
read amplifier inputs.
Vth = (210 + 560 d0 + 280 b2) µV ,
where d0 is d0 of test mode register and b2 is d2 of
capacitor compensation register.
8.10.9 SETTLE PULSE
By default (d2 = d1 = d0 = logic 0) the settle pulse has a
nominal duration of 3 µs. Its value can be programmed
from 2.125 µs to 3 µs according to the following formula:
8.10.6 WRITE AMPLIFIER PROGRAMMABLE CAPACITORS
By default (d2 = d1 = d0 = logic 0) the programmable
capacitors are zero. These capacitors are used to improve
the performance of the write amplifier according to the
write amplifier output load.
1
tst = 2 +
µ s
-------------------------------------------------------------------------
(4 d2 + 2 d1 + 1 d0 + 1)
8.10.7 HIGH FREQUENCY GAIN ATTENUATOR POLE
REGISTER
By default (d3 = d2 = d1 = d0 = logic 0), the high
frequency gain attenuator is not active. The gain
8.10.10 ADDRESS REGISTERS; note 1
A7 A6 A5 A4 A3 A2 A1 A0
DESCRIPTION
0
0
0
0
0
0
1
0
configuration register:
d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop
d1 = 0: the WDI inputs are PECL levels; d1 = 1: invalid
d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive
read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH
write mode: d3 = 0: HUS active; d3 = 1: HUS LOW
d4 = 0: read gain nominal; d4 = 1: read gain nominal + 3 dB
d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON
during write mode
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
power control register:
(d1, d0) = (0, 0): sleep mode
(d1, d0) = (1, 0) or (0, 1): standby mode
(d1, d0) = (1, 1): active mode (write or read)
head select register:
6 channels: (d2,d1,d0) = (0,0,0) to (1,0,1): H0 to H5
4 channels: (d2,d1,d0) = (0, 0, 1) to (1, 0, 0): H1 to H4
1997 Jul 02
14
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
A7 A6 A5 A4 A3 A2 A1 A0
DESCRIPTION
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
MR current DAC register:
10 kΩ
Rext
IMR = 0.5 ×
× (10 + 16 d4 + 8 d3 + 4 d2 + 2 d1 + 1 d0) mA
---------------
write current DAC register:
10 kΩ
Rext
IWR
=
× (20 + 16 d4 + 8 d3 + 4 d2 + 2 d1 + 1 d0) mA
---------------
servo write register:
(d0, d1) = (0, 0) = one head
(d0, d1) = (1, 1) = all heads
test mode register:
(d2,d1,d0) = (0,0,0) = not in test mode
(d2,d1,d0) = (0,0,1) = read head test (IMR1 = IMR2
)
(d2,d1,d0) = (0,1,0) = read head test (IMR2 = 5 mA fixed)
(d2,d1,d0) = (0,1,1) = temperature monitor
(d2,d1,d0) = (1, X, d0) = thermal asperity detection
Vth = (210 + 560 d0 + 280 b2) µV , see note 2
0
1
1
0
1
0
1
0
0
0
0
0
1
1
0
0
compensation capacitor register:
equivalent differential capacitance: (4 d2 + 2 d1 + 1 d0) × 2 pF
high frequency gain attenuator register:
800 MHz
nominal pole frequency:
------------------------------------------------------------------------------
8 d3 + 4 d2 + 2 d1 + 1 d0
high-frequency gain boost register:
1
1
1
0
0
1
0
1
1
1
0
1
0
0
0
0
1
1
0
0
800 MHz
nominal zero frequency:
settle time register:
------------------------------------------------------------------------------
8 d3 + 4 d2 + 2 d1 + 1 d0
1
settle time: t st = 2 +
µ s
-------------------------------------------------------------------------
(4 d2 + 2 d1 + 1 d0 + 1)
0
0
0
0
1
1
1
1
chip ID register:
ID = 8 d3 + 4 d2 + 2 d1 + 1 d0 , d3 to d0 are preset to (0, 0, 1, 1)
a7 a6 a5 a4
when a0 = 1, data from the register with address a7 to a4 is read out on
SDATA
Notes
1. Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all
registers. For VCC < 2.5 V, the register contents are not guaranteed.
2. Vth programming uses both test mode register and compensation capacitor register. d0 in the formula above is the
LSB of the test mode register and b2 is the data bit d2 of the compensation register.
1997 Jul 02
15
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
Test mode: HUS is HIGH except when the TAS detector
8.11 Head unsafe
is ON. If a thermal asperity is detected, HUS goes LOW.
The HUS pin is an open-collector output. Consequently,
when the pin is not connected to an external pull-up
resistor, HUS is LOW. HUS pins can be connected
together in case of operation with more than one amplifier.
It is used to detect abnormal/unexpected operation.
Servo write mode: HUS is LOW
Write mode:
• if in the configuration register d3 = 1, HUS is LOW
• if in the configuration register d3 = 0, HUS goes HIGH
for: the write current may be inhibited if d1 = 0 in the
configuration register.
Sleep mode: HUS is HIGH, to permit working with more
than one amplifier.
Standby mode: HUS is HIGH, to permit working with
more than one amplifier.
– Rext pin open, short-circuited to ground or to VCC
(write current too low or too high)
Read mode:
– Write data input frequency too low (WDIx − WDIy)
• if in the configuration register d3 = 1, HUS is HIGH
– Write head Wx − Wy open, Wx or Wy short-circuited
to ground (switching to write mode makes HUS LOW;
after the transient the HUS detection circuitry is
activated; the target for the head-open detect time is
15 ns)
• if in the configuration register d3 = 0, HUS goes LOW
for:
– Rext pin open, short-circuited to ground or to VCC
(read current too low or too high)
– Write-head still left biased while not selected
– Low VCC and VCC(WD) conditions. A low supply
voltage detector is placed close to the VCC and
VCC(WD) pins.
– Low VCC and VCC(WD) conditions (write current inhibit
can be active or inactive).
The same detector is used for read and write mode. HUS
goes LOW again between 0.5 and 1 µs after the last
unsafe condition was detected.
Detection of low VCC (main general supply): a VCC supply
voltage below 4.0 V ±5% is flagged to the HUS pin.
The voltage detection range is then 4.2 to 3.8 V with an
hysteresis of 110 mV ±10%. Detection of low VCC(WD)
(writer dedicated supply): a fault will be flagged at HUS pin
if VCC(WD) drops 0.8 V ±10% below VCC. One must be
aware that such a detection is only aimed to warn for a
catastrophic situation. Indeed, VCC(WD) should never be
below VCC
.
8.12 HUS survey
HUS
DATA BIT D3
MODE
STATE
0
1
Sleep mode
Standby mode
−
−
−
−
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Read mode
A-test mode(1)
TAS mode
ACTIVE
HIGH
Read
Write
ACTIVE
ACTIVE
HIGH
ACTIVE
LOW
Active mode
Write mode
A-test mode(1)
Servo mode(2)
HIGH
LOW
LOW
Notes
1. HUS survey: A-test mode = analog test mode.
2. In servo mode, the performance of the IC is not guaranteed.
1997 Jul 02
16
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VCC
VCC(WD)
VIL
MIN.
MAX.
UNIT
supply voltage
−0.5
−0.5
−0.5
−0.5
+6.0
+9.5
+5.5
+5.5
+5.5
V
V
V
V
V
write driver supply voltage
LOW level digital input voltage
HIGH level digital input voltage
VIH
Vn1
voltage on all pins except VCC, read inputs nRx, nRy and −0.5
write outputs nWx, nWy (n = 0 to 9)
but not higher than
−
VCC + 0.5
+8.8
V
V
Vn2
voltage on write driver outputs nWx, nWy
but not higher than
−0.5
−
V
CC(WD) + 0.8 V
Vn3
InGND
Tstg
Tj
voltage on read inputs nRx, nRy
current through pins nGND
storage temperature
−0.5
−
1
V
0.1
+150
150
A
−65
−
°C
°C
junction temperature
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS device.
11 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient
TDA5153AG, TDA5153BG
TDA5153X
in free air
70
K/W
see note 1
Note
1. The TDA5153X is shipped in naked dies. The thermal resistance depends on the flex used.
1997 Jul 02
17
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
12 RECOMMENDED OPERATION CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage range
CONDITIONS
note 1
MIN.
4.5
TYP
MAX.
5.5
UNIT
−
−
−
−
V
V
V
V
V
VCC(WD)
VIH
write driver supply voltage
note 2
VCC
3.5
0
8.8
VCC
0.8
1.5
HIGH level input voltage (CMOS)
LOW level input voltage (CMOS)
VIL
Vi(dif)(p-p)
differential input voltage
(peak-to-peak value)
note 3
0.4
0.7
VIH(PECL) HIGH level PECL input voltage
note 3
note 3
1.5
−
2.85
2.15
−
VCC
−
V
V
VIL(PECL)
Tamb
Tj
LOW level PECL input voltage
ambient temperature
0
70
110
130
34
4
°C
°C
°C
Ω
junction temperature
reading
−
−
writing (VCC(WD) = 8 V)
−
−
RMR
MR element resistance
15
−
28
−
∆RMR
Ll(tot)
Rl(tot)
VMR
RMR mismatch
note 4
Ω
total lead inductance to the head
total lead resistance to the head
voltage on top of MR elements
in each lead; note 5
in each lead; note 5
note 6
−
35
1.5
−
−
nH
Ω
−
−
−
0.5
2
V
Vsig(dif)(p-p) differential MR head input signal
(peak-to-peak value)
0.4
1
mV
Lwh
Rwh
Cwh
Rext
write head inductance
write head resistance
write head capacitance
external reference resistor
including lead; note 5
including lead; note 5
including lead; note 5
Vref
−
−
−
−
0.15
10
5
−
−
−
−
µH
Ω
pF
k Ω
10
Iref
=
----------
Rext
Notes
1. A supply by-pass capacitor from VCC to ground or a low-pass filter may be used to optimize the PSRR.
2. The supply voltage VCC(WD) must never be below VCC in normal mode, and two diode voltages above VCC in servo
mode.
3. The given values should be interpreted in such a way that the single-ended voltage could swing 0.2 to 0.75 V and
that the common mode voltage should be such that for any of the two states, VIH(max) < VCC and VIL(min) > 1.5 V.
PECL voltage swing: a wider peak-to-peak voltage swing can be used. In that case a current will flow through the
(WDIx – WDIy) – 1.4
WDI inputs. This current is approximately equal to
----------------------------------------------------------
200
4. The mismatch refers to the resistance of the two stripes of the same head. This is defined as follows:
∆RMR = RMR1 − RMR2
5. These parameters depend on the head model. The values given are those used for testing.
6. The combination of maximum head resistance, lead resistance and bias current is not permitted. To avoid voltage
break-through between heads and disk, the voltage over the MR elements is limited by two diodes.
1997 Jul 02
18
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
13 CHARACTERISTICS
VCC = 5.0 V; VCC(WD) = 8 V; VGND = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
Read characteristics
IMR
MR current adjust range
tolerance (excluding Rext
Rext = 10 kΩ; 0.5 mA steps
5
−
20.5
mA
∆IMR
−
±4
−
%
)
I
– IMR(PR)
--M-----R--------------------------
IMR(PR)
with IMR(PR) = 10 mA
Gv(dif)
differential voltage gain; note 1
from head inputs to RDx, RDy;
RMR = 28 Ω; IMR = 10 mA;
f = 20 MHz;
d4 = 0
d4 = 1
−
−
−
−
−
−
−
−
−
160
226
13
−
−
Ri(dif)
Ci(dif)
THD
BL
differential input resistance
differential input capacitance
total harmonic distortion
IMR = 10 mA
−
Ω
16
−
pF
1
−
%
signal gain pass band edge; note 2 −3 dB
−
100
−
kHz
MHz
MHz
dB
BH
signal gain pass band edge without −3 dB (4 nH lead inductance)
220
170
3.0
gain boost; note 2
−3 dB (50 nH lead inductance)
−
F
noise figure; note 3
RMR = 28 Ω; IMR = 10mA;
amb = 25 °C; f = 20 MHz
3.2
T
Vnir
fB(L)
input referred noise voltage; note 3 RMR = 28 Ω; IMR = 10mA;
Tamb = 25 °C; f = 20 MHz
−
−
0.9
1.0
nV/√Hz
+3 dB noise low corner frequency RMR = 28 Ω; IMR = 10 mA;
400
kHz
Tamb = 25 °C; no lead
inductance
fB(H)
+3 dB noise upper corner
frequency
RMR = 28 Ω; IMR = 10 mA;
Tamb = 25 °C; no lead
inductance
−
220
MHz
αcs
channel separation; note 4
unselected head
−
−
−
50
80
50
dB
dB
dB
PSRR
power supply rejection ratio; note 5 f < 1 MHz; IMR = 10 mA
f < 100 MHz; IMR = 10 mA
CMRR
common mode rejection ratio;
note 5
from nRx − nRy to RDx − RDy;
MR mismatch < 5%;
R
IMR = 10 mA;
f < 1 MHz
−
−
−
45
25
50
dB
dB
dB
f < 100 MHz
DR
rejection of SCLK and SDATA;
note 6
from SCLK, SDATA inputs to
the RDx − RDy outputs; note 7
VO(R)(dif)
Zo(R)
output DC offset voltage in read
mode (differential after DC settling) RDx − RDy (in read mode)
DC voltage between
−
−
−
±0.2
V
output impedance in read mode
single ended
16
−
Ω
1997 Jul 02
19
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
mA
Io(max)(dif)
maximum differential output
current
−
4
−
Vo(cm)
common mode output voltage in
read mode
RDx, RDy
1.0
1.5
20
2.0
−
V
common mode DC supply rejection
in read mode
−
dB
∆Vocm
----------------
∆VCC
Zo(n)(dif)
differential output impedance in
−
50
−
kΩ
other modes (write, standby, sleep)
Write characteristics
IWR
write current adjust range (in the
write drivers)
Rext = 10 kΩ; 1 mA steps
WR(PR) = 35 mA
20
35
51
mA
%
∆IWR
I
−
±7
−
tolerance (excluding Rext);
I
– IRW (PR)
--W-----R----------------------------
IRW (PR)
Vs(max)(p-p) maximum voltage swing
(peak-to-peak value)
VCC(WD) = 5 V
CC(WD) = 8 V (differential)
−
−
−
−
−
8
V
V
−
13
−
V
Ro(dif)
tr, tf
differential output resistance
200
−
Ω
ns
write current rise/fall time without
flip-flop (10% to 90%); note 8
VCC(WD) = 8 V; Lh = 150 nH,
Rh = 10 Ω; IWR = 35 mA;
f = 20 MHz
1.8
tas
write current asymmetry; note 9
percentage of tr/tf
(tr, tf and logic asymmetry)
−
−
−
−
5
5
−
%
tpd
αcs
propagation delay 50% of
(WDIx/WDIy) to 50% of (Wx, Wy)
write head short circuited; data
flip-flop by passed
−
ns
dB
channel separation
unselected head
45
Switching characteristics
fSCLK
serial interface clock rate
−
−
−
25
MHz
mV
∆Vo(cm)
output common mode DC voltage IMR = 10 mA; IWR = 35 mA
change from Read to Write modes
200
−
trec(W-R)
write to read recovery time
(AC and DC settling); note 10
from 50% of the rising edge of
R/W to steady state read-back
signal: AC and DC settling at
90% (without load at
RDx − RDy)
read amplifier OFF: d5 = 0
read amplifier ON: d5 = 1
−
−
−
3
4.5
150
4.5
µs
µs
µs
100
3
tsw(R)
head switching (in read mode),
standby to read active and MR
current change recovery time;
(AC and DC settling); note 11
from falling edge of SEN to
steady state read-back signal;
(without load at RDx − RDy)
toff(R)
read amplifier off time
from falling edge of R/W to
read head inactive
−
−
50
ns
1997 Jul 02
20
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
ns
tst(W)
write settle times; note 12
from 50%of the falling edge of
R/W to 90% of the steady state
write current (in Write Mode)
−
−
70
toff(W)
write amplifier off time
from rising edge of R/W to
−
−
50
ns
IWR-programmed /10
(IWR = 35 mA)
tsw(W)
tsw(S)
head switching (in write mode),
and standby to write head active
from falling edge of SEN to
write head active
−
−
50
70
ns
sleep to (and from) any other
modes
−
100
µs
DC characteristics
ICC(R) supply current; note 13
ICC(W)
read mode; IMR = 10 mA
write mode; IWR = 35 mA
from VCC (5 V)
−
72
80
mA
supply current; note 14
−
−
−
−
−
33
41
61
1
mA
mA
mA
mA
V
from VCC(WD) (5 to 8 V)
54
IDD(stb)
IDD(S)
Vref
standby mode supply current
sleep mode supply current
reference voltage for Rext
0.25
0.025
1.32
static
−
−
Notes to the characteristics
Boltzmann constant and T is the temperature in K.
The noise figure is defined as follows:
1. The differential voltage gain depends on the MR
resistance. It can be improved by programming the
d4 bit in the configuration register using the serial
interface.
2
Vno
--------
Gv
F = 10 × log
dB
-----------------------------------------------------------
4kT × (RMR1 + RMR2
)
2. The gain boost implements a pole-zero combination:
The +3 dB gain boost corner frequency is
in 1 Hz bandwidth. Note that RMR includes all
resistances between Rx or Ry to ground.
800 MHz
-------------------------------------------------------------------------------------
(8 d3 + 4 d2 + 2 d1 + 1 d0)
b) Noise figure versus IMR and RMR: Table 1 shows
the variation of the noise figure with IMR (mA) and
RMR (Ω).
The −3 dB gain attenuation corner frequency is
800 MHz
-------------------------------------------------------------------------------------
(8 d3 + 4 d2 + 2 d1 + 1 d0)
c) Input noise voltage consideration: the input
referred noise voltage calculation can significantly
be different (from 1.0 to 0.44 nV/√Hz for instance)
by taking into account an equivalent
where d3, d2, d1, d0 are bits (0, 1) to be programmed
via the Serial Interface. In practical use, the bandwidth
is limited by the inductance of the connection between
the MR heads and the pre-amplifier.
signal-to-noise ratio when using two MR stripes
(28 Ω for each stripe) or one MR stripes (42 W).
It assumes that the signal coming from the head is
larger for a dual stripe head than for a single stripe
head (50% extra signal for dual stripe head).
3. Noise calculation
a) Definitions: The amplifier has a low-ohmic input.
No lead resistance is taken into account. The input
referred noise voltage, excluding the noise of the
MR resistors, is defined as follows:
4. The channel separation is defined by the ratio of the
gain response of the amplifier using the selected head
H(n) to the gain response of the amplifier using the
adjacent head H(n ±1), Head H(n) being selected.
2
Vno
2
V nir
=
– 4kT × (RMR1 + RMR2) V
--------
Gv
where Gv is the voltage gain and Vno is the noise
voltage at the output of the amplifier, k is the
1997 Jul 02
21
----------------------
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
8. The rise and fall times depend on the write
5. The PSRR (in dB) is defined as input referred ratio:
Gv
amplifier-write head combination. Lh and Rh represent
the components on the evaluation board. Parasitic
capacitances also limit the performance.
PSRR = 20 × log
------
Gp
Where Gv is the differential input to differential output
gain, and Gp is the power supply to differential output
gain. The CMRR (in dB) is defined as input referred
Gv
9. The write current rise/fall time asymmetry is defined by
tr – tf
2 (tr + tf)
ratio: CMRR = 20 × log
----------
Gcm
10. Write-to-read recovery time includes the write mode to
read mode switching using the R/W pin on the same
head (see Fig.6). The AC signal reaches its full
amplitude few tenth of ns after appearing at the reader
RDx and RDy outputs.
where Gv is the differential input to differential output
gain and Gcm is the common mode input to differential
output gain. Flex and board lay-out may affect
significantly these parameters.
11. In read mode, the head switching, standby to read
active switching and changing MR current include fast
current settling (see Fig.7). Same note regarding the
AC signals at the reader outputs as above.
6. This refers to the crosstalk from SCLK and SDATA
inputs via the read inputs to RDx − RDy. Two cases
can be distinguished:
a) With SEN LOW, SCLK and SDATA are prohibited
from entering the device and crosstalk is low.
12. Write settle time includes read mode to write mode
switching using the R/W pin.
b) Programming via the serial interface is done with
SEN HIGH. Then crosstalk can occur. A careful
design of the board or flex-foil is required in order
not to get crosstalk via this path.
13. The typical supply current in read mode depends on
the bias current for the MR element.
14. The typical supply current in write mode also depends
on the write current.
7. A 200 mV peak-to-peak signal is applied to SCLK or
SDATA inputs at 25 MHz, and measurement is
performed at RDx − RDy.
Table 1 Noise figure
F (dB)
RMR (Ω)
IMR = 7 mA
IMR = 10 mA
IMR = 15 mA
20
25
30
2.7
2.8
2.9
2.9
3.0
3.1
3.1
3.3
3.5
1997 Jul 02
22
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
R/W
RDx-RDy
t
rec(W-R)
t
off(R)
MGG985
Fig.6 Timing diagram of the reader: write-to-read switching on the same logic head.
h
SEN
RDx-RDy
t
MGG986
sw(R)
Fig.7 Timing diagram of the reader: typical head, current and standby-to-read characteristics.
23
1997 Jul 02
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
14 PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
Q
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75 0.69
0.45 0.59
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-06-15
94-12-19
SOT313-2
1997 Jul 02
24
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
If wave soldering cannot be avoided, the following
conditions must be observed:
15 SOLDERING
15.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
15.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
15.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
15.3 Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Jul 02
25
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
16 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jul 02
26
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
NOTES
1997 Jul 02
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Indonesia: see Singapore
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
297027/25/01/pp28
Date of release: 1997 Jul 02
Document order number: 9397 750 01904
相关型号：
©2020 ICPDF网 联系我们和版权申明