TDA5201 [INFINEON]
ASK Single Conversion Receiver; ASK单转换接收器
| 型号： | TDA5201 |
| 厂家： | 
Infineon |
| 描述： | ASK Single Conversion Receiver |
| 文件： | 总43页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
ASK Single Conversion Receiver
TDA 5201 Version 1.5
Specification July 2004
Revision History
Current Version: 1.5 as of 01.07.04
Previous Version: 1.4, March 2000
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
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Edition 07.04
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© Infineon Technologies AG July 2004.
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TDA 5201
Product Info
Product Info
Package
General Description The IC is a very low power consump-
tion single chip ASK Single Conver-
sion Receiver for receive frequencies
between 310 and 350MHz. The
Receiver offers a high level of integra-
tion and needs only a few external
components. The device contains a
low noise amplifier (LNA), a double
balanced mixer, a fully integrated
VCO, a PLL synthesiser, a crystal
oscillator, a limiter with RSSI genera-
tor, a data filter, a data comparator
(slicer) and a peak detector. Addition-
ally there is a power down feature to
save battery life.
Features ꢀ Low supply current
ꢀ Selectable frequency ranges
(Is = 4.6mA typ.)
around 315 MHz and 345 MHz
ꢀ Supply voltage range 5V ±10%
ꢀ Selectable reference frequency
ꢀ Power down mode with very low
ꢀ Limiter with RSSI generation,
supply current (50nA typ)
operating at 10.7MHz
ꢀ Fully integrated VCO and PLL
ꢀ 2nd order low pass data filter with
Synthesiser
external capacitors
ꢀ RF input sensitivity < –110dBm
ꢀ Data slicer with self-adjusting
threshold
Application ꢀ Keyless Entry Systems
ꢀ Remote Control Systems
ꢀ Fire Alarm Systems
ꢀ Low Bitrate Communication
Systems
Ordering Information
Type
Ordering Code
Q67037-A1118
Package
TDA 5201
P-TSSOP-28-1
available on tape and reel
Wireless Components
Product Info
Specification, July 2004
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
3.1
3.2
3.3
3.4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
9
10
10
10
10
11
11
11
11
12
12
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 Data Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
4.1
Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
4.3
4.4
4.5
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
7
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2
3
4
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
5.3
5.4
5.5
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
11
13
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5201
Product Description
2.1 Overview
The IC is a very low power consumption single chip ASK Superheterodyne
Receiver (SHR) for the frequency bands 315 and 345MHz. The SHR offers a
high level of integration and needs only a few external components. The device
contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated
VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a
data filter, a data comparator (slicer) and a peak detector. Additionally there is
a power down feature to save battery life.
2.2 Application
ꢀ Keyless Entry Systems
ꢀ Remote Control Systems
ꢀ Fire Alarm Systems
ꢀ Low Bitrate Communication Systems
2.3 Features
ꢀ Low supply current (Is = 4.6mA typ.)
ꢀ Supply voltage range 5V ±10%
ꢀ Power down mode with very low supply current (50nA typ.)
ꢀ Fully integrated VCO and PLL Synthesiser
ꢀ RF input sensitivity < –110dBm
ꢀ Selectable receive frequency bands 315 and 345MHz
ꢀ Selectable reference frequency
ꢀ Limiter with RSSI generation, operating at 10.7MHz
ꢀ 2nd order low pass data filter with external capacitors
ꢀ Data slicer with self-adjusting threshold
Wireless Components
2 - 2
Specification, July 2004
TDA 5201
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2 - 3
Specification, July 2004
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
TDA 5201
Functional Description
3.1 Pin Configuration
CRST1
VCC
LNI
1
2
3
4
5
6
7
8
9
28 CRST2
27 PDWN
26 PDO
25 DATA
24 3VOUT
23 THRES
22 FFB
21 OPP
20 SLN
19 SLP
18 LIMX
17 LIM
TAGC
AGND
LNO
VCC
MI
TDA 5201
MIX
AGND 10
FSEL 11
IFO 12
DGND 13
VDD 14
16 CSEL
15 LF
Pin_Configuration_5201_V1.4.wmf
Figure 3-1
IC Pin Configuration
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Specification, July 2004
TDA 5201
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No. Symbol Equivalent I/O-Schematic
Function
1
CRST1
External Crystal Connector 1
4.15V
1
50uA
2
3
VCC
LNI
5V Supply
LNA Input
57uA
3
500uA
4k
1k
Wireless Components
3 - 3
Specification, July 2004
TDA 5201
Functional Description
4
TAGC
AGC Time Constant Control
4.3V
3uA
4
1k
1.4uA
1.7V
5
6
AGND
LNO
Analogue Ground Return
LNA Output
5V
1k
6
7
8
VCC
MI
5V Supply
Mixer Input
1.7V
2k
2k
9
MIX
Complementary Mixer Input
8
9
400uA
10
11
AGND
FSEL
Analogue Ground Return
not applicable - has to be left
open
Wireless Components
3 - 4
Specification, July 2004
TDA 5201
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
Digital Ground Return
5V Supply (PLL Counter Cir-
cuitry)
15
LF
PLL Filter Access Point
5V
4.6V
30uA
200
15
100
30uA
2.4V
16
CSEL
5.xx or 10.xx MHz Quartz
Selector
1.2V
80k
16
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3 - 5
Specification, July 2004
TDA 5201
Functional Description
17
18
LIM
Limiter Input
2.4V
15k
17
LIMX
Complementary Limiter Input
75uA
330
15k
18
19
SLP
Data Slicer Positive Input
15uA
100
3k
19
40uA
20
SLN
Data Slicer Negative Input
5uA
10k
20
Wireless Components
3 - 6
Specification, July 2004
TDA 5201
Functional Description
21
22
23
24
25
OPP
OpAmp Noninverting Input
Data Filter Feedback Pin
AGC Threshold Input
3V Reference Output
Data Output
5uA
200
100k
10k
21
FFB
5uA
22
THRES
3VOUT
DATA
5uA
23
24
3V
200
25
80k
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3 - 7
Specification, July 2004
TDA 5201
Functional Description
26
PDO
Peak Detector Output
200
26
27
PDWN
Power Down Input
27
220k
220k
28
CRST2
External Crystal Connector 2
4.15V
28
50uA
Wireless Components
3 - 8
Specification, July 2004
TDA 5201
Functional Description
3.3 Functional Block Diagram
VCC
IF
Filter
LNO
6
MI MIX IFO
LIM
17
LIMX
18
FFB
22
OPP
21
SLP
19
SLN
20
9
8
12
25
DATA
3
RF
LNA
RSSI
SLICER
PDO
26
23
4
TAGC
THRES
3VOUT
AGC
Reference
24
TDA 5201
14
VDD
UREF
Φ
Crystal
OSC
: 1/2
VCO
: 128/64
DET
DGND 13
Bandgap
Reference
Loop
Filter
2/7
VCC
5/10
AGND
28
11
FSEL
15
LF
16
1
27
CSEL
PDWN
Crystal
Function_5200.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3 - 9
Specification, July 2004
TDA 5201
Functional Description
3.4 Functional Blocks
3.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The
gain figure is determined by the external matching networks situated ahead of
LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX
(Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current
consumption is 500µA. The gain can be reduced by approximately 18dB. The
switching point of this AGC action can be determined externally by applying a
threshold voltage at the THRES pin (Pin 23). This voltage is compared internally
with the received signal (RSSI) level generated by the limiter circuitry. In case
that the RSSI level is higher than the threshold voltage the LNA gain is reduced
and vice versa. The threshold voltage can be generated by attaching a voltage
divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3V output generated from the internal bandgap voltage and the THRES pin as
described in Section 4.1. The time constant of the AGC action can be deter-
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a vol-
tage gain of approximately 21dB by utilising either high- or low-side injection of
the local oscillator signal. In case the mixer is interfaced only single-ended, the
unused mixer input has to be tied to ground via a capacitor. The mixer is fol-
lowed by a low pass filter with a corner frequency of 20MHz in order to suppress
RF signals to appear at the IF output (IFO pin). The IF output is internally con-
sisting of an emitter follower that has a source impedance of approximately
330Ω to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter
without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO
was designed to guarantee over production spread and the specified tempera-
ture range a receive frequency range between 310 and 350MHz depending on
whether high- or low-side injection of the local oscillator is used. The oscillator
signal is fed both to the synthesiser divider chain and to a divider that is dividing
Wireless Components
3 - 10
Specification, July 2004
TDA 5201
Functional Description
the signal by 2 before it is applied to the downconverting mixer. Local oscillator
high side injection has to be used for receive frequencies between approxi-
mately 310 and 330 MHz, low side injection for receive frequencies between
330 and 350MHz - see also Section 4.4..
3.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in
the 5 and 10MHz range as the overall division ratio of the PLL can be switched
between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States
CSEL
Crystal Frequency
5.xx MHz
Open
Shorted to ground
10.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown
in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80dB that has a bandpass-characteristic centred around
10.7MHz. It has an input impedance of 330 Ω to allow for easy interfacing to a
10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength
Indicator (RSSI) generator which produces a DC voltage that is directly propor-
tional to the input signal level as can be seen in Figure 4-2. This signal is used
to demodulate the ASK receive signal in the subsequent baseband circuitry and
to turn down the LNA gain by approximately 18dB in case the input signal
strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
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Specification, July 2004
TDA 5201
Functional Description
3.4.7 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of approximately 120kBaud. The maximum
achievable data rate also depends on the IF Filter bandwidth and the local oscil-
lator tolerance values. Both inputs are accessible. The output delivers a digital
data signal (CMOS-like levels) for the detector. The self-adjusting threshold on
pin 20 its generated by RC-term or peak detector depending on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4.8 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The out-
put can be used as an indicator for the signal strength and also as a reference
for the data slicer. The maximum output current is 500µA.
3.4.9 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States
PDWN
Operating State
Powerdown Mode
Receiver On
Open or tied to ground
Tied to Vs
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Specification, July 2004
4
Applications
Contents of this Chapter
4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . 4-2
4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
TDA 5201
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is
shown.
R4
R5
Uthreshold
Pins:
24
23
RSSI (0.8 - 2.8V)
+3V
OTA
VCC
Iload
LNA
Gain control
voltage
RSSI > Uthreshold: Iload=4.2µA
RSSI < Uthreshold: Iload= -1.5µA
4
Uc:< 2.6V : Gain high
Uc:> 2.6V : Gain low
UC
C
U
cmax= VCC - 0.7V
Ucmin = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimped-
ance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
U
thres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control volt-
age.
Wireless Components
4 - 2
Specification, July 2004
TDA 5201
Applications
3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating sce-
nario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power con-
sumption, the power divider resistors should have high impedance values. R4
can be chosen as 120kΩ, R5 as 180kΩ to yield an overall 3VOUT output current
of 10µA.
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
Wireless Components
4 - 3
Specification, July 2004
TDA 5201
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 exter-
nal capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
22
C2
21
Pins:
19
R
R
100k
100k
Filter_Design.wmf
Figure 4-3
Data Filter Design
2Q b
C1 =
R2Πf3dB
b
C2 =
4QRΠf3dB
with
b
Q =
a
the quality factor of the poles where
in case of a Bessel filter
and thus
a = 1.3617, b = 0.618
Q = 0.577
and in case of a Butterworth filter
and thus
a = 1.141, b = 1
Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4 - 4
Specification, July 2004
TDA 5201
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Input
impedance
Crystal
Z1-28
TDA5200
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
1
CS =
1
+ 2π f X L
Cl
with Cl the load capacitance (refer to the quartz crystal specification).
Examples:
5.1 MHz:
CL = 12 pF
XL=580 Ω
XL=870 Ω
CS = 9.8 pF
CS = 7.2 pF
10.18 MHz: CL = 12 pF
These values may be obtained by putting two capacitors in series to the quartz,
such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz
case.
But please note that the calculated value of CS includes the parasitic capacitors
also.
Wireless Components
4 - 5
Specification, July 2004
TDA 5201
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is wide
enough to guarantee a receive frequency range between 310 and 350MHz. The
VCO signal is divided by 2 before applied to the mixer . This local oscillator sig-
nal can be used to downconvert the RF signals both with high- or low-side injec-
tion at the mixer. High-side injection of the local oscillator has to be used for
receive frequencies between 310 and 330 MHz. In this case the local oscillator
frequency is calculated by adding the IF frequency (10.7 MHz) to the RF fre-
quency.
Low-side injection has to be used for receive frequencies between 330 and
350 MHz. The local oscillator frequency is calculated by subtracting the IF fre-
quency (10.7 MHz) from the RF frequency then. The overall division ratios in
the PLL are 64 or 32 depending on whether the CSEL-pin is left open or tied to
ground.
Therefore the quartz frequency may be calculated by using the following for-
mula:
fRF −10.7
fQU
=
r
with
ƒRF ....
ƒLO ....
ƒQU ....
receive frequency
local oscillator (PLL) frequency (ƒRF ± 10.7)
quartz oscillator frequency
r
....
ratio of local oscillator (PLL) frequency and quartz
frequency as shown in the subsequent table.
Table 4-1 PLL Division Ratio Dependence on States of CSEL
CSEL
open
GND
Ratio r = (fLO/fQU)
64
32
Example:
Addition of 10.7 is used in case of operation the device at 315 MHz, subtraction
in case of operation at 345 MHz for instance. This yields the following frequen-
cies:
CSEL tied to GND:
fQU
fQU
=
=
(
315MHz +10.7MHz
)
)
/ 32 = 10.1781 MHz
/ 32 = 10.4469 MHz
(
345MHz −10.7MHz
Wireless Components
4 - 6
Specification, July 2004
TDA 5201
Applications
CSEL open:
fQU
fQU
=
=
(
315MHz + 10.7MHz
)
)
/ 64 = 5.0891 MHz
/ 64 = 5.2234 MHz
(
345MHz −10.7MHz
Wireless Components
4 - 7
Specification, July 2004
TDA 5201
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer especially for a coding scheme without DC-con-
tent, can be generated in two ways, depending on the signal coding scheme
used. In case of a signal coding scheme without DC content such as Manches-
ter coding the threshold can be generated using an external R-C integrator as
shown in Figure 4-5. The time constant TA of the R-C integrator has to be sig-
nificantly larger than the longest period of no signal change TL within the data
sequence. In order to keep distortion low, the minimum value for R is 20kΩ.
R
C
data out
Pins:
19
20
25
Uthreshold
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in con-
nection with two resistors and one capacitor as shown in the following figure.
The component values are depending on the coding scheme and the protocol
used.
R
C
R
data out
Pins:
20
19
26
25
Uthreshold
peak detector
data slicer
data
filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4 - 8
Specification, July 2004
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.5 Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . 5-13
TDA 5201
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T
=-40°C ... + 85°C
Limit Values
AMB
#
Parameter
Symbol
Unit
Remarks
min
-0.3
max
5.5
1
2
3
4
5
Supply Voltage
Vs
Tj
V
°C
Junction Temperature
Storage Temperature
Thermal Resistance
ESD integrity, all pins
-40
-40
+125
+150
114
+1
Ts
°C
RthJA
VESD
K/W
kV
-1
HBM
according to
MIL STD
883D,
method
3015.7
Wireless Components
5 - 2
Specification, July 2004
TDA 5201
Reference
5.1.2 Operating Range
Within the operating range the IC operates as explained in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature T
= -40°C ... + 85°C
AMB
#
Parameter
Symbol
Limit Values
Unit
Test Conditions/Notes
L
Item
min
max
5.2
1
2
Supply Current
I
mA
f
= 315MHz
RF
S
Receiver Input Level
RFin
-110
-13
dBm
@ source impedance 50Ω,
BER 2E-3, average power
level, Manchester encoded
datarate 4kBit, 280kHz IF
Bandwidth
ꢀ
3
4
5
6
7
8
LNI Input Frequency
MI/X Input Frequency
3dB IF Frequency Range
Powerdown Mode On
Powerdown Mode Off
fRF
fMI
310
310
5
350
350
23
MHz
MHz
MHz
V
fIF -3dB
PWDNON
PWDNOFF
VTHRES
0
0.8
2
V
V
S
S
Gain Control Voltage,
LNA high gain state
2.8
V
V
9
Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7V
V
ꢀꢀ Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in
Section 5.2.
Wireless Components
5 - 3
Specification, July 2004
TDA 5201
Reference
5.1.3 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the spec-
ified voltage and ambient temperature range. Typical characteristics are the
median of the production. The device performance parameters marked with ꢀ
are not part of the production test, but verified by design or measured on an Infi-
neon evaluation board as desdribed in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V
#
Parameter
Symbol
Limit Values
Unit Test Conditions /
L
Item
Notes
min
typ
max
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
50
70
5
nA
Pin 27 (PDWN)
open or tied to 0 V
2
Supply current
I
4.6
mA
S
LNA
Signal Input LNI (PIN 3), V
> 2.8V, high gain mode
THRES
1
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-112
dBm Manchester
encoded datarate
ꢀ
4kBit, 280kHz IF
Bandwidth
ꢀ
ꢀ
ꢀ
2
3
4
Input impedance,
S
0.895 / -25.5 deg
11 LNA
f
= 315 MHz
RF
Input level @ 1dB C.P.
fRF=315 MHz
P1dB
IIP3
-14
-10
dBm
LNA
Input 3rd order intercept
LNA
LNI
dBm fin = 315 & 317MHz
dBm
point f = 315 MHz
RF
ꢀ
5
LO signal feedthrough at
antenna port
LO
-119
Signal Output LNO (PIN 6), V
> 2.8V, high gain mode
THRES
ꢀ
ꢀ
1
2
Gain f = 315 MHz
RF
S
1.577 / 150.3 deg
21 LNA
22 LNA
Output impedance,
S
0.897 / -10.3 deg
f
= 315 MHz
RF
3
4
Voltage Gain Antenna to
G
21
2
dB
AntMI
MI f = 315 MHz
RF
ꢀ
Noise Figure
NF
dB
excluding matching
network loss - see
Appendix
LNA
Signal Input LNI, V
= GND, low gain mode
THRES
ꢀ
ꢀ
1
Input impedance,
= 315 MHz
S
0.918 / -25.2 deg
-7
11 LNA
f
RF
2
Input level @ 1dB C. P.
= 315 MHz
P1dB
LNA
dBm matched input
f
RF
Wireless Components
5 - 4
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions/
Notes
L
Item
min
= GND, low gain mode
typ
max
Signal Input LNI, V
THRES
Input 3rd order intercept
LNA
ꢀ
3
IIP3
-13
dBm fin = 315 & 317MHz
point f = 315 MHz
RF
Signal Output LNO, V
= GND, low gain mode
THRES
ꢀ
ꢀ
1
2
Gain f = 315 MHz
S
0.007 / 153.7 deg
0.907 / -10.5 deg
RF
21 LNA
22 LNA
Output impedance,
S
f
= 315 MHz
RF
3
Voltage Gain Antenna to
MI f = 315 MHz
G
2
3
dB
AntMI
RF
Signal 3VOUT (PIN 24)
1
2
Output voltage
Current out
V
I
V
3VOUT
50
µA
3VOUT
Signal THRES (PIN 23)
1
2
3
4
Input Voltage range
LNA low gain mode
LNA high gain mode
Current in
V
0
0
V -1V
S
V
V
see chapter 4.1
THRES
THRES
THRES
V
V
2.8
3
5
V -1
S
V
or shorted to Pin 24
ꢀ
ITHRES_in
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
4.2
1.5
µA
µA
RSSI > V
RSSI < V
THRES
2
Current in,
I
TAGC_in
THRES
LNA high gain state
MIXER
Signal Input MI/MIX (PINS 8/9)
ꢀ
ꢀ
1
Input impedance,
= 315 MHz
S
0.954 / -10.9 deg
-25
11 MIX
f
RF
Input 3rd order intercept
point
MIX
2
IIP3
dBm
Signal Output IFO (PIN 12)
1
2
Output impedance
Z
330
+21
Ω
IFO
Conversion Voltage Gain
G
dB
MIX
f
=869 MHz
RF
ꢀ
ꢀ
3
4
Noise Figure, SSB
(~DSB NF+3dB)
NF
13
46
dB
dB
MIX
RF to IF isolation
A
RF-IF
Wireless Components
5 - 5
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions/
Notes
L
Item
min
typ
max
LIMITER
Signal Input LIM/X (PINS 17/18)
ꢀ
1
2
3
4
Input Impedance
RSSI dynamic range
RSSI linearity
Z
264
60
330
396
80
Ω
dB
LIM
DR
LIN
f
RSSI
RSSI
ꢀ
ꢀ
dB
±1
Operating frequency (3dB
points)
5
10.7
23
MHz
LIM
DATA FILTER
ꢀ
1
2
3
Useable bandwidth
BW
100
kHz
BB
FILT
RSSI Level at Data Filter
Output SLP
RSSI
1.1
V
V
LNA in high gain
low
RF ~-103dBm
IN
RSSI Level at Data Filter
Output SLP
RSSI
2.65
LNA in high gain.
high
RF ~-30dBm
IN
SLICER
Signal Output DATA (PIN 25)
ꢀ
1
Useable bandwith
BW
100
20
kHz
pF
BB
SLIC
2
Capacitive loading of out-
put
C
max
SLIC
3
4
LOW output voltage
HIGH output voltage
V
V
0
V
V
SLIC_L
V -1.3
V -1
S
V -0.7
S
Output current
=200µA
S
SLIC_H
5
Output current
I
200
µA
SLIC_out
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
2
3
LOW output voltage
HIGH output voltage
Load current
V
V
0
V
V
SLIC_L
V -1
S
SLIC_H
I
-500
µA
Static load current
must not exceed
-500µA
load
4
Leakage current
I
700
nA
leakage
Wireless Components
5 - 6
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit Test Conditions/
Notes
L
Item
min
typ
max
CRYSTAL OSCILLATOR
Signals CRSTL1, CRISTL 2, (PINS 1/28)
1
Operating frequency
f
5
11
MHz fundamental mode,
series resonance
CRSTL
ꢀ
ꢀ
2
Input Impedance
@ ~5MHz
Z
-760
+j580
Ω
1-28
3
4
5
Input Impedance
@ ~10MHz
Z
-600
+j870
Ω
1-28
Serial Capacity
@ ~5MHz
C
C
=C1
9.3
pF
pF
S 5
Serial Capacity
@ ~10MHz
=C1
6.4
S10
PLL
Signal LF (PIN 15)
1
Tuning voltage relative to
V
0.4
1.6
2.4
V
V
TUNE
V
s
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDN
N
2.8
0
V
S
O
2
3
4
Powerdown Mode Off
PWDN
0.8
V
Off
Input bias current PDWN
I
19
1
µA
PDWN
Start-up Time until valid IF
signal is detected
T
mS
Depends on the
used crystal
SU
PLL DIVIDER
Signal CSEL (PIN 16)
1
2
f
range 5.xxMHz
range 10.xxMHz
V
1.4
0
4
V
V
or open
CRSTL
CRSTL
CSEL
CSEL
f
V
0.2
3
Input bias current CSEL
I
5
µA
CSEL tied to GND
CSEL
ꢀꢀ Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in
Section 5.2.
Wireless Components
5 - 7
Specification, July 2004
TDA 5201
Reference
5.2 Test Circuit
The device performance parameters marked with ꢀ in Section 5.1.3 were either
verified by design or measured on an Infineon evaluation board. This evaluation
board can be obtained together with evaluation boards of the accompanying
transmitter device TDA5101 in an evaluation kit that may be ordered on the
INFINEON RKE Webpage www.infineon.com/rke
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5 - 8
Specification, July 2004
TDA 5201
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5 - 9
Specification, July 2004
TDA 5201
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 10
Specification, July 2004
TDA 5201
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5201 at
315MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials
Ref
Value
100kΩ
100kΩ
820kΩ
120kΩ
180kΩ
10kΩ
15nH
12pF
Specification
0805, ± 5%
R1
R2
0805, ± 5%
R3
0805, ± 5%
R4
0805, ± 5%
R5
0805, ± 5%
R6
0805, ± 5%
L1
Toko, PTL2012-F15N0G
0805,COG, ± 2%
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
0805, COG, ± 5%
1206, X7R, ± 10%
Toko, PTL2012-F15N0G
0805, COG, ± 5%
0805, COG, ± 5%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, COG, ± 5%
0805, X7R, ± 10%
0805, COG, ± 0.1pF
0805, COG, ± 2%
L2
C1
3.3 pF
10pF
C2
C3
6.8pF
100pF
47nF
C4
C5
C6
15nH
100pF
33pF
C7
C8
C9
100pF
10nF
C10
C11
C12
C13
C14
C15
C16
C17
10nF
220pF
47nF
470pF
47nF
18pF
12pF
Q2
(315 + 10.7MHz)/32
HC49/U, fundamental mode, C = 12pF,
L
e.g. 434.2 MHz: Jauch Q 10.17813-S11-1323-12-10/20
F1
X2, X3
X1, X4, S1, S5
S4
SFE10.7MA5-A
142-0701-801
Murata
Johnson
2-pole pin connector
3-pole pin connector, or not equipped
Infineon
IC1
TDA 5201
Wireless Components
5 - 11
Specification, July 2004
TDA 5201
Reference
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5201 in conjunction with a Microchip HCS515
decoder.
Table 5-5 Bill of Materials Addendum
Ref
Value
22kΩ
Specification
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
0805, ± 5%
1206, X7R, ± 10%
1206, X7R, ± 10%
Microchip
R21
R22
R23
R24
R25
C21
C22
IC2
T1
100kΩ
22kΩ
820kΩ
560kΩ
100nF
100nF
HCS515
BC 847B
LS T670-JL
Infineon
D1
Infineon
Wireless Components
5 - 12
Specification, July 2004
TDA 5201
Reference
5.5 Appendix - Noise Figure and Gain Circles
The following gain and noise figure circles were measured utilizing Microlab
Stub Stretchers and a HP8514 network analyser. Maximum gain is shown at
point 1 at 18.5 dB, minimum noise figure ist 1.9dB at point 2, step size of circles
is 0.5dB.
Figure 5-5
Gain and Noise Circles of the TDA5201 at 315 MHz.
Wireless Components
5 - 13
Specification, July 2004
TDA 5201
List of Figures
List of Figures
Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-2 RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . .
Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . .
Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . .
Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2 Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-5 Gain and Noise Circles of the TDA5201 at 315 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . .
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Wireless Components
List of Figures - 1
Specification, July 2004
TDA 5201
List of Tables
List of Tables
Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-3 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C . . . . . . . . .
Table 5-2 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C . . . . . . . . . . . . . . . . .
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 5
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AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 6
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued) 7
Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Wireless Components
List of Tables - 1
Specification, July 2004
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