TDA5201_10 [INFINEON]
ASK Single Conversion Receiver; ASK单转换接收器
| 型号： | TDA5201_10 |
| 厂家： | 
Infineon |
| 描述： | ASK Single Conversion Receiver |
| 文件： | 总38页 (文件大小：1683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA 5201
ASK Single Conversion Receiver
Version 1.6
Data Sheet
Revision 1.6, 2010-12-21
Wireless Components
Edition 2010-12-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TDA 5201
ASK Single Conversion Receiver
Revision History
Page or Item
Subjects (major changes since previous revision)
Previous Revision: 1.5
Revision 1.6, 2010-12-21
all
Converted into structured FrameMaker (EDD 3.4)
More detailed explanation of AGC
4-3
5-5, 5-7
5-3, 5-4
More detailed information of LNA high gain mode and LNA low gain mode
Enhanced sensitivity values
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,
CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,
MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,
PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,
SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2010-10-26
Data Sheet
3
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Product Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
2
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
3
3.1
3.2
3.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
4.2
4.3
4.4
4.5
5
5.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1
5.1.2
5.1.3
5.2
5.2.1
5.2.2
5.2.3
Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
4
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
PG-TSSOP-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PG-TSSOP-28 Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical Curve of RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . 22
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . . . . . . . . . 24
Data Slicer Threshold Generation with External R-C Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11 Schematic of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12 Top Side of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15 Gain and Noise Circles of the TDA5201 at 315 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
5
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Absolute Maximum Ratings, Ambient Temperature TAMB = - 40 °C ... + 85 °C . . . . . . . . . . . . . . . 27
Operating Range, Ambient Temperature TAMB = - 40 °C ... + 85 °C . . . . . . . . . . . . . . . . . . . . . . . 27
AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
6
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Product Info
1
Product Info
General Description
The IC is a very low power consumption single chip ASK Single Conversion Receiver for receive frequencies
between 310 MHz and 350 MHz. The Receiver offers a high level of integration and needs only a few external
components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a
peak detector. Additionally there is a power down feature to save battery life.
Features
•
•
•
•
•
•
•
•
•
•
Low supply current (Is = 4.6 mA typ.)
Supply voltage range 5 V ±10 %
Power down mode with very low supply current (50 nA typ)
Fully integrated VCO and PLL Synthesizer
RF input sensitivity < – 110 dBm
Selectable frequency ranges around 315 MHz and 345 MHz
Selectable reference frequency
Limiter with RSSI generation, operating at 10.7 MHz
2nd order low pass data filter with external capacitors
Data slicer with self-adjusting threshold
Application
•
•
•
•
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication Systems
Package
Figure 1
PG-TSSOP-28
Ordering Information
Type
Ordering Code
Package1)
TDA5201
SP000012902
PG-TSSOP-28
1) Available on tape and reel
Data Sheet
7
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Product Description
2
Product Description
2.1
Overview
The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency
bands 315 MHz and 345 MHz. The SHR offers a high level of integration and needs only a few external
components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a
peak detector. Additionally there is a power down feature to save battery life.
2.2
Application
•
•
•
•
Keyless Entry Systems
Remote Control Systems
Fire Alarm Systems
Low Bitrate Communication Systems
2.3
Features
•
•
•
•
•
•
•
•
•
•
Low supply current (Is = 4.6 mA typ.)
Supply voltage range 5 V ±10 %
Power down mode with very low supply current (50 nA typ.)
Fully integrated VCO and PLL Synthesizer
RF input sensitivity < – 110 dBm
Selectable receive frequency bands 315 MHz and 345 MHz
Selectable reference frequency
Limiter with RSSI generation, operating at 10.7 MHz
2nd order low pass data filter with external capacitors
Data slicer with self-adjusting threshold
Data Sheet
8
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Product Description
2.4
Package Outlines
Figure 2
PG-TSSOP-28 Package Outlines
Data Sheet
9
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
3
Functional Description
3.1
Pin Configuration
CRST1
VCC
LNI
1
2
3
4
5
6
7
8
9
28 CRST2
27 PDWN
26 PDO
25 DATA
24 3VOUT
23 THRES
22 FFB
TAGC
AGND
LNO
VCC
MI
TDA 5201
21 OPP
20 SLN
MIX
AGND 10
FSEL 11
IFO 12
19 SLP
18 LIMX
17 LIM
DGND 13
VDD 14
16 CSEL
15 LF
Figure 3
IC Pin Configuration
Data Sheet
10
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
3.2
Pin Definition and Function
Table 1
Pin Definition and Function
Pin
No.
Name
Pin
Type
Buffer Type
Function
1
CRST1
In/Out
External Crystal Connector 1
4.15V
1
50uA
2
3
VCC
LNI
In
In
5 V Supply
LNA Input
57uA
3
500uA
4k
1k
Data Sheet
11
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
4
TAGC
In/Out
AGC Time Constant Control
4.3V
4.2uA
1.5uA
4
1k
1.7V
5
6
AGND
LNO
In
Analogue Ground Return
LNA Output
Out
5V
1k
6
7
8
VCC
MI
In
In
5 V Supply
Mixer Input
1.7V
2k
2k
8
9
400uA
Data Sheet
12
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
9
MIX
In
Complementary Mixer Input
1.7V
2k
2k
8
9
400uA
10
11
AGND
FSEL
In
Analogue Ground Return
Not applicable - has to be left
open
12
IFO
Out
IF Mixer Output
10.7 MHz
300uA
2.2V
60
12
4.5k
13
14
DGND
VDD
In
In
Digital Ground Return
5 V Supply
PLL Counter Circuitry
Data Sheet
13
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
15
LF
In/Out
PLL Filter Access Point
5V
4.6V
30uA
200
100
15
30uA
2.4V
16
CSEL
In
Quartz Selector
5.xx MHz or 10.xx MHz
1.2V
80k
16
17
LIM
In
Limiter Input
2.4V
15k
17
75uA
330
15k
18
Data Sheet
14
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
18
LIMX
In
Complementary Limiter Input
2.4V
15k
17
75uA
330
15k
18
19
SLP
In
Data Slicer Positive Input
15uA
100
3k
9
40uA
20
SLN
In
Data Slicer Negative Input
5uA
10k
20
21
OPP
In
OpAmp Noninverting Input
5uA
200
21
Data Sheet
15
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
22
23
24
25
FFB
In
Data Filter Feedback Pin
5uA
100k
22
THRES
3VOUT
DATA
In
AGC Threshold Input
3 V Reference Output
Data Output
5uA
10k
23
Out
24
3V
Out
200
25
80k
26
PDO
Out
Peak Detector Output
200
26
Data Sheet
16
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
Table 1
Pin Definition and Function (cont’d)
Pin
No.
Name
Pin
Type
Buffer Type
Function
27
PDWN
In
Power Down Input
27
220k
220k
28
CRST2
In/Out
External Crystal Connector 2
4.15V
28
50uA
Data Sheet
17
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
3.3
Functional Block Diagram
VCC
IF
Filter
LNO
6
MI MIX IFO
LIM
17
LIMX
18
FFB
22
OPP
21
SLP
19
SLN
20
9
8
12
25
DATA
3
RF
LNA
RSSI
SLICER
PDO
26
23
4
TAGC
THRES
3VOUT
AGC
Reference
24
TDA 5201
14
VDD
UREF
Φ
Crystal
OSC
: 1/2
VCO
: 128/64
DET
DGND 13
Bandgap
Reference
Loop
Filter
2/7
VCC
5/10
AGND
28
11
FSEL
15
LF
16
1
27
CSEL
PDWN
Crystal
Figure 4
Main Block Diagram
Data Sheet
18
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
3.4
Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 dB to 20 dB. The gain figure is determined by
the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer
Inputs MI and MIX (Pin 8 and Pin 9). The noise figure of the LNA is approximately 2 dB, the current consumption
is 500 µA. The gain can be reduced by approximately 18 dB. The switching point of this AGC action can be
determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared
internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is
higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated
by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output
generated from the internal bandgap voltage and the THRES pin as described in Chapter 4.1. The time constant
of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operating case and interference scenario
to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described
in Chapter 4.1.
3.4.2
Mixer
The Double Balanced Mixer down-converts the input frequency (RF) in the range of 310 MHz to 350 MHz to the
intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 21 dB by utilizing either high- or low-
side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input
has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20 MHz
in order to suppress RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an
emitter follower that has a source impedance of approximately 330 Ω to facilitate interfacing the pin directly to a
standard 10.7 MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with
charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor
diodes. The FSEL pin (Pin 11) has to be left open. The tuning range of the VCO was designed to guarantee over
production spread and the specified temperature range a receive frequency range between 310 MHz and
350 MHz depending on whether high- or low-side injection of the local oscillator is used. The oscillator signal is
fed both to the synthesizer divider chain and to a divider that is dividing the signal by 2 before it is applied to the
down-converting mixer. Local oscillator high side injection has to be used for receive frequencies between
approximately 310 MHz and 330 MHz, low side injection for receive frequencies between 330 MHz and 350 MHz
- see also Chapter 4.4.
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilization of quartzes both in the 5 MHz and 10 MHz range as the
overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16) pin according to the
following table.
Table 2
CSEL
Open
CSEL Pin Operating States
Crystal Frequency
5.xx MHz
Shorted to ground
10.xx MHz
Data Sheet
19
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Functional Description
The calculation of the value of the necessary quartz load capacitance is shown in Chapter 4.3, the quartz
frequency calculation is explained in Chapter 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a
bandpass-characteristic centered around 10.7 MHz. It has an input impedance of 330 Ω to allow for easy
interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI)
generator, which produces a DC voltage that is directly proportional to the input signal level as can be seen in
Figure 6. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to
turn down the LNA gain by approximately 18 dB in case the input signal strength is too strong as described in
Chapter 3.4.1 and Chapter 4.1.
3.4.6
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 kΩ on-
chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of
the capacitor values is described in Chapter 4.2.
3.4.7
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of
approximately 120 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the
local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like
levels) for the detector. The self-adjusting threshold on pin 20 is generated by RC-term or peak detector
depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in
more detail in Chapter 4.5.
3.4.8
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An
external RC network is necessary. The output can be used as an indicator for the signal strength and also as a
reference for the data slicer. The maximum output current is 500 µA.
3.4.9
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode
is available to switch off all sub-circuits which is controlled by the PWDN pin (Pin 27) as shown in the following
table. The supply current drawn in this case is typically 50 nA.
Table 3
PDWN
PDWN Pin Operating States
Operating State
Power Down Mode
Receiver On
Open or tied to ground
Tied to VCC
Data Sheet
20
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
4
Applications
4.1
Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R4
R5
Uthreshold
Pins:
24
23
RSSI (0.8 - 2.8V)
+3V
OTA
VCC
Iload
LNA
Gain control
voltage
RSSI > Uthreshold: Iload=4.2µA
RSSI < Uthreshold: Iload= -1.5µA
4
Uc:< 2.6V : Gain high
Uc:> 2.6V : Gain low
UC
C
Ucmax= VCC - 0.7V
Ucmin = 1.67V
Figure 5
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to
compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold
voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately
typically 0.8 V and 2.8 V to provide a switching point within the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23). The threshold voltage can be generated by attaching a
voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output generated from
the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres
,
the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA
generates a negative current. These currents do not have the same values in order to achieve a fast-attack and
slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain
control voltage.
Data Sheet
21
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
3
2.5
2
RSSI Level
1.5
1
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
Figure 6
Typical Curve of RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the
optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8 V is apparently
a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50 µA, but that the
THRES pin input current is only in the region of 40 nA. As the current drawn out of the 3VOUT pin is directly related
to the receiver power consumption, the power divider resistors should have high impedance values. R4 can be
chosen as 120 kΩ, R5 as 180 kΩ to yield an overall 3VOUT output current of 10 µA.
Notes
1. To keep the LNA in high gain mode for the complete RF-input level range a voltage equal or higher than 3.3 V
has to be applied at pin 23. Alternatively, pin 23 has to be connected to pin 24 and pin 4 has to be connected
to GND. In addition this would save an external capacitor.
2. To keep the LNA in low gain mode for the complete RF-input level range a voltage lower than 0.7 V has to be
applied to the THRES pin (e.g. THRES connected to GND). In the above-mentioned mode pin 4 has to be
connected by a capacitor to GND.
3. As stated above, the gain control voltage of the LNA is generated at the capacitor connected to the TAGC pin
by the charging and discharging currents of the OTA. Consequently this capacitor is responsible for the AGC
time constant. As the charging and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall be chosen according to the
data rate. According to measurements performed at Infineon the capacitor value should be greater than 47 nF.
Data Sheet
22
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
4.2
Data Filter Design
Utilizing the on-board voltage follower and the two 100 kΩ on-chip resistors a 2nd order Sallen-Key low pass data
filter can be constructed by adding 2 external capacitors between pin 19 (SLP) and pin 22 (FFB) and to pin 21
(OPP) as depicted in the following figure and described in the following formulas1).
C1
22
C2
21
Pins:
19
R
R
100k
100k
Figure 7
Data Filter Design
2Q b
C1 =
(1)
(2)
R2Πf3dB
b
C2 =
4QRΠf3dB
with
b
(3)
Q =
a
the quality factor of the poles where
in case of a Bessel filter
and thus
a = 1.3617, b = 0.618
Q = 0.577
and in case of a Butterworth filter
and thus
a = 1.141, b = 1
Q = 0.71
Example
Butterworth filter with
f
3dB = 5 kHz and R = 100 kΩ
C1 = 450 pF, C2 = 225 pF
1) Taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Data Sheet 23
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
4.3
Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is
determined by the reactive part of the negative resistance of the oscillator circuit as shown in Chapter 1.1.3 and
by the quartz specifications given by the quartz manufacturer.
CS
Pin 28
Input
impedance
Crystal
Z1-28
TDA5201
Pin 1
Figure 8
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
1
CS =
(4)
1
+2π f XL
CL
with CL the load capacitance (refer to the quartz crystal specification).
Examples
5.1 MHz
CL = 12 pF
CL = 12 pF
XL = 580 Ω
XL = 870 Ω
CS = 9.8 pF
CS = 7.2 pF
10.18 MHz
These values may be obtained by putting two capacitors in series to the quartz, such as 18 pF and 22 pF in the
5.1 MHz case and 18 pF and 12 pF in the 10.2 MHz case.
But please note that the calculated value of CS includes the parasitic capacitors also.
Data Sheet
24
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
4.4
Quartz Frequency Calculation
As described in Chapter 3.4.3, the operating range of the on-chip VCO is wide enough to guarantee a receive
frequency range between 310 MHz and 350 MHz. The VCO signal is divided by 2 before applied to the mixer .
This local oscillator signal can be used to down-convert the RF signals both with high- or low-side injection at the
mixer. High-side injection of the local oscillator has to be used for receive frequencies between 310 MHz and 330
MHz. In this case the local oscillator frequency is calculated by adding the IF frequency (10.7 MHz) to the RF
frequency.
Low-side injection has to be used for receive frequencies between 330 MHz and 350 MHz. The local oscillator
frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. The overall
division ratios in the PLL are 64 or 32 depending on whether the CSEL-pin is left open or tied to ground.
Therefore, the quartz frequency may be calculated by using the following formula:
fRF −10.7
fQU
=
(5)
r
with
ƒRF
ƒLO
ƒQU
r
Receive frequency
Local oscillator (PLL) frequency (ƒRF ± 10.7)
Quartz oscillator frequency
Ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table
Table 4
CSEL
Open
PLL Division Ratio Dependence on States of CSEL
Ratio r = (ƒLO/ƒQU
)
64
32
GND
Example
Addition of 10.7 is used in case of operation the device at 315 MHz, subtraction in case of operation at 345 MHz
for instance. This yields the following frequencies:
CSEL tied to GND:
fQU
fQU
=
=
(
315MHz +10.7MHz
)
/ 32 = 10.1781 MHz
(6)
(7)
(
345MHz −10.7MHz
)
/ 32 = 10.4469 MHz
CSEL open:
fQU
fQU
=
=
(
315MHz +10.7MHz
)
/ 64 = 5.0891MHz
(8)
(9)
(
345MHz −10.7MHz
)
/ 64 = 5.2234 MHz
Data Sheet
25
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Applications
4.5
Data Slicer Threshold Generation
The threshold of the data slicer especially for a coding scheme without DC-content, can be generated in two ways,
depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as
Manchester coding the threshold can be generated using an external RC-Integrator as shown in Figure 9. The
time constant TA of the RC-Integrator has to be significantly larger than the longest period of no signal change TL
within the data sequence. In order to keep distortion low, the minimum value for R is 20 kΩ.
R
C
data out
Pins:
19
20
25
Uthreshold
data
filter
data slicer
Figure 9
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in connection with two resistors and one
capacitor as shown in the following figure. The component values are depending on the coding scheme and the
protocol used.
R
C
R
data out
Pins:
20
19
26
25
Uthreshold
peak detector
data slicer
data
filter
Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector
Data Sheet
26
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
5
Electrical Characteristics
5.1
Electrical Data
5.1.1
Absolute Maximum Ratings
Attention: The maximum ratings may not be exceeded under any circumstances, not even momentarily
and individually, as permanent damage to the IC will result.
Table 5
Absolute Maximum Ratings, Ambient Temperature TAMB = - 40 °C ... + 85 °C
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Number
Min.
-0.3
-40
Max.
5.5
Supply Voltage
Vs
V
1.1
1.2
1.3
1.4
1.5
Junction Temperature
Storage Temperature
Thermal Resistance
ESD HBM integrity, all pins
Tj
+125
+150
114
°C
°C
K/W
kV
Ts
-40
RthJA
VESD
±1,5
AEC Q100-002 /
JESD22-A114B
ESD SDM integrity, all pins
VESD
±750
V
AINSI / ESD
1.6
SP5.3.2-2008
5.1.2
Operating Range
Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits
are not guaranteed.
Supply voltage: VCC = 4.5 V ... 5.5 V
Table 6
Operating Range, Ambient Temperature TAMB = - 40 °C ... + 85 °C
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Test Number
Min.
Max.
5.2
Supply Current
IS
mA
f
RF = 315 MHz
dBm @ source
impedance 50 Ω,
2.1
Receiver Input Level
RFin
-111
-13
■
2.2
BER 2E-3,
average power
level, Manchester
encoded data rate
4 kBit, 280 kHz IF
Bandwidth
LNI Input Frequency
MI/X Input Frequency
fRF
310
310
5
350
350
23
MHz
MHz
MHz
2.3
2.4
2.5
fMI
3 dB IF Frequency
Range
fIF -3 dB
Data Sheet
27
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Table 6
Operating Range, Ambient Temperature TAMB = - 40 °C ... + 85 °C (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Test Number
Min.
0
Max.
0.8
Power Mode Off
Power Mode Off
VOFF
VON
V
V
V
2.6
2.7
2.8
2
VCC
Gain Control Voltage,
LNA high gain state
VTHRES
2.8
VCC-1
Gain Control Voltage,
LNA low gain state
VTHRES
0
0.7
V
2.9
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production.
Table 7
AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Test Number
Min.
Max.
Supply Current
Supply current
standby mode
IS PDWN
IS
50
70
5
nA
Pin 27 (PDWN)
open or tied to 0 V
3.1
3.2
Supply current
4.6
mA
LNA - Signal Input LNI (PIN 3), VTHRES > 3.3 V, High Gain Mode
Average Power Level
at BER = 2E-3
(Sensitivity)
RFin
-113
dBm Manchester
encodeddatarate
■
3.3
4 kBit, 280 kHz IF
Bandwidth
Input impedance
S11 LNA
0.895 /
-25.5 deg
■
■
■
■
3.4
3.5
3.6
3.7
f
RF = 315 MHz
Input level @ 1 dB C.P. P1dBLNA
RF = 315 MHz
-14
dBm
f
Input 3rd order intercept IIP3LNA
point fRF = 315 MHz
-10
dBm fin = 315 MHz &
317 MHz
LO signal feedthrough at LOLNI
-119
dBm
antenna port
LNA - Signal Output LNO (PIN 6), VTHRES > 3.3 V, High Gain Mode
Gain fRF = 315 MHz
S21 LNA
1.577 /
150.3 deg
■
■
■
3.8
Output impedance,
S22 LNA
0.897 /
-10.3 deg
3.9
f
RF = 315 MHz
Voltage Gain Antenna to GAntMI
21
dB
3.10
MI fRF = 315 MHz
Data Sheet
28
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Table 7
AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note /
Test Condition
Test Number
Min.
Max.
Noise Figure
NFLNA
2
dB
Excluding
■
3.11
matching network
loss see Appendix
LNA - Signal Input LNI, VTHRES = GND, Low Gain Mode
Input impedance
RF = 315 MHz
Input level @ 1 dB C. P. P1dBLNA
RF = 315 MHz
S11 LNA
0.918 /
-25.2 deg
■
■
3.12
3.13
3.14
f
-7
dBm Matched input
f
Input 3rd order intercept IIP3LNA
-13
dBm fin = 315 MHz and ■
point fRF = 315 MHz
317 MHz
LNA - Signal Output LNO, VTHRES = GND, Low Gain Mode
Gain fRF = 315 MHz
S21 LNA
0.007 /
153.7 deg
■
3.15
3.16
3.17
Output impedance
,fRF = 315 MHz
S22 LNA
0.907 /
-10.5 deg
■
Voltage Gain Antenna to GAntMI
MI fRF = 315 MHz
2
dB
AGC - Signal 3VOUT (PIN 24)
Output voltage
Current out
V3VOUT
I3VOUT
3
V
3.18
3.19
50
µA
AGC - Signal THRES (PIN 23)
Input Voltage range
LNA low gain mode
LNA high gain mode
VTHRES
VTHRES
VTHRES
0
VCC-1
VCC-11)
V
V
V
See chapter 4.1
3.20
3.21
3.22
0
3.31)
Voltage must not
be higher than
VCC-1 V
Current in
ITHRES_in
5
nA
■
3.23
AGC - Signal TAGC (PIN 4)
Current out,
LNA low gain state
ITAGC_out
4.2
1.5
µA
µA
RSSI > VTHRES
RSSI < VTHRES
3.24
3.25
Current in,
ITAGC_in
LNA high gain state
MIXER - Signal Input MI/MIX (PINS 8/9)
Input impedance
RF = 315 MHz
S11 MIX
0.954 /
-10.9 deg
■
■
3.26
3.27
f
Input 3rd order intercept IIP3MIX
-25
dBm
point
MIXER - Signal Output IFO (PIN 12)
Output impedance
ZIFO
330
Ω
3.28
Data Sheet
29
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Table 7
AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Symbol Values Unit Note /
Test Condition
Parameter
Test Number
Min.
Typ.
Max.
Conversion Voltage Gain GMIX
RF = 315 MHz
+21
dB
dB
dB
3.29
f
Noise Figure, SSB
(~DSB NF + 3 dB)
NFMIX
13
■
■
3.30
3.31
RF to IF isolation
ARF-IF
46
LIMITER - Signal Input LIM/LIMX (PINS 17/18)
Input Impedance
RSSI dynamic range
RSSI linearity
ZLIM
264
60
330
396
80
Ω
■
3.32
3.33
3.34
3.35
DRRSSI
LINRSSI
fLIM
dB
dB
MHz
±1
■
■
Operating frequency
(3 dB points)
5
10.7
23
DATA FILTER
Useable bandwidth
BWBB FILT
100
kHz
V
■
3.36
3.37
RSSI Level at Data Filter RSSIlow
1.1
LNA in high gain
Output SLP
RFIN = -103 dBm
RSSI Level at Data Filter RSSIhigh
2.65
V
LNA in high gain
3.38
Output SLP
RFIN = -30 dBm
SLICER - Signal Output DATA (PIN 25)
Useable bandwidth
BWBB SLIC
Cmax SLIC
100
20
kHz
pF
■
3.39
3.40
Capacitive loading of
output
LOW output voltage
HIGH output voltage
VSLIC_L
VSLIC_H
0
V
3.41
3.42
VCC-1.3 VCC-1
VCC-0.7 V
Output current
= 200 µA
Output current
ISLIC_out
200
µA
3.43
PEAK DETECTOR - Signal Output PDO (PIN 26)
LOW output voltage
HIGH output voltage
Load current
VSLIC_L
VSLIC_H
Iload
0
V
3.44
3.45
3.46
VCC-1
V
-500
µA
Staticloadcurrent
must not exceed
-500 µA
Leakage current
Ileakage
700
nA
3.47
3.48
CRYSTAL OSCILLATOR - Signals CRST1, CRST2, (PINS 1/28)
Operating frequency
fCRSTL
5
11
MHz Fundamental
mode, series
resonance
Input Impedance
@ ~5 MHz
Z1-28
Z1-28
-760
+ j580
Ω
Ω
■
■
3.49
3.50
Input Impedance
@ ~10 MHz
-600
+ j870
Data Sheet
30
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Table 7
AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Symbol Values Unit Note /
Test Condition
Parameter
Test Number
Min.
Typ.
Max.
Serial Capacity
@ ~5 MHz
C
S5 = C1
9.3
pF
3.51
3.52
Serial Capacity
@ ~10 MHz
CS10 = C1
6.4
pF
PLL - Signal LF (PIN 15)
Tuning voltage relative to VTUNE
0.4
1.6
2.4
V
3.53
VCC
POWER DOWN MODE - Signal PDWN (PIN 27)
Power Mode On
Power Mode Off
VON
VOff
2.8
0
VCC
V
3.54
3.55
3.56
3.57
0.8
V
Input bias current PDWN IPDWN
19
1
µA
ms
Start-up Time until valid TSU
IF signal is detected
Depends on the
used crystal
PLL DIVIDER - Signal CSEL (PIN 16)
f
f
CRSTL range 5.xx MHz
VCSEL
1.4
0
42)
V
or open
3.58
3.59
3.60
CRSTL range 10.xx MHz VCSEL
0.2
V
Input bias current CSEL ICSEL
5
µA
CSEL tied to GND
1) See Chapter 4.1, Choice of LNA Threshold Voltage and Time Constant
2) Maximum voltage in Power-On state is 4 V, but in PDWN-state the maximum voltage is 2.8 V.
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Data Sheet
31
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
5.2
Test Board
Test Circuit
5.2.1
The device performance parameters marked with ■ in Chapter 5.1.3 are not subject to production test. They were
verified by design/characterization.
Figure 11 Schematic of the Evaluation Board
Data Sheet
32
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
5.2.2
Test Board Layouts
Figure 12 Top Side of the Evaluation Board
Figure 13 Bottom Side of the Evaluation Board
Data Sheet
33
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Figure 14 Component Placement on the Evaluation Board
Data Sheet
34
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
5.2.3
Bill of Materials
The following components are necessary for evaluation of the TDA5201 at 315 MHz without use of a Microchip
HCS515 decoder.
Table 8
Ref
R1
Bill of Materials
Value
Specification
100 kΩ
100 kΩ
820 kΩ
120 kΩ
180 kΩ
10 kΩ
0805, ±5 %
R2
0805, ±5 %
R3
0805, ±5 %
R4
0805, ±5 %
R5
0805, ±5 %
R6
0805, ±5 %
L1
15 nH
Toko, PTL2012-F15N0G
0805,COG, ±2 %
0805, COG, ±0.1 pF
0805, COG, ±0.1 pF
0805, COG, ±0.1 pF
0805, COG, ±5 %
1206, X7R, ±10 %
Toko, PTL2012-F15N0G
0805, COG, ±5 %
0805, COG, ±5 %
0805, COG, ±5 %
0805, X7R, ±10 %
0805, X7R, ±10 %
0805, COG, ±5 %
0805, X7R, ±10 %
0805, COG, ±5 %
0805, X7R, ±10 %
0805, COG, ±0.1 pF
0805, COG, ±2 %
L2
12 pF
C1
3.3 pF
10 pF
C2
C3
6.8 pF
100 pF
47 nF
C4
C5
C6
15 nH
C7
100 pF
33 pF
C8
C9
100 pF
10 nF
C10
C11
C12
C13
C14
C15
C16
C17
Q2
10 nF
220 pF
47 nF
470 pF
47 nF
18 pF
12 pF
(315 + 10.7 MHz)/32
HC49/U, fundamental mode, CL = 12 pF,
315 MHz: Jauch Q 10.17813-S11-1323-12-10/20
F1
SFE10.7MA5-A
142-0701-801
Murata
X2, X3
Johnson
X1, X4, S1, S5
2-pole pin connector
3-pole pin connector, or not equipped
Infineon
S4
IC1
TDA5201
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5201
in conjunction with a Microchip HCS515 decoder.
Data Sheet
35
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Electrical Characteristics
Table 9
Ref
Bill of Materials Addendum
Value
Specification
0805, ±5 %
0805, ±5 %
0805, ±5 %
0805, ±5 %
0805, ±5 %
R21
R22
R23
R24
R25
C21
C22
IC2
22 kΩ
100 kΩ
22 kΩ
820 kΩ
560 kΩ
100 nF
100 nF
HCS515
BC 847B
LS T670-JL
1206, X7R, ±10 %
1206, X7R, ±10 %
Microchip
T1
Infineon
D1
Infineon
Data Sheet
36
Revision 1.6, 2010-12-21
TDA 5201
ASK Single Conversion Receiver
Appendix - Noise Figure and Gain Circles
Appendix - Noise Figure and Gain Circles
The following gain and noise figure circles were measured utilizing Microlab Stub Stretchers and a HP8514
network analyzer. Maximum gain is shown at point 1 at 18.5 dB, minimum noise figure is 1.9 dB at point 2, step
size of circles is 0.5 dB.
Figure 15 Gain and Noise Circles of the TDA5201 at 315 MHz
Data Sheet
37
Revision 1.6, 2010-12-21
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Published by Infineon Technologies AG
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