TDA5200_10_技术文档

TDA 5200

ASK Single Conversion Receiver

Version 3.0

Data Sheet

Revision 3.0, 2010-12-28

Wireless Components

Edition 2010-12-28

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

TDA 5200

ASK Single Conversion Receiver

Revision History

Page or Item

Subjects (major changes since previous revision)

Previous Revision: 2.9

Revision 3.0, 2010-12-28

all

Converted into structured FrameMaker (EDD 3.4)

More detailed explanation of AGC

More detailed information of LNA high gain mode and LNA low gain mode

4-3

5-6, 5-8

Trademarks of Infineon Technologies AG

AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,

CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,

EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,

MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,

PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,

SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,

TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,

PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR

development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,

FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.

FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of

Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data

Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of

MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics

Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™

of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,

OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.

RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.

SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden

Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.

UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™

of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of

Diodes Zetex Limited.

Last Trademarks Update 2010-10-26

Data Sheet

3

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Product Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1

2

Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

2.3

2.4

3

3.1

3.2

3.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

3.4.9

4

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1

4.2

4.3

4.4

4.5

5

5.1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Test Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.1.1

5.1.2

5.1.3

5.2

5.2.1

5.2.2

5.2.3

Data Sheet

4

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

PG-TSSOP-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PG-TSSOP-28 Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Typical Curve of RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . 23

Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . . . . . . . . . 25

Data Slicer Threshold Generation with External R-C Integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11 Schematic of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 12 Top Side of the Evaluation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Sheet

5

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

List of Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table 9

Table 10

Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Absolute Maximum Ratings, Ambient Temperature T_AMB= - 40 °C ... + 85 °C . . . . . . . . . . . . . . . 28

Operating Range, Ambient Temperature T_AMB= - 40 °C ... + 85 °C . . . . . . . . . . . . . . . . . . . . . . . 29

AC/DC Characteristics with T_AMB= 25 °C, V_CC= 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Bill of Materials Addendum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Data Sheet

6

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Product Info

1

Product Info

General Description

The IC is a very low power consumption single chip ASK Single Conversion Receiver for receive frequencies

bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a

PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a

peak detector. Additionally there is a power down feature to save battery life.

Features

•

Low supply current (I_s= 4.8 mA typ. at 868 MHz, I_s= 4.6 mA typ. at 434 MHz)

Supply voltage range 5 V ±10 %

Power down mode with very low supply current (50 nA typ)

Fully integrated VCO and PLL Synthesizer

RF input sensitivity < – 107 dBm

Selectable frequency ranges around 868-870 MHz and 433-435 MHz

Selectable reference frequency

Limiter with RSSI generation, operating at 10.7 MHz

2^ndorder low pass data filter with external capacitors

Data slicer with self-adjusting threshold

Application

•

Keyless Entry Systems

Remote Control Systems

Alarm Systems

Low Bitrate Communication Systems

Package

Figure 1

PG-TSSOP-28

Ordering Information

Type

Ordering Code

Package¹⁾

TDA5200

SP000016381

PG-TSSOP-28

1) Available on tape and reel

Data Sheet

7

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Product Description

2

Product Description

2.1

Overview

The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency

bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external

components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a

PLL synthesizer, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a

peak detector. Additionally there is a power down feature to save battery life.

2.2

Application

•

Keyless Entry Systems

Remote Control Systems

Alarm Systems

Low Bitrate Communication Systems

2.3

Features

•

Low supply current (I_s= 4.8 mA typ. at 868 MHz, I_s= 4.6 mA typ. at 434 MHz)

Supply voltage range 5 V ±10 %

Power down mode with very low supply current (100 nA typ.)

Fully integrated VCO and PLL Synthesizer

RF input sensitivity < – 107 dBm

Selectable receive frequency bands 868-870 MHz and 433-435 MHz

Selectable reference frequency

Limiter with RSSI generation, operating at 10.7 MHz

2^ndorder low pass data filter with external capacitors

Data slicer with self-adjusting threshold

Data Sheet

8

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Product Description

2.4

Package Outlines

Figure 2

PG-TSSOP-28 Package Outlines

Data Sheet

9

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

3

Functional Description

3.1

Pin Configuration

CRST1

VCC

LNI

1

2

3

4

5

6

7

8

9

28 CRST2

27 PDWN

26 PDO

25 DATA

24 3VOUT

23 THRES

22 FFB

TAGC

AGND

LNO

VCC

MI

TDA 5200

21 OPP

20 SLN

MIX

AGND 10

FSEL 11

IFO 12

19 SLP

18 LIMX

17 LIM

DGND 13

VDD 14

16 CSEL

15 LF

Figure 3

IC Pin Configuration

Data Sheet

10

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

3.2

Pin Definition and Function

Table 1

Pin Definition and Function

Pin Name

No.

Type

Buffer Type

Function

1

CRST1

In/Out

External Crystal Connector 1

4.15V

1

50uA

2

3

VCC

LNI

In

5 V Supply

LNA Input

57uA

3

500uA

4k

1k

Data Sheet

11

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

4

TAGC

In/Out

AGC Time Constant Control

4.3V

4.2uA

1.5uA

4

1k

1.7V

5

6

AGND

LNO

In

Analogue Ground Return

LNA Output

Out

5V

1k

6

7

8

VCC

MI

In

5 V Supply

Mixer Input

1.7V

2k

8

9

400uA

Data Sheet

12

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

9

MIX

In

Complementary Mixer Input

1.7V

2k

8

9

400uA

10

11

AGND

FSEL

In

Analogue Ground Return

Operating Frequency

Selector

869/434 MHz

750

1.2V

2k

11

12

IFO

Out

IF Mixer Output

10.7 MHz

300uA

2.2V

60

12

4.5k

13

14

DGND

VDD

In

Digital Ground Return

5 V Supply

PLL Counter Circuitry

Data Sheet

13

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

15

LF

In/Out

PLL Filter Access Point

5V

4.6V

30uA

200

100

15

30uA

2.4V

16

CSEL

In

Quartz Selector

6.xx MHz or 13.xx MHz

1.2V

80k

16

17

LIM

In

Limiter Input

2.4V

15k

17

75uA

330

15k

18

Data Sheet

14

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

18

LIMX

In

Complementary Limiter Input

2.4V

15k

17

75uA

330

15k

18

19

SLP

In

Data Slicer Positive Input

15uA

100

3k

19

40uA

20

SLN

In

Data Slicer Negative Input

5uA

10k

20

21

OPP

In

OpAmp Noninverting Input

5uA

200

21

Data Sheet

15

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

22

FFB

In

Data Filter Feedback Pin

5uA

100k

22

23

THRES

In

AGC Threshold Input

5uA

10k

23

24

3VOUT

Out

3 V Reference Output

24

3V

25

DATA

Out

Data Output

200

25

80k

26

PDO

Out

Peak Detector Output

200

26

Data Sheet

16

Revision 3.0, 2010-12-28

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ASK Single Conversion Receiver

Functional Description

Table 1

Pin Definition and Function (cont’d)

Pin Name

No.

Type

Buffer Type

Function

27

PDWN

In

Power Down Input

27

220k

28

CRST2

In/Out

External Crystal Connector 2

4.15V

28

50uA

Data Sheet

17

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Functional Description

3.3

Functional Block Diagram

V_CC

IF

Filter

LNO

6

MI MIX IFO

LIM

17

LIMX

18

FFB

22

OPP

21

SLP

19

SLN

20

9

8

12

25

DATA

3

RF

LNA

RSSI

SLICER

PDO

26

23

4

TAGC

THRES

3VOUT

AGC

Reference

24

TDA 5200

14

VDD

U_REF

Φ

Crystal

OSC

: 1/2

VCO

: 128/64

DET

DGND 13

Bandgap

Reference

Loop

Filter

2/7

VCC

5/10

AGND

28

11

FSEL

15

LF

16

1

27

CSEL

PDWN

Crystal

Figure 4

Main Block Diagram

Data Sheet

18

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Functional Description

3.4

Functional Blocks

3.4.1

Low Noise Amplifier (LNA)

The LNA is an on-chip cascode amplifier with a voltage gain of 15 dB to 20 dB. The gain figure is determined by

the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer

Inputs MI and MIX (Pin 8 and Pin 9). The noise figure of the LNA is approximately 3.2 dB, the current consumption

is 500 µA. The gain can be reduced by approximately 18 dB. The switching point of this AGC action can be

determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared

internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is

higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated

by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output

generated from the internal bandgap voltage and the THRES pin as described in Chapter 4.1. The time constant

of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen

along with the appropriate threshold voltage according to the intended operating case and interference scenario

to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described

in Chapter 4.1.

3.4.2

Mixer

The Double Balanced Mixer down-converts the input frequency (RF) in the range of 433-435 MHz / 868-870 MHz

to the intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 21 dB. A low pass filter with a

corner frequency of 20 MHz is built on chip in order to suppress RF signals to appear at the IF output (IFO pin).

The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 Ω

to facilitate interfacing the pin directly to a standard 10.7 MHz ceramic filter without additional matching circuitry.

3.4.3

PLL Synthesizer

The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with

charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor

diodes. It’s nominal centre frequency is 840 MHz. No additional components are necessary.

Local oscillator high side injection has to be used for receive frequencies below approximately 420 MHz or

840 MHz, low side injection for receive frequencies above approximately 420 MHz or 840 MHz - see also

Chapter 4.4. Therefore low-side injection of the local oscillator has to be used for operation both in the 868 MHz

and the 434 MHz ISM bands.

The oscillator signal is fed both to the synthesizer divider chain and to the down-converting mixer. In case of

operation in the 433-435 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled by

the selection pin FSEL (Pin 11) as described in the following table. The overall division ratio of the divider chain

can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below).

The loop filter is also realized fully on-chip.

Table 2

FSEL

FSEL Pin Operating States

RF Frequency

433-435 MHz

868-870 MHz

Open

Shorted to ground

Data Sheet

19

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Functional Description

3.4.4

Crystal Oscillator

The on-chip crystal oscillator circuitry allows for utilization of quartzes both in the 6 MHz and 13 MHz range as the

overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16) pin according to the

following table.

Table 3

CSEL

Open

CSEL Pin Operating States

Crystal Frequency

6.xx MHz

Shorted to ground

13.xx MHz

The calculation of the value of the necessary quartz load capacitance is shown in Chapter 4.3, the quartz

frequency calculation is explained in Chapter 4.4.

3.4.5

Limiter

The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a

bandpass-characteristic centered around 10.7 MHz. It has an input impedance of 330 Ω to allow for easy

interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI)

generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in

Figure 6. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to

turn down the LNA gain by approximately 17 dB in case the input signal strength is too strong as described in

Chapter 3.4.1 and Chapter 4.1.

3.4.6

Data Filter

The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 kΩ on-

chip resistors. Along with two external capacitors a 2^ndorder Sallen-Key low pass filter is formed. The selection of

the capacitor values is described in Chapter 4.2.

3.4.7

Data Slicer

The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of

approximately 120 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the

local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like

levels) for the detector. The self-adjusting threshold on pin 20 is generated by RC-term or peak detector

depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in

more detail in Chapter 4.5.

3.4.8

Peak Detector

The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An

external RC network is necessary. The output can be used as an indicator for the signal strength and also as a

reference for the data slicer. The maximum output current is 500 µA.

3.4.9

Bandgap Reference Circuitry

A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode

is available to switch off all sub-circuits which is controlled by the PWDN pin (Pin 27) as shown in the following

table. The supply current drawn in this case is typically 50 nA.

Data Sheet

20

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Functional Description

Table 4

PDWN

PDWN Pin Operating States

Operating State

Open or tied to ground

Power Down Mode

Receiver On

Tied to V_CC

Data Sheet

21

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Applications

4

Applications

4.1

Choice of LNA Threshold Voltage and Time Constant

In the following figure the internal circuitry of the LNA automatic gain control is shown.

R4

R5

U_threshold

Pins:

24

23

RSSI (0.8 - 2.8V)

+3V

OTA

V_CC

I_load

LNA

Gain control

voltage

RSSI > U_threshold: I_load=4.2µA

RSSI < U_threshold: I_load= -1.5µA

4

U_c:< 2.6V : Gain high

U_c:> 2.6V : Gain low

U_C

C

U_cmax= V_CC- 0.7V

U_cmin= 1.67V

Figure 5

LNA Automatic Gain Control Circuitry

The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to

compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold

voltage U_thres. As shown in the following figure the threshold voltage can have any value between approximately

typically 0.8 V and 2.8 V to provide a switching point within the receive signal dynamic range.

This voltage U_thresis applied to the THRES pin (Pin 23). The threshold voltage can be generated by attaching a

voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output generated from

the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than U_thres

,

the OTA generates a positive current I_load. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA

generates a negative current. These currents do not have the same values in order to achieve a fast-attack and

slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain

control voltage.

Data Sheet

22

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Applications

3

2.5

2

RSSI Level

1.5

1

0.5

0

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

Input Level at LNA Input [dBm]

Figure 6

Typical Curve of RSSI Level and Permissive AGC Threshold Levels

The switching point should be chosen according to the intended operating scenario. The determination of the

optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8 V is apparently

a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50 µA, but that the

THRES pin input current is only in the region of 40 nA. As the current drawn out of the 3VOUT pin is directly related

to the receiver power consumption, the power divider resistors should have high impedance values. R4 can be

chosen as 120 kΩ, R5 as 180 kΩ to yield an overall 3VOUT output current of 10 µA.

Notes

1. To keep the LNA in high gain mode for the complete RF-input level range a voltage equal or higher than 3.3 V

has to be applied at pin 23. Alternatively, pin 23 has to be connected to pin 24 and pin 4 has to be connected

to GND. In addition this would save an external capacitor.

2. To keep the LNA in low gain mode for the complete RF-input level range a voltage lower than 0.7 V has to be

applied to the THRES pin (e.g. THRES connected to GND). In the above-mentioned mode pin 4 has to be

connected by a capacitor to GND.

3. As stated above, the gain control voltage of the LNA is generated at the capacitor connected to the TAGC pin

by the charging and discharging currents of the OTA. Consequently this capacitor is responsible for the AGC

time constant. As the charging and discharging currents are not equal two different time constants will result.

The time constant corresponding to the charging process of the capacitor shall be chosen according to the

data rate. According to measurements performed at Infineon the capacitor value should be greater than 47 nF.

Data Sheet

23

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Applications

4.2

Data Filter Design

Utilizing the on-board voltage follower and the two 100 kΩ on-chip resistors a 2^ndorder Sallen-Key low pass data

filter can be constructed by adding 2 external capacitors between pin 19 (SLP) and pin 22 (FFB) and to pin 21

(OPP) as depicted in the following figure and described in the following formulas¹⁾.

C₁

22

C₂

21

Pins:

19

R

100k

Figure 7

Data Filter Design

2Q b

C1 =

(1)

(2)

R2Πf_3dB

b

C2 =

4QRΠf_3dB

with

b

(3)

Q =

a

the quality factor of the poles where

in case of a Bessel filter

and thus

a = 1.3617, b = 0.618

Q = 0.577

and in case of a Butterworth filter

and thus

a = 1.141, b = 1

Q = 0.71

Example

Butterworth filter with

f

_3dB= 5 kHz and R = 100 kΩ

C₁= 450 pF, C₂= 225 pF

1) Taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999

Data Sheet 24

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Applications

4.3

Quartz Load Capacitance Calculation

The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is

determined by the reactive part of the negative resistance of the oscillator circuit as shown in Chapter 5.1.3 and

by the quartz specifications given by the quartz manufacturer.

C_S

Pin 28

Input

impedance

Crystal

Z_1-28

TDA5200

Pin 1

Figure 8

Determination of Series Capacitance Value for the Quartz Oscillator

Crystal specified with load capacitance

1

C_S=

(4)

1

+2π f X_L

C_L

with C_Lthe load capacitance (refer to the quartz crystal specification).

Examples

6.7 MHz

C_L= 12 pF

X_L= 750 Ω

C_S= 8.7 pF

C_S= 5.3 pF

13.401 MHz

X_L= 1250 Ω

These values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 20 pF

and 15 pF in the 6.7 MHz case and 15 pF and 8.2 pF in the 13.401 MHz case.

But please note that the calculated value of C_Sincludes the parasitic capacitors also.

Data Sheet

25

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Applications

4.4

Quartz Frequency Calculation

As described in Chapter 3.4.3, the operating range of the on-chip VCO is 820 MHz to 860 MHz with a nominal

center frequency of approximately 840 MHz. This signal is divided by 2 before applied to the mixer in case of

operation at 434 MHz. This local oscillator signal can be used to down-convert the RF signals both with high- or

low-side injection at the mixer. The resulting receive frequency ranges then extend between 810 MHz and

870 MHz or between 400 MHz and 440 MHz. Low-side injection of the local oscillator has to be used for receive

frequencies between 840 MHz and 870 MHz as well as high-side injection for receive frequencies below 840 MHz.

Corresponding to that in the 400 MHz region low-side injection is applicable for receive frequencies above

420 MHz, high-side injection below this frequency. Therefore for operation both in the 868 MHz and the 434 MHz

ISM bands low-side injection of the local oscillator has to be used. Then the local oscillator frequency is calculated

by subtracting the IF frequency (10.7 MHz) from the RF frequency (434 MHz or 868 MHz). The overall division

ratios in the PLL are 64 or 128 in case of operation at 868 MHz or 32 and 64 in case of operation at 434 MHz,

depending on the crystal frequency used as shown below.

Therefore, the quartz frequency is calculated by using the following formula:

f_RF±10.7

f_QU

=

(5)

r

with

ƒ_RF

ƒ_LO

ƒ_QU

r

Receive frequency

Local oscillator (PLL) frequency (ƒ_RF± 10.7)

Quartz oscillator frequency

Ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table

Table 5

FSEL

Open

GND

PLL Division Ratio Dependence on States of CSEL

CSEL

Open

GND

Open

GND

Ratio r = (ƒ_LO/ƒ_QU)

64

32

128

64

GND

Subtraction of 10.7 occurs in case the receive frequency is higher than the intended local oscillator frequency,

addition in case the receive frequency lies below the local oscillator frequency.

Example

f_QU

=

(

868.4MHz −10.7MHz

434.2MHz −10.7MHz

)

/64 = 13.40156MHz

/128 = 6.7008 MHz

/32 = 13.23437MHz

(6)

(7)

(8)

(

)

=

(

)

Data Sheet

26

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Applications

4.5

Data Slicer Threshold Generation

The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In

case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated

using an external RC-Integrator as shown in Figure 9. The time constant T_Aof the RC-Integrator has to be

significantly larger than the longest period of no signal change T_Lwithin the data sequence. In order to keep

distortion low, the minimum value for R is 20 kΩ.

R

C

data out

Pins:

19

20

25

U_threshold

data

filter

data slicer

Figure 9

Data Slicer Threshold Generation with External R-C Integrator

Another possibility for threshold generation is to use the peak detector in connection with two resistors and one

capacitor as shown in the following figure. The component values are depending on the coding scheme and the

protocol used.

R

C

R

data out

Pins:

20

19

26

25

U_threshold

peak detector

data slicer

data

filter

Figure 10 Data Slicer Threshold Generation Utilizing the Peak Detector

Data Sheet

27

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Electrical Characteristics

5

Electrical Characteristics

5.1

Electrical Data

5.1.1

Absolute Maximum Ratings

Attention: The maximum ratings may not be exceeded under any circumstances, not even momentarily

and individually, as permanent damage to the IC will result.

Table 6

Absolute Maximum Ratings, Ambient Temperature T_AMB= - 40 °C ... + 85 °C

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Number

Min.

-0.3

-40

Max.

5.5

Supply Voltage

V_CC

T_j

V

1.1

1.2

1.3

1.4

1.5

Junction Temperature

Storage Temperature

Thermal Resistance

ESD HBM integrity, all pins

+125

+150

114

°C

K/W

kV

T_s

-40

R_thJA

V_ESD

±1,5

AEC Q100-002 /

JESD22-A114B

ESD SDM integrity, all pins

V_ESD

±750

V

AINSI / ESD

1.6

SP5.3.2-2008

Data Sheet

28

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Electrical Characteristics

5.1.2

Operating Range

Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits

are not guaranteed.

Supply voltage: V_CC= 4.5 V ... 5.5 V

Table 7

Operating Range, Ambient Temperature T_AMB= - 40 °C ... + 85 °C

Parameter

Symbol

Values

Typ. Max.

5.6

Unit Note /

Test Condition

Test Number

Min.

Supply Current

I_{S 868}

I_{S 434}

RF_in

mA

f

_RF= 868 MHz

_RF= 434 MHz

2.1

2.2

5.4

Receiver Input Level

-107

-13

dBm @ source impedance ■

50 Ω, BER 2E-3,

average power level,

Manchester encoded

data rate 4 kBit,

2.3

280 kHz IF

Bandwidth

LNI Input Frequency

MI/X Input Frequency

f_RF

433

868

433

868

5

435

870

435

870

23

MHz

2.4

2.5

2.6

2.7

2.8

f_RF

f_MI

3 dB IF Frequency

Range

f_{IF -3 dB}

Power Down Mode On PWDN_ON

Power Down Mode Off PWDN_OFF

0

0.8

V

2.9

2

V_CC

2.10

2.11

Gain Control Voltage,

LNA high gain state

V_THRES

2.8

V_CC-1

Gain Control Voltage,

LNA low gain state

V_THRES

0

0.7

V

2.12

Attention: Test ■ means that the parameter is not subject to production test.

It was verified by design/characterization.

Data Sheet

29

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Electrical Characteristics

5.1.3

AC/DC Characteristics

AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient

temperature range. Typical characteristics are the median of the production. The device performance parameters

marked with ■ are not subject to production test. They were verified by design/characterization.

Table 8

AC/DC Characteristics with T_AMB= 25 °C, V_CC= 4.5 ... 5.5 V

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Test Number

Min.

Max.

Supply Current

Supply current

standby mode

I_{S PDWN}

I_{S 868}

50

70

5.2

5

nA

Pin 27 (PDWN)

open or tied to 0 V

3.1

3.2

3.3

Supply current, device

operating at 868 MHz

4.8

4.6

mA

Pin11(FSEL)tied

to GND

Supply current, device

operating at 434 MHz

I_{S 434}

Pin 11 (FSEL)

open

LNA - Signal Input LNI (PIN 3), V_THRES> 3.3 V, High Gain Mode

Average Power Level

at BER = 2E-3

(Sensitivity)

RF_in

-110

dBm Manchester

encodeddatarate

■

3.4

4 kBit, 280 kHz IF

Bandwidth

Input impedance

S_{11 LNA}

0.873 /

-34.7 deg

■

3.5

3.6

3.7

3.8

3.9

3.10

f

_RF= 434 MHz

Input impedance

_RF= 868 MHz

S_{11 LNA}

0.738 /

-73.5 deg

f

Input level @ 1 dB

compression

P1dB_LNA

-10

-14

dBm

Input 3rd order intercept IIP3_LNA

point f_RF= 434 MHz

dBm Matched input

dBm

Input 3rd order intercept IIP3_LNA

point f_RF= 868 MHz

LO signal feedthrough at LO_LNI

-73

antenna port

LNA - Signal Output LNO (PIN 6), V_THRES> 3.3 V, High Gain Mode

Gain f_RF= 434 MHz

Gain f_RF= 868 MHz

Output impedance,

S_{21 LNA}

S_{22 LNA}

1.509 /

138.2 deg

■

3.11

3.12

3.13

3.14

1.419 /

101.7 deg

0.886 /

-12.9 deg

f

_RF= 434 MHz

Output impedance,

_RF= 868 MHz

0.866 /

-24.2 deg

f

LNA - Signal Input LNI, V_THRES= GND, Low Gain Mode

Input impedance

_RF= 434 MHz

S_{11 LNA}

0.873 /

-34.7 deg

■

3.15

f

Data Sheet

30

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Electrical Characteristics

Table 8

AC/DC Characteristics with T_AMB= 25 °C, V_CC= 4.5 ... 5.5 V (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Test Number

Min.

Max.

Input impedance

S_{11 LNA}

0.738 /

-73.5 deg

■

3.16

3.17

3.18

3.19

3.20

f

_RF= 868 MHz

Input level @ 1 dB C. P. P1dB_LNA

_RF= 434 MHz

Input level @ 1 dB C. P. P1dB_LNA

_RF= 868 MHz

-18

dBm Matched input

f

-6

f

Input 3^rdorder intercept IIP3_LNA

point f_RF= 434 MHz

Input 3^rdorder intercept IIP3_LNA

point f_RF= 868 MHz

-10

-5

LNA - Signal Output LNO, V_THRES= GND, Low Gain Mode

Gain f_RF= 434 MHz

S_{21 LNA}

S_{22 LNA}

0.183 /

140.6 deg

■

3.21

3.22

3.23

3.24

Gain f_RF= 868 MHz

0.179 /

109.1 deg

Output impedance

,f_RF= 434 MHz

0.897 /

-13.6 deg

Output impedance

0.868 /

,f_RF= 868 MHz

-26.3 deg

LNA - Antenna to IFO, V_THRES> 3.3 V, High Gain Mode

Voltage Gain Antenna to G_AntMixerOut

Mixer-Out (IFO)

42

dB

3.25

3.26

f

_RF= 434 MHz

Voltage Gain Antenna to G_AntMixerOut

40

Mixer-Out (IFO)

f

_RF= 868 MHz

LNA - Antenna to IFO, V_THRES= GND, Low Gain Mode

Voltage Gain Antenna to G_AntMixerOut

Mixer-Out (IFO)

22

19

dB

3.27

3.28

f

_RF= 434 MHz

Voltage Gain Antenna to G_AntMixerOut

Mixer-Out (IFO)

f

_RF= 868 MHz

AGC - Signal 3VOUT (PIN 24)

Output voltage

Current out

V_3VOUT

I_3VOUT

3

V

At 5 µA

3.29

3.30

50

µA

AGC - Signal THRES (PIN 23)

Input Voltage range

LNA low gain mode

V_THRES

0

V_CC-1

V

See chapter 4.1

3.31

3.32

Data Sheet

31

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Electrical Characteristics

Table 8

AC/DC Characteristics with T_AMB= 25 °C, V_CC= 4.5 ... 5.5 V (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Test Number

Min.

Max.

LNA high gain mode

V_THRES

3.3¹⁾

V_CC-1¹⁾

V

Voltage must not

be higher than

V_CC-1 V

3.33

Current in

I_{THRES_in}

5

nA

■

3.34

AGC - Signal TAGC (PIN 4)

Current out,

LNA low gain state

I_{TAGC_out}

4.2

1.5

µA

RSSI > V_THRES

RSSI < V_THRES

3.35

3.36

Current in,

I_{TAGC_in}

LNA high gain state

MIXER - Signal Input MI/MIX (PINS 8/9)

Input impedance

_RF= 434 MHz

Input impedance

_RF= 868 MHz

Input 3^rdorder intercept IIP3_MIX

point f_RF= 434 MHz

S_{11 MIX}

0.942 /

-14.4 deg

■

3.37

3.38

3.39

3.40

f

S_{11 MIX}

0.918 /

-28.1 deg

f

-28

dBm

Input 3^rdorder intercept IIP3_MIX

point f_RF= 868 MHz

-26

MIXER - Signal Output IFO (PIN 12)

Output impedance

Conversion Voltage Gain G_MIX

_RF= 434 MHz

Conversion Voltage Gain G_MIX

_RF= 868 MHz

LIMITER - Signal Input LIM/LIMX (PINS 17/18)

Z_IFO

330

Ω

3.41

3.42

+19

dB

f

+18

dB

3.43

f

Input Impedance

RSSI dynamic range

RSSI linearity

Z_LIM

264

60

330

396

80

Ω

■

3.44

3.45

3.46

3.47

DR_RSSI

LIN_RSSI

f_LIM

dB

MHz

±1

■

Operating frequency

(3 dB points)

5

10.7

23

DATA FILTER

Useable bandwidth

BW_{BB FILT}

100

kHz

V

■

3.48

3.49

RSSI Level at Data Filter RSSI_low

Output SLP

1.1

LNA in high gain

RF_IN= -103 dBm

868 MHz

RSSI Level at Data Filter RSSI_high

Output SLP

2.65

V

LNA in high gain

RF_IN= -30 dBm

868 MHz

3.50

3.51

SLICER - Signal Output DATA (PIN 25)

Useable bandwidth

BW_{BB SLIC}

100

kHz

■

Data Sheet

32

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

Table 8

AC/DC Characteristics with T_AMB= 25 °C, V_CC= 4.5 ... 5.5 V (cont’d)

Parameter

Symbol

Values

Typ.

Unit Note /

Test Condition

Test Number

Min.

Max.

Capacitive loading of

output

C_{max SLIC}

20

pF

3.52

LOW output voltage

HIGH output voltage

V_{SLIC_L}

V_{SLIC_H}

0

V

3.53

3.54

V_CC-1.3 V_CC-1

V_CC-0.7 V

Output current

= 200 µA

Output current

I_{SLIC_out}

200

µA

3.55

PEAK DETECTOR - Signal Output PDO (PIN 26)

LOW output voltage

HIGH output voltage

Load current

V_{SLIC_L}

V_{SLIC_H}

I_load

0

V

3.56

3.57

3.58

V_CC-1

V

-500

µA

Staticloadcurrent

must not exceed

-500 µA

Leakage current

I_leakage

700

nA

3.59

3.60

CRYSTAL OSCILLATOR - Signals CRST1, CRST2, (PINS 1/28)

Operating frequency

f_CRSTL

6

14

MHz Fundamental

mode, series

resonance

Input Impedance

@ ~6 MHz

Z_1-28

-900

+ j750

Ω

■

3.61

3.62

3.63

3.64

Input Impedance

@ ~13 MHz

-450

+ j1250

Ω

Serial Capacity

@ ~6 MHz

C

_S6= C1

_S13= C1

8.7

pF

Serial Capacity

@ ~13 MHz

C

5.3

PLL - Signal LF (PIN 15)

Tuning voltage relative to V_TUNE

0.4

1.6

2.4

V

3.65

V_CC

POWER DOWN MODE - Signal PDWN (PIN 27)

Power Mode On

Power Mode Off

V_ON

2.8

0

V_CC

V

3.66

3.67

3.68

3.69

V_PWDN

0.8

V

Input bias current PDWN I_PDWN

19

<1

µA

Start-up Time until valid T_SU

IF signal is detected

ms

Depends on the

used crystal

PLL DIVIDER - Signal CSEL (PIN 16)

f

_CRSTLrange 6.xx MHz

V_CSEL

1.4

0

4²⁾

V

Or open

3.70

3.71

3.72

_CRSTLrange 13.xx MHz V_CSEL

0.2

V

Input bias current CSEL I_CSEL

5

µA

CSEL tied to GND

1) See Chapter 4.1 Choice of LNA Threshold Voltage and Time Constant.

2) Maximum voltage in Power-On state is 4 V, but in PDWN-state the maximum voltage is 2.8 V.

Data Sheet

33

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

5.2

Test Board

Test Circuit

5.2.1

The device performance parameters marked with ■ in Chapter 5.1.3 are not subject to production test. They were

verified by design/characterization.

Figure 11 Schematic of the Evaluation Board

Data Sheet

34

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

5.2.2

Test Board Layouts

Figure 12 Top Side of the Evaluation Board

Figure 13 Bottom Side of the Evaluation Board

Data Sheet

35

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

Figure 14 Component Placement on the Evaluation Board

Data Sheet

36

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

5.2.3

Bill of Materials

The following components are necessary for evaluation of the TDA5200 without use of a Microchip HCS515

decoder.

Table 9

Ref

R1

Bill of Materials

Value

Specification

0805, ± 5 %

100 kΩ

R2

100 kΩ

R3

820 kΩ

R4

120 kΩ

R5

180 kΩ

R6

10 kΩ

L1

434 MHz: 15 nH

868 MHz: 3.3 nH

Toko, PTL2012-F15N0G

Toko, PTL2012-F3N3C

L2

434 MHz: 8.2 pF

868 MHz: 3.9 nH

0805, COG, ± 0.1 pF

Toko, PTL2012-F3N9C

C1

C2

1 pF

0805, COG, ± 0.1 pF

434 MHz: 4.7 pF

868 MHz: 3.9 pF

0805, COG, ± 0.1 pF

C3

434 MHz: 6.8 pF

868 MHz: 5.6 pF

0805, COG, ± 0.1 pF

C4

C5

C6

100 pF

47 nF

0805, COG, ± 5 %

1206, X7R, ± 10 %

434 MHz: 10 nH

868 MHz: 3.9 pF

Toko, PTL2012-F10N0G

0805, COG, ± 0.1 pF

C7

C8

100 pF

0805, COG, ± 5 %

434 MHz: 33 pF

868 MHz: 22 pF

0805, COG, ± 5 %

C9

100 pF

10 nF

220 pF

47 nF

470 pF

47 nF

15 pF

8.2 pF

0805, COG, ± 5 %

0805, X7R, ± 10 %

0805, COG, ± 5 %

0805, X7R, ± 10 %

0805, COG, ± 5 %

0805, X7R, ± 5 %

0805, COG, ± 1 %

C10

C11

C12

C13

C14

C15

C16

C17

Q2

(fRF – 10.7 MHz)/32 or

(fRF – 10.7 MHz)/64

HC49/U, fundamental mode, CL = 12 pF,

e.g. 434.2 MHz: Jauch Q 13,23437-S11-1323-12-10/20

e.g. 868.4 MHz: Jauch Q 13,40155-S11-1323-12-10/20

F1

SFE10.7MA5-A or

SKM107M1-A20-10

Murata

Toko

X2, X3

Data Sheet

142-0701-801

Johnson

37

Revision 3.0, 2010-12-28

TDA 5200

ASK Single Conversion Receiver

Electrical Characteristics

Table 9

Ref

Bill of Materials

Value

Specification

X1, X4, S1, S5

2-pole pin connector

S4

3-pole pin connector, or not equipped

Infineon

IC1

TDA 5200

Please note that in case of operation at 434 MHz a capacitor has to be soldered in place of L2 and an inductor in

place of C6.

The following components are necessary in addition to the above mentioned ones for evaluation of the TDA 5200

in conjunction with a Microchip HCS515 decoder.

Table 10

Ref

Bill of Materials Addendum

Value

Specification

0805, ± 5 %

1206, X7R, ± 10 %

Microchip

R21

R22

R23

R24

R25

C21

C22

IC2

22 kΩ

100 kΩ

22 kΩ

820 kΩ

560 kΩ

100 nF

HCS515

BC 847B

LS T670-JL

T1

Infineon

D1

Infineon

Data Sheet

38

Revision 3.0, 2010-12-28

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	TDA5200_10
厂家：	Infineon
描述：	ASK Single Conversion Receiver ASK单转换接收器
文件：	总39页 (文件大小：1575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TDA5200_10 [INFINEON]

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