TDA8023TT [NXP]
Low power IC card interface; 低功耗IC卡接口
| 型号： | TDA8023TT |
| 厂家： | 
NXP |
| 描述： | Low power IC card interface |
| 文件： | 总32页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA8023
Low power IC card interface
Rev. 01 — 16 July 2007
Product data sheet
1. General description
The TDA8023 is a complete cost-efficient, low-power analog interface for synchronous or
asynchronous smart cards. It can be placed between the card and the microcontroller with
very few external components to perform all supply, protection and control functions.
2. Features
I I2C-bus controlled IC card interface in TSSOP28
I Supply voltage from 2.7 V to 6.5 V
I Independant supply voltage VDD(INTF) for interface signals with the microcontroller
I Shutdown input for very low power consumption when the part is not used
I Power reduction modes when the card is active
I DC-to-DC converter for VCC generation (capacitive doubler, tripler, or inductive, or
follower automatically selected according to supply voltage and card voltage)
I 1 specific protected half duplex bidirectional buffered I/O line, with current limitation at
±15 mA, maximum frequency 1 MHz
I 2 auxiliary card I/O lines controlled by I2C-bus (C4 and C8)
I VCC regulation: 5 V, 3 V or 1.8 V ± 8 %, ICC < 55 mA, current spikes of 40 nAs up to
20 MHz, with controlled rise and fall times, filtered overload detection approximately
80 mA, current limitation about 120 mA
I Thermal and short-circuit protections on all card contacts
I Automatic activation and deactivation sequences: initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, VDD or VDD(DCDC) drop-out
I Enhanced ElectroStatic Discharge (ESD) protection on card side (> 6 kV)
I 20 MHz clock input
I Clock generation for the card up to 10 MHz (CLKIN divided by 1, 2, 4 or 5) with
synchronous frequency changes; stop HIGH or LOW or free running 1 MHz in cards
Low-power mode; current limitation on pin CLK (C3)
I RST signal (C2) with current limitation at 20 mA, controlled by an embedded
programmable CLK pulse counter on asynchronous cards or by a register on
synchronous cards
I ISO 7816-3, GSM 11.11 and EMV 2000 (payment systems) compatibility
I Supply voltage supervisor for spike killing during power-on and emergency
deactivation at power-off: threshold internally fixed or set via an external resistor
bridge; pulse width internally fixed or set via an external capacitor
I Card presence input with 10 ms built-in debouncing system
I One interrupt signal INT
TDA8023
NXP Semiconductors
Low power IC card interface
3. Applications
I Banking terminals
I Internet terminals
I Set-top boxes
I Portable IC card readers
4. Quick reference data
Table 1.
Quick reference data
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
on pin VDD
2.7
2.7
-
-
6.5
6.5
V
V
VDD(DCDC) DC-to-DC converter
supply voltage
on pin VDDP
VDD(INTF)
IDD
interface supply voltage on pin VDDI
supply current Shutdown mode
1.5
-
-
-
6.5
10
V
[1]
[1]
[1]
-
-
µA
µA
Inactive mode; CLKIN LOW or HIGH
Active mode; VCC = 5 V; fCLK = 5 MHz
capacitive; ICC = 5 mA
200
-
-
-
-
-
-
-
-
-
-
15
200
15
150
2
mA
mA
mA
mA
mA
capacitive; ICC = 55 mA
inductive; ICC = 5 mA
inductive; ICC = 55 mA
[1]
[3]
Power-down mode; VCC = 5 V; ICC = 100 µA;
CLK stopped; CLKIN HIGH or LOW;
capacitive or inductive
[2]
Supply voltage for the card: pin VCC
VCC supply voltage
Active mode; 2.7 V < VDD < 6.5 V
5 V card; ICC < 60 mA; VCC = 5 V
3 V card; ICC < 55 mA; VCC = 3 V
1.8 V card; ICC < 30 mA; VCC = 1.8 V
4.75
2.80
1.65
5
5.25
3.15
1.95
V
V
V
3
1.8
[3]
Active mode; AC current pulses with
I < 200 mA, t < 400 ns and f < 20 MHz
5 V card; current pulses of 40 nAs
3 V card; current pulses of 24 nAs
1.8 V card; current pulses of 15 nAs
on VCC; 20 kHz to 200 MHz
4.65
2.76
1.62
-
-
-
-
-
5.35
3.24
1.98
350
V
V
V
Vripple(p-p) peak-to-peak ripple
voltage
mV
ICC
supply current
VDD > 2.7 V
5 V card; VCC = 0 V to 5 V
3 V card; VCC = 0 V to 3 V
1.8 V card; VCC = 0 V to 1.8 V
-
-
-
-
-
-
−55
−55
−35
mA
mA
mA
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
2 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 1.
Quick reference data …continued
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
General
tdeact
Parameter
Conditions
Min
Typ
Max
Unit
deactivation time
total sequence
60
-
80
-
100
500
+85
µs
Ptot
total power dissipation Tamb = −25 °C to +85 °C
mW
°C
Tamb
ambient temperature
−40
-
[1] Sum of currents on pins VDD and VDDI
.
[2] Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet
these specifications.
[3] Output voltage towards the card, including ripple.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDA8023TT
TSSOP28
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
6. Block diagram
optional
100 nF
1 µF
100 nF
100 nF
external
resistor
bridge
V
V
DDP
DD
SBP SBM SAM SAP
27 25 23 28
22
26
R2
PORADJ 20
CDEL 21
24 GNDP
R1
SUPPLY
SUPERVISOR
DC-TO-DC CONVERTER
C
VUP
1
CDEL
GND 10
100 nF
TDA8023
17
4
V
CC
V
DDI
100 nF
3
SDWN
SDA
5
18
16
14
13
12
19
15
RST
6
SCL
CLK
I/O
SEQUENCER
9
2
CLKIN
I/OUC
INT
I C-BUS
CARD
DRIVERS
11
2
INTERFACE
CLOCK
COUNTER
C4
C8
8
SPRES
SAD0
PRES
GNDC
7
001aag336
Fig 1. Block diagram with capacitive DC-to-DC converter
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
3 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
optional
external
resistor
bridge
LX
100 nF
6.8 µH
10 µF
V
V
DDP
DD
SBP SBM SAM SAP
27 25 23 28
22
26
R2
PORADJ 20
CDEL 21
24 GNDP
R1
SUPPLY
SUPERVISOR
DC-TO-DC CONVERTER
C
VUP
1
CDEL
GND 10
100 nF
4.7 µF
TDA8023
17
4
V
CC
100 nF
V
DDI
3
SDWN
SDA
5
18
16
14
13
12
19
15
RST
6
SCL
CLK
I/O
SEQUENCER
9
2
CLKIN
I/OUC
INT
I C-BUS
CARD
DRIVERS
11
2
INTERFACE
CLOCK
COUNTER
C4
C8
8
SPRES
SAD0
PRES
GNDC
7
001aag337
Fig 2. Block diagram with inductive DC-to-DC converter
7. Pinning information
7.1 Pinning
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VUP
INT
SAP
SBP
3
SDWN
V
DDP
4
V
SBM
DDI
5
SDA
SCL
GNDP
SAM
6
7
SAD0
SPRES
CLKIN
GND
I/OUC
C8
V
DD
TDA8023TT
8
CDEL
9
PORADJ
PRES
RST
10
11
12
13
14
V
CC
C4
CLK
I/O
GNDC
001aag338
Fig 3. Pin configuration TDA8023TT
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
4 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
7.2 Pin description
Table 3.
Symbol
VUP
Pin description
Pin
1
Type[1] Description
O
O
output of the DC-to-DC converter
INT
2
Negative-channel Metal Oxide Semiconductor (NMOS) interrupt
to the host (active LOW and open-drain) (see fault detection in
Section 8.7 “Protection”)
SDWN
VDDI
3
I
shutdown and reset input
4
S
interface positive supply voltage
SDA
5
I/O
serial data line to/from the I2C-bus master (open-drain)
serial clock line from the I2C-bus master
I2C-bus address selection
SCL
6
I
SAD0
SPRES
CLKIN
GND
I/OUC
C8
7
I
8
I
select PRES mode[2]
9
I
external clock input
10
11
12
13
14
15
16
17
18
19
20
S
I/O[3]
I/O[4]
I/O[4]
ground connection
data in/out from/to microcontroller
auxiliary input/output to/from the card (contact C8)
auxiliary input/output to/from the card (contact C4)
data input/output to/from (contact C7 of) the card
ground connection for the card (contact C5)
clock output to (contact C3 of) the card
supply voltage for the card (contact C1)
reset output to (contact C2 of) the card
card presence input with a 10 ms built-in debouncing system[2]
C4
I/O
I/O[4]
GNDC
CLK
S
O
S
O
I
VCC
RST
PRES
PORADJ
I
input for changing the power-on reset threshold with an external
resistor bridge.
In case no external resistor bridge is used, it is mandatory to
connect this pin to GND to avoid possible perturbations.
CDEL
21
C
delay capacitor connection for the voltage supervisor (1 ms per
2 nF)
VDD
22
23
24
25
26
27
28
S
C
S
C
S
C
C
power supply
SAM
GNDP
SBM
VDDP
SBP
SAP
connection for the DC-to-DC converter
ground connection for the DC-to-DC converter
connection for the DC-to-DC converter
positive supply for the DC-to-DC converter
connection for the DC-to-DC converter
connection for the DC-to-DC converter
[1] I = input, O = output, S = supply, C = configuration.
[2] PRES is active-HIGH when SPRES = LOW and PRES is active-LOW when SPRES = HIGH.
[3] With integrated pull-up to VDD(INTF)
.
[4] With integrated pull-up to VCC
.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
5 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
8. Functional description
Remark: Throughout this document, it is assumed that the reader is familiar with
ISO 7816 and EMV 2000 terminology.
8.1 Power supplies
The supply pins for the TDA8023 are VDD and GND. VDD should be in the range from
2.7 V to 6.5 V. The supply voltages VDD, VDD(INTF) and VDD(DCDC) may be applied to the
TDA8023 in any time sequence.
All interface signals with the system controller are referenced to a separate supply voltage
VDD(INTF) on pin VDDI, that may be lower or higher than VDD
.
For generating a supply voltage VCC of 5 V ± 5 % or 3 V ± 5 % used by the card, an
integrated DC-to-DC converter is incorporated. This DC-to-DC converter should be
separately supplied by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V).
The I2C-bus signals SDA and SCL may be externally referenced to a voltage higher than
VDD
.
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply voltage. It is used as Power-On Reset
(POR) and as supply dropout detection during a card session. Supply dropout detection
ensures that a proper deactivation sequence is followed before the voltage is too low. A
reset pulse of duration tW (see Figure 4) is used internally for maintaining the TDA8023 in
the Inactive mode during powering up or powering down of VDD
.
As long as VDD is less than Vth(POR)H the TDA8023 will remain inactive whatever the levels
on the command lines are. This also lasts for the duration of tW after VDD has reached a
level higher than Vth(POR)H. When VDD falls below Vth(POR)L an automatic deactivation
sequence of the contacts is performed.
In this case (no external resistor bridge) it is mandatory to connect pin PORADJ to GND.
power on
shutdown mode
power off
V
V
th(POR)H
th(POR)L
V
DD
V
hys(POR)
status read
status read
INT
t
t
W
W
SDWN
bus unresponsive
bus unresponsive
bus unresponsive
001aag339
Fig 4. Voltage supervisor and Shutdown mode
Rev. 01 — 16 July 2007
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
6 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
8.2.2 With external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 to GND and R2 to VDD as
shown in Figure 1 and Figure 2), then the internal threshold voltages and the internal
hysteresis voltage are overridden by externally determined ones.
The voltage on pin PORADJ is:
R1
R1 + R2
VPORADJ
where
k =
=
× V
= k × VDD
DD
-------------------
R1
--------------------
R1 + R2
The thresholds that are applied by the TDA8023 to this voltage VPORADJ are:
Vhys
Vth(H)(PORADJ) = Vbg(int)
+
(rising)
(falling)
----------
2
Vhys
Vth(L)(PORADJ) = Vbg(int)
where
–
----------
2
V
bg(int) = 1.25 V (typ)
Vhys = 60 mV (typ)
The thresholds and hysteresis on VDD can then be calculated from:
Vhys
Vbg(int)
+
----------
Vth(H)(PORADJ)
2
Vth(POR)H
=
=
(rising)
(falling)
-------------------------------------
-----------------------------------------
k
k
Vhys
Vbg(int)
–
----------
Vth(L)(PORADJ)
2
Vth(POR)L
=
=
------------------------------------
----------------------------------------
k
k
Vhys
Vhys(POR)
=
----------
k
The minimum threshold voltage Vth(POR)L should be chosen higher than 2 V.
Input PORADJ is biased internally with a pull-down current source of 4 µA which is cut
when the voltage on this pin exceeds 1 V. This ensures that after detection of the external
bridge during power-on, the input current on this pin does not cause inaccuracy of the
bridge voltage.
8.2.3 External capacitor on pin CDEL
The width of the POR pulse (tW) is externally set by the value of the CDEL capacitor: the
typical value is 1 ms per 2 nF. Usually CCDEL = 22 nF, therefore tW = 10 ms (typ).
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
7 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
8.2.4 Shutdown mode
When pin SDWN = HIGH, the TDA8023 is in Shutdown mode; the consumption in this
mode is less than 10 µA. The I2C-bus is unresponsive.
If the card is extracted or inserted when the TDA8023 is in Power-down mode, pin INT
becomes LOW and stays LOW as long as pin SDWN = HIGH.
When pin SDWN is pulled LOW, the TDA8023 leaves Shutdown mode and executes a
complete power-on reset sequence.
8.3 I2C-bus
A 400 kHz I2C-bus slave interface is used for configuring the TDA8023 and reading the
status.
8.3.1 I2C-bus protocol
The I2C-bus is for 2-way 2-line communication between ICs or modules. The serial bus
consists of two bidirectional lines: one for data signals (SDA) and one for clock signals
(SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor.
The following protocol has been defined:
• Data transfer may be initiated only when the bus is not busy
• During data transfer, the data line must remain stable whenever the clock line is
HIGH; changes in the data line while the clock line is HIGH will be interpreted as
control signals
8.3.2 Bus conditions
The following bus conditions have been defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line from HIGH to LOW, while the
clock is HIGH, defines the START condition.
Stop data transfer — A change in the state of the data line from LOW to HIGH, while the
clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock signal.
There is one clock pulse per bit of data.
8.3.3 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition (see Figure 7). See Table 15 for timing information.
Data transfer is unlimited in the Read mode. The information is transmitted in bytes and
each receiver acknowledges with a 9th bit.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
8 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Within the I2C-bus specifications, a Standard mode (100 kHz clock rate) and a Fast-speed
mode (400 kHz clock rate) are defined. The TDA8023 operates in both Fast-speed and
Standard modes.
By definition, a device that sends a signal is called a transmitter and a device that receives
the signal is called a receiver. The device that controls the signal is called the master. The
devices that are controlled by the master are called slaves.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put
on the bus by the transmitter. The master generates an extra acknowledge-related clock
pulse. The slave receiver that is addressed is obliged to generate an acknowledge after
the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge-related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end
of data to the slave transmitter by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter must leave the data line HIGH
to enable the master generation of the STOP condition.
8.3.4 Device addressing
Each TDA8023 has 2 different addresses, one for each of its two registers.
Two TDA8023s may be used in parallel due to the address selection pin SAD0. Pin SAD0
is externally hardwired to pin VDD or pin GND. The voltage on pin SAD0 sets address bit
b2: HIGH sets bit b2 to logic 1, LOW resets b2 to logic 0.
Address bit b1 selects Register 0 or Register 1.
Address bit b0 defines Read or Write operation: 1 means Read, 0 means Write.
The addresses for the TDA8023 are shown in Table 4 and Table 5.
Table 4.
Device addressing
b7
b6
b5
b4
b3
b2
b1
b0
0
1
0
0
0
SAD0
0/1
R/W
Table 5.
I2C-bus addresses for write mode
Pin SAD0
Register 0
40h
Register 1
42h
L
H
44h
46h
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
9 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
8.3.5 Registers
Table 6.
Bit
Table of registers
Register 0
Register 1
Read/Write mode
REG1 = 0
REG0 = 0
TEST
Read mode
Status
Write mode
Command
REG1 = 1
REG0 = 1
D7
REG0 = 0
C15
C14
C13
C12
C11
C10
C9
REG0 = 1
C7
7
6
5
4
3
2
1
0
ACTIVE
EARLY
MUTE
PROT
VCC1V8
I/OEN
RSTIN
D6
C6
REG1
C8
D5
C5
REG0
C4
D4
C4
SUPL
PDWN
5V/3VN
WARM
START
CLKPD2
CLKPD1
CLKDIV2
CLKDIV1
D3
C3
CLKSW
PRESL
PRES
D2
C2
D1
C1
D0
C8
C0
Table 7.
Status - Register 0 in Read mode bit description
Bit
7
Symbol
ACTIVE
EARLY
Description
set if the card is active; reset if the card is inactive
6
set during Answer To Reset (ATR) when the selected card has answered
too early
5
4
3
2
1
0
MUTE
PROT
SUPL
set during ATR when the card has not answered during the ISO 7816
time slots
set when an overload or an overheating has occurred during a session;
reset when the status has been read
set when the voltage supervisor has signalled a fault; reset when the
status has been read
CLKSW
PRESL
PRES
set when the TDA8023 is in Power-down mode and the clock has
changed
set when the card has been inserted or extracted; reset when the status
has been read
set when the card is present; reset when the card is not present
When at least one of the bits PRESL, PROT, MUTE and EARLY is set, pin INT goes LOW
until the status byte has been read. After power-on, bit SUPL is set until the status byte
has been read, and pin INT = LOW until the voltage supervisor becomes inactive.
Table 8.
Command - Register 0 in Write mode bit description
Bit
Symbol
Description
7
VCC1V8
1: VCC = 1.8 V
0: VCC is defined by bit 5V/3VN
this bit can not change if bit START is logic 1
1: signal on pin I/OUC is transferred to pin I/O
0: pin I/OUC and pin I/O are high-impedance
selection of subaddress in Register 1 (see Table 9, 10, 11 and 12)
6
I/OEN
5 and 4 REG[1:0]
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
10 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 8.
Command - Register 0 in Write mode bit description …continued
Bit
Symbol
Description
3
PDWN
1: applies on pin CLK the frequency that is defined by bits CLKPD[2:1]
and reduces power consumption (in Synchronous mode); this bit can not
change if bit START is logic 1
2
5V/3VN
1: VCC = 5 V
0: VCC = 3 V
this bit can not change if bit START is logic 1
1: initiates a warm reset procedure
1
0
WARM
START
this bit will be automatically reset by hardware when bit MUTE is set to
logic 1
1: initiates an activation sequence and a cold reset procedure (only if bit
SUPL = 0 and the bit PRES = 1)
0: initiates a deactivation sequence
Table 9.
R1_00 - Register 1 subaddress 00 in Read/Write mode bit description
Bit
Symbol
Description
7
TEST
1: the circuit is in Test mode
0: the circuit is in Operational mode
6
5
4
RSTIN[1]
C8
defines the voltage on pin RST:
1: VCC
0: 0 V
defines the voltage on pin C8:
1: VCC
0: 0 V
C4
defines the voltage on pin C4:
1: VCC
0: 0 V
3 and 2 CLKPD[2:1] clock pulse definition:
00: CLK stop LOW
01: CLK stop HIGH
10: frequency on pin CLK: fCLK = fosc(int) / 2
11: no change
in Synchronous mode bit CLKPD2 is always logic 0 by hardware and bit
CLKPD1 controls the voltage on pin CLK:
1: VCC
0: 0 V
1 and 0 CLKDIV[2:1] clock divider:
00: fCLK = fCLKIN
01: fCLK = fCLKIN / 2
10: fCLK = fCLKIN / 4
11: fCLK = fCLKIN / 5
in Synchronous mode, bits CLKDIV[2:1] are always 00 by hardware
[1] Synchronous or asynchronous cards management are defined when bit START is set: the TDA8023 will be
in asynchronous cards management when bit RSTIN = 1 when bit START is set to logic 1.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
11 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 10. R1_01 - Register 1 subaddress 01 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0
D[7:0]
8-bit programmable CLK period count register;
range: 0 to 255;
initial value: 170
Table 11. R1_10 - Register 1 subaddress 10 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0
C[15:8]
8-bit programmable CLK period count register;
range in combination with C[7:0]: 0 to 65535;
initial value: 164
Table 12. R1_11 - Register 1 subaddress 11 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0
C[7:0]
8-bit programmable CLK period count register;
range in combination with C[15:8]: 0 to 65535;
initial value: 116
If bit RSTIN = 0 when bit START is set to logic 1, then pin RST is controlled by bit RSTIN.
Else, pin RST = LOW during a number of CLK periods, defined by the 16-bit CLK count
register C[15:0], and goes HIGH afterwards.
There are two synchronous card management types:
• If bit PDWN = 0 when bit START is set to logic 1, then the output CLK is controlled by
input CLKIN (without division)
• If bit PDWN = 1 when bit START is set to logic 1, then the output CLK is controlled by
bit CLKPD1
8.4 DC-to-DC converter
For generating a supply voltage VCC of 5 V ± 5 % or 3 V ± 5 % to the card, an integrated
voltage converter is incorporated. This DC-to-DC converter should be separately supplied
by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V).
The DC-to-DC conversion is either capacitive or inductive, according to the external
components (automatic detection).
8.4.1 Capacitive configuration
The external components are three 100 nF capacitors (low-ESR), see Figure 1.
The DC-to-DC converter is either tripler, doubler or follower according to the respective
values of VCC and VDD(DCDC). An hysteresis of 100 mV is present on both thresholds:
• Follower:
– If VCC = 5 V and VDD(DCDC) > 5.8 V
– If VCC = 3 V and VDD(DCDC) > 4 V
– If VCC = 1.8 V
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
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TDA8023
NXP Semiconductors
Low power IC card interface
• Doubler:
– If VCC = 5 V and VDD(DCDC) = 4 V to 5.8 V
– If VCC = 3 V and VDD(DCDC) < 4 V
• Tripler:
– If VCC = 5 V and VDD(DCDC) < 4 V
8.4.2 Inductive configuration
The external components are a diode, a coil of 6.8 µH and a capacitor of 4.7 µF (see
Figure 2). In this configuration the DC-to-DC converter acts as follows.
• If VCC = 5 V then VVUP is regulated at 5.5 V
• If VCC = 3 V then VVUP is regulated at 4 V
• If VCC = 1.8 V then the DC-to-DC converter acts as a follower
8.5 VCC buffer
In all modes (follower, doubler, tripler), the DC-to-DC converter is able to deliver 60 mA
over the whole VDD range (2.7 V to 6.5 V) or 90 mA if VDD > 3 V.
The current on the VCC buffer has an internal limitation of around 90 mA. When this limit is
reached, an automatic deactivation sequence is performed.
The VCC voltage should be decoupled with a low-ESR capacitor between 100 nF and
168 nF. If the card socket is not very close to the TDA8023, one capacitor should be
placed near the TDA8023, and a second one near the card contacts.
8.6 Sequencer and clock counter
The sequencer takes care of ensuring activation and deactivation sequences according to
ISO 7816 and EMV 2000, even in case of emergency (card removal during transaction,
supply dropout or hardware problem).
The sequencer is clocked with an internal oscillator.
The activation of a card is initiated by setting bit START in the Command register, which is
only possible if the card is present and if the voltage supervisor is not active. The
activation sequence is described in Section 8.6.1.
The deactivation is initiated either by the system controller or automatically in case of a
hardware problem or a supply dropout. The deactivation sequence is described in
Section 8.6.2.
Outside a session, card contacts are forced low-impedance with respect to pin GNDC.
8.6.1 Activation sequence
When the card is inactive, pins VCC, CLK, RST and I/O are LOW, which is low-impedance
with respect to pin GNDC. The DC-to-DC converter is stopped.
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Product data sheet
Rev. 01 — 16 July 2007
13 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
When everything is satisfactorily present (voltage supply, card present, no hardware
problems) the system controller may initiate an activation sequence of a present card:
1. The internal oscillator changes to its high frequency (t0, see Figure 5).
2. The DC-to-DC converter is started (t1).
3. VCC starts rising from 0 V to 5 V, 3 V or 1.8 V with a controlled rise time (t2).
4. The voltage on pin I/O rises to VCC, due to integrated 14 kΩ pull-ups to VCC (t3).
5. CLK is sent to the card and pin RST is enabled (t4 = tact).
During the activation sequence, the answer from the card (ATR) is monitored and the
steps are the following:
1. If a start bit is detected on pin I/O during the first 200 CLK pulses, then it is simply
ignored, and the CLK count goes on.
2. If a start bit is detected whilst pin RST = LOW (between 200 and 42100 CLK pulses or
the value written in C[15:0]), then the bits EARLY and MUTE are set in the Status
register. Pin RST will remain LOW. It is up to the software to decide whether to accept
the card or not.
3. If no start bit has been detected within 42100 CLK pulses, then pin RST is toggled to
HIGH (t5).
4. If, again, a start bit is detected within 370 CLK pulses (200 + 170 or the value defined
in D[7:0]), bit EARLY in the Status register is set.
5. If the card does not answer within 42100 new CLK pulses, then bit MUTE in the
Status register is set.
6. If the card answers within the correct time window, then the CLK count is stopped and
the system controller can send commands to the card.
f osc(int)
The sequencer is clocked by
which leads to a time interval T = 25 µs (typical).
-------------------
64
T
64
3T
2
7T
2
Thus t1 = 0 s to
, t = t +
, t = t +
and t4 = t1 + 4T .
------
-----
------
2
3
1
1
START
VUP
V
CC
I/O
CLK
RST
t
t
t
t
t
t
5
ATR
0
1
2
3
4
001aag340
t
act
Fig 5. Activation sequence
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
14 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
8.6.2 Deactivation sequence
When the session is completed, the microcontroller resets bit START to logic 0 (t10, see
Figure 6). The circuit then executes an automatic deactivation sequence:
1. Card reset: pin RST falls to LOW (t11).
2. CLK is stopped (t12).
3. Pin I/O falls to 0 V (t13).
4. Pin VCC falls to 0 V with a controlled slew rate (t14).
5. The DC-to-DC converter is stopped and pins CLK, RST, VCC and I/O become
low-impedance with relation to GNDC (t15).
6. The internal oscillator changes to its low frequency (t15).
T
T
---
2
3T
------
2
7T
------
2
t11 = t10
+
, t = t
+
, t = t + T , t14 = t +
11
and t15 = t11
+
.
-----
64
12
13
11
11
The deactivation time tdeact is the time that VCC needs for going down to less than 0.4 V,
counted from the moment bit START is reset.
START
RST
CLK
I/O
V
CC
VUP
t
t
t
t
t
t
15
001aag619
10
11
12
13
14
t
deact
Fig 6. Deactivation sequence
8.7 Protection
All card contacts are protected against any short with any other card contact.
The currents on various pins are limited:
• on pin CLK: limited to ±70 mA
• on pin I/O: limited to ±10 mA (typical value)
• on pin RST: limited (only when this pin is LOW) to ±20 mA
• on pin VCC: limited to 90 mA
If any of these currents exceeds its limit, an emergency deactivation sequence is
performed: pin INT is pulled LOW and bit PROT in the Status register is set.
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
15 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
In case of overcurrent on pin VCC, removal of the card during a session, overheating,
supply dropout, DC-to-DC out of limits, or overcurrent on pin RST, the TDA8023 performs
an automatic emergency deactivation sequence on the card, resets bit START and pulls
pin INT LOW.
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
on pin VDD
on pin VDDP
Min
−0.5
−0.5
Max
+6.5
+6.5
Unit
V
VDD
supply voltage
VDD(DCDC) DC-to-DC converter
supply voltage
V
VDD(INTF)
VIH
interface supply voltage on pin VDDI
HIGH-level input voltage on pins SAP, SAM, SBP, SBM, VUP
on pins SDA, SCL
−0.5
−0.5
−0.5
−0.5
-
+6.5
+7.5
+6.5
V
V
V
on all other pins
VDD + 0.5 V
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
Tamb = −25 °C to +85 °C
500
mW
−55
-
+150
150
°C
°C
[1]
Vesd
electrostatic discharge
voltage
Human Body Model (HBM)
on card pins I/O, VCC, CLK, GNDC, PRES, RST
on all other pins
−6
−2
+6
+2
kV
kV
Machine Model (MM)
all pins, excluding card pins
−200
+200
V
[1] Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM;
1500 Ω; 100 pF) defines 3 pulses positive and 3 pulses negative on each pin referenced to ground.
10. Thermal characteristics
Table 14. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
in free air
100
K/W
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
16 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
11. Characteristics
Table 15. Supply
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
VDD
Parameter
Conditions
on pin VDD
on pin VDDP
Min
2.7
2.7
Typ
Max Unit
supply voltage
-
-
6.5
6.5
V
V
VDD(DCDC)
DC-to-DC converter
supply voltage
VDD(INTF)
IDD
interface supply voltage
supply current
on pin VDDI
1.5
-
-
-
6.5
10
V
[1]
[1]
[1]
Shutdown mode
-
-
µA
µA
Inactive mode; CLKIN LOW or HIGH
Active mode; VCC = 5 V; fCLK = 5 MHz
capacitive; ICC = 5 mA
capacitive; ICC = 55 mA
inductive; ICC = 5 mA
200
-
-
-
-
-
-
-
-
-
-
15
200
15
mA
mA
mA
mA
mA
inductive; ICC = 55 mA
150
2
[1]
Power-down mode; VCC = 5 V; ICC = 100 µA;
CLK stopped; CLKIN HIGH or LOW;
capacitive or inductive
IDD(INTF)
Vth(POR)L
interface supply current
on pin VDDI
-
-
-
120
µA
LOW-level power-on reset decreasing voltage on pin VDD; see Figure 4
threshold voltage
2.30
2.60
V
Vhys(POR)
power-on reset hysteresis on pin VDD; see Figure 4
voltage
50
-
150
mV
[1] Sum of currents on pins VDD and VDDI
.
Table 16. Supply supervisor
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pin PORADJ
Vth(H)(PORADJ)
HIGH-level threshold voltage rising voltage;
1.25 1.28 1.31
1.19 1.22 1.25
V
on pin PORADJ
see Section 8.2.2
Vth(L)(PORADJ)
LOW-level threshold voltage
on pin PORADJ
falling voltage;
see Section 8.2.2
V
Vhys
∆Vth/∆T
IL
hysteresis voltage
V
th(H)(PORADJ) − Vth(L)(PORADJ)
;
30
-
60
-
90
mV
mV/°C
see Section 8.2.2
threshold voltage variation
with temperature
on Vth(H)(PORADJ)
and Vth(L)(PORADJ)
0.25
leakage current
VPORADJ < 0.6 V
VPORADJ > 0.8 V
0
4
-
10
+1
µA
µA
−1
Pin CDEL
VCDEL
voltage on pin CDEL
current on pin CDEL
-
-
-
-
-
VDD + 0.3
V
ICDEL
pin grounded (charge)
VCDEL = VDD (discharge)
internal alarm pulse;
−2
−5
10
0
-
µA
mA
ms
tW
pulse width
-
C
CDEL = 22 nF
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
17 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 17. DC-to-DC converter
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
fosc(int)
VVUP
Parameter
Conditions
Min
2
Typ
Max Unit
internal oscillator frequency
voltage on pin VUP
2.5
3
MHz
V
5 V card
5.3
3.5
-
5.5
5.8
4.2
-
3 V card
4
V
1.8 V card
VDD(DCDC)
V
Vdet
detection voltage
on pin VDDP
5 V card; Follower mode
3 V card; Follower mode
5 V card; Tripler mode
5.5
3.8
-
5.8
4
6
V
V
V
4.2
-
3.5
Table 18. Card drivers
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
Supply voltage for the card: pin VCC
Vo(inact)
inactive mode output
voltage
no load
0
0
-
-
-
-
0.1
0.3
−1
V
Io(inact) = 1 mA
at grounded pin VCC
V
Io(inact)
VCC
inactive mode output
current
mA
[2]
[2]
supply voltage
Active mode; 2.7 V < VDD < 6.5 V
5 V card; ICC < 60 mA; VCC = 5 V
3 V card; ICC < 55 mA; VCC = 3 V
1.8 V card; ICC < 30 mA; VCC = 1.8 V
4.75
2.80
1.65
5
5.25
3.15
1.95
V
V
V
3
1.8
Active mode; AC current pulses with
I < 200 mA, t < 400 ns and f < 20 MHz
5 V card; current pulses of 40 nAs
3 V card; current pulses of 24 nAs
1.8 V card; current pulses of 15 nAs
on VCC; 20 kHz < f < 200 MHz
4.65
2.76
1.62
-
-
-
-
-
5.35
3.24
1.98
350
V
V
V
Vripple(p-p) peak-to-peak ripple
voltage
mV
ICC
supply current
VDD > 2.7 V
5 V card; VCC = 0 V to 5 V
3 V card; VCC = 0 V to 3 V
1.8 V card; VCC = 0 V to 1.8 V
VCC shorted to GND
5 V card or 3 V card
1.8 V card
-
-
-
-
-
-
−55
−55
−35
mA
mA
mA
-
-
−90
−70
−120
−90
mA
mA
SR
slew rate
rise or fall; maximum load capacitor
CL = 300 nF
5 V card
3 V card
1.8 V card
0.080
0.050
0.025
0.140 0.200
0.080 0.110
0.045 0.080
V/µs
V/µs
V/µs
TDA8023_1
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Product data sheet
Rev. 01 — 16 July 2007
18 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 18. Card drivers …continued
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reset output to the card: pin RST
Vo(inact)
inactive mode output
voltage
no load
0
0
0
-
-
-
0.1
0.3
−1
V
Io(inact) = 1 mA
at grounded pin RST
V
Io(inact)
VOL
inactive mode output
current
mA
LOW-level output
voltage
IOL = 200 µA
0
-
0.3
V
V
VOH
HIGH-level output
voltage
IOH < −200 µA
V
CC − 0.5 -
VCC
tr
tf
rise time
fall time
CL = 30 pF
CL = 30 pF
-
-
-
-
0.1
0.1
µs
µs
Clock output to the card: pin CLK
Vo(inact)
inactive mode output
voltage
no load
0
0
0
-
-
-
0.1
0.3
−1
V
Io(inact) = 1 mA
at grounded pin CLK
V
Io(inact)
VOL
inactive mode output
current
mA
LOW-level output
voltage
IOL = 200 µA
0
-
0.3
V
V
VOH
HIGH-level output
voltage
IOH < −200 µA
V
CC − 0.5 -
VCC
tr
rise time
CL = 30 pF
-
-
-
-
-
-
8
ns
tf
fall time
CL = 30 pF
-
8
ns
fCLK
δ
frequency on pin CLK
clock duty cycle
slew rate
operational
0
10
55
-
MHz
%
CL = 30 pF
45
0.2
SR
rise and fall; CL = 30 pF
V/ns
Data lines: pins I/O, C4 and C8
Vo(inact)
inactive mode output
voltage
no load
0
-
-
-
-
0.1
0.3
−1
V
Io(inact) = 1 mA
at grounded pin I/O
V
[3]
Io(inact)
VOL
inactive mode output
current
-
mA
LOW-level output
voltage
IOL = 1 mA
0
-
0.3
V
VOH
HIGH-level output
voltage
no DC load
IOH < −20 µA
IOH < −40 µA
0.9VCC
0.8VCC
0.75VCC
−0.3
-
-
-
-
-
VCC + 0.1 V
VCC + 0.1 V
VCC + 0.1 V
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
+0.8
VCC
V
V
1.5
[3]
[3]
LOW-level input current at pin I/O; VIL = 0 V
VCC = 5 V
VCC = 3 V
-
-
-
-
-
-
600
500
10
µA
µA
µA
ILIH
HIGH-level input
leakage current
at pin I/O; VIH = VCC
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
19 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 18. Card drivers …continued
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
pull-up current
delay time
Conditions
Min
−1
-
Typ
-
Max
-
Unit
mA
ns
[3]
Ipu
td
at pin I/O; VOH = 0.9VCC; CL = 30 pF
[3][4]
between edges on pin I/O and pin
I/OUC; corresponds to width of active
pull-up pulse
500
650
tr
rise time
inputs; from VIL(max) to VIH(min)
-
-
-
-
1.5
0.1
µs
µs
tTLH
clock rise time
output transition time; from 10 % of VCC
to 90 % of VCC; CL < 30 pF; no DC load
[3]
[3]
Ci
input capacitance
on pin I/O
-
-
10
pF
Rpu(int)
internal pull-up
resistance
between pin I/O and VCC
10
13.5 17
kΩ
[3]
fmax
maximum input clock
frequency
on pin I/O
-
-
500
kHz
Card presence input: pin PRES, active-HIGH when pin SPRES = LOW or active-LOW when pin SPRES = HIGH
VIL
VIH
ILIL
LOW-level input voltage
-
-
-
-
-
-
-
0.3VDD
V
HIGH-level input voltage
0.7VDD
0
-
V
LOW-level input leakage VI = 0.3VDD; pin SPRES = HIGH
current
5
µA
µA
µA
µA
VI = 0.3VDD; pin SPRES = LOW
10
40
−10
0
ILIH
HIGH-level input
leakage current
VI = 0.7VDD; pin SPRES = HIGH
VI = 0.7VDD; pin SPRES = LOW
−40
−5
[1] Two ceramic multilayer capacitors of minimum 100 nF with low Equivalent Series Resistance (ESR) should be used in order to meet
these specifications.
[2] Output voltage towards the card, including ripple.
[3] Pin I/O has an internal 15 kΩ pull-up resistor to VCC
.
[4] Pin I/OUC has an internal 11 kΩ pull-up resistor to VDD(INTF)
.
Table 19. Sequencer and clock counter
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
-
Typ
-
Max Unit
tact
activation time
total sequence
total sequence
135
100
µs
µs
tdeact
deactivation time
60
80
Table 20. Interface signals to host controller
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Data line: pin I/OUC[1]
Conditions
Min
Typ Max
Unit
VOL
VOH
LOW-level output voltage
IOL = 1 mA
no DC load
IOH < −10 µA
0
-
-
-
-
-
-
-
0.3
V
HIGH-level output voltage
0.9VDD(INTF)
VDD(INTF) + 0.2
VDD(INTF) + 0.2
0.25VDD(INTF)
VDD(INTF) + 0.3
600
V
0.75VDD(INTF)
V
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
−0.3
V
0.7VDD(INTF)
V
VIL = 0 V
-
-
µA
µA
ILIH
HIGH-level input leakage
current
VIH = VDD(INTF)
10
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
20 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 20. Interface signals to host controller …continued
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
µs
tr
rise time
input; from VIL(max) to VIH(min)
-
-
-
-
1
tTLH
clock rise time
output transition time; from
0.1
µs
10 % to 90 % of VDD(INTF)
;
CL < 30 pF
[1]
Rpu(int)
internal pull-up resistance
between pin I/OUC and pin
VDDI
11
15
19
kΩ
Clock input: pin CLKIN
fCLKIN frequency on pin CLKIN
VIL
0
-
-
-
-
-
-
-
25
MHz
V
LOW-level input voltage
HIGH-level input voltage
VDD(INTF) > 2 V
0
0.3VDD(INTF)
0.15VDD(INTF)
VDD(INTF) + 0.3
1.5 V < VDD(INTF) < 2 V
VDD(INTF) > 2 V
0
V
VIH
0.7VDD(INTF)
V
1.5 V < VDD(INTF) < 2 V
0.85VDD(INTF)
VDD(INTF) + 0.3 ns
tr
tf
rise time
fall time
-
-
0.1 / fCLKIN
0.1 / fCLKIN
ns
ns
Logic inputs: pins SAD0, SPRES and SDWN
VIL
VIH
ILIL
LOW-level input voltage
HIGH-level input voltage
−0.3
0.7VDD
-
-
-
-
0.3VDD(INTF)
VDD(INTF) + 0.3
±1
V
V
LOW-level input leakage
current
µA
ILIH
HIGH-level input leakage
current
-
-
-
-
±1
µA
Ci
input capacitance
10
pF
Interrupt line: pin INT; open-drain active-LOW output
VOL
ILH
LOW-level output voltage
HIGH-level leakage current
Io = 2 mA
-
-
-
-
0.3
10
V
µA
Serial data input/output: pin SDA; open-drain
VIL
LOW-level input voltage
HIGH-level input voltage
LOW-level output voltage
HIGH-level leakage current
LOW-level leakage current
−0.3
-
-
-
-
-
0.3VDD
V
VIH
VOL1
ILH
0.7VDD
6.5
0.3
1
V
IOL = 3 mA
-
-
-
V
input or output
µA
µA
ILL
depends on the pull-up
1
resistance; input or output
Serial clock input: pin SCL
VIL
VIH
ILIH
LOW-level input voltage
−0.3
0.7VDD
-
-
-
-
0.3VDD
6.5
V
HIGH-level input voltage
V
HIGH-level input leakage
current
1
µA
IIL
LOW-level input current
depends on the pull-up
resistance
-
-
1
µA
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
21 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
Table 20. Interface signals to host controller …continued
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
I2C-bus timing; see Figure 7
fSCL
tBUF
SCL clock frequency
0
-
-
400
-
kHz
bus free time between a STOP
and START condition
1.3
µs
tHD;STA
hold time (repeated) START
condition
hold time after which first
clock pulse is generated
0.6
-
-
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
0.6
-
-
-
-
-
-
µs
µs
µs
tHIGH
tSU;STA
set-up time for a repeated
START condition
[2]
tHD;DAT
tSU;DAT
tr
data hold time
0
-
-
-
-
ns
ns
ns
data set-up time
100
-
-
rise time of both SDA and SCL
signals
300
tf
fall time of both SDA and SCL
signals
-
-
-
300
-
ns
tSU;STO
set-up time for STOP condition
0.6
µs
[1] Pin I/OUC has an internal 11 kΩ pull-up resistor to VDD(INTF)
.
[2] The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by
a transmitter.
Table 21. Protection and limitations
VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
−40
-
Typ
Max Unit
Tamb
Tsd
ambient temperature
-
+85
-
°C
shutdown temperature
input current limit
at die
150
°C
[1]
[1]
IIlim
on pin I/O
−15
−15
−70
−20
-
-
+15
+15
+70
+20
-
mA
mA
mA
mA
mA
IOlim
output current limit
on pin I/O
-
on pin CLK
-
shutdown current; on pin RST
shutdown current; on pin VCC
-
−90
[1] Pin I/O has an internal 15 kΩ pull-up resistor to VCC
.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
22 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
SDA
t
t
t
t
HD;STA
BUF
LOW
f
SCL
P
S
S
P
t
t
HIGH
HD;STA
t
t
t
t
t
SU;STO
r
HD;DAT
SU;DAT
SU;STA
mba705
P = STOP condition; S = START condition.
Fig 7. Timing requirements for the I2C-bus
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
23 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
12. Application information
V
DD
R3
10 kΩ
(1)
C16
IC1
100 nF
V
VUP
SAP
SBP
V
DD
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INT
IC2
C20
100 nF
V
DD
SDWN
DDP
HOST
CONTROLLER
(1)
C19
V
SBM
DDI
4.7 kΩ
V
INT
SDA
DD
C15
100 nF
100 nF
SDA
SCL
GNDP
SAM
GND
(1)
C17
SCL
CLKout
I/OAUX
100 nF
V
SAD0
SPRES
CLKIN
GND
I/OUC
C8
DD
4.7 kΩ
CDEL
22 nF
TDA8023TT
CDEL
V
DD
V
DD
PORADJ
PRES
RST
P1
C29
10
11
12
13
14
10 kΩ
100 nF
V
CC
C4
CLK
I/O
GNDC
(1)
C18
(2)
C13
100 nF
68 nF
CARD READER
normally closed
C5I
C6I
C7I
C8I
C1I
C2I
C3I
C4I
K1
K2
R
p
10 kΩ
V
DD
001aag341
(1) Low-ESR capacitor, placed near the IC.
(2) Low-ESR capacitor, placed near the C1 contact.
Fig 8. Application diagram: typical TDA8023TT application with capacitive DC-to-DC converter
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
24 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
V
DD
R3
10 kΩ
(1)
C16
IC1
100 nF
C8
D1
V
VUP
SAP
SBP
V
DD
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
4.7 µF
BAT54
INT
IC2
16 V
C20
V
DD
100 nF
SDWN
DDP
HOST
CONTROLLER
L1
V
SBM
DDI
4.7 kΩ
V
INT
SDA
6.8 µH
C15
100 nF
DD
SDA
SCL
GNDP
SAM
GND
SCL
CLKout
I/OAUX
V
SAD0
SPRES
CLKIN
GND
I/OUC
C8
DD
4.7 kΩ
CDEL
22 nF
TDA8023TT
CDEL
PORADJ
PRES
RST
V
DD
V
DD
P1
10 kΩ
C29
100 nF
10
11
12
13
14
V
CC
C4
CLK
I/O
GNDC
(1)
(2)
C18
C13
100 nF
68 nF
CARD READER
normally open
C5I
C6I
C7I
C8I
C1I
C2I
C3I
C4I
K1
K2
V
DD
001aag342
(1) Low-ESR capacitor, placed near the IC.
(2) Low-ESR capacitor, placed near the C1 contact.
Fig 9. Application diagram: typical TDA8023TT application with inductive DC-to-DC converter
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
25 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
13. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
D
E
A
X
c
H
v
M
A
y
E
Z
15
28
Q
A
2
(A )
3
A
A
pin 1 index
1
θ
L
p
L
1
14
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.8
0.5
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT361-1
MO-153
Fig 10. Package outline SOT361-1 (TSSOP28)
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
26 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
14. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
27 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 11) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 22 and 23
Table 22. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 23. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 11.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
28 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 11. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
29 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
15. Revision history
Table 24. Revision history
Document ID
Release date
20070716
Data sheet status
Change notice
Supersedes
TDA8023_1
Product data sheet
-
-
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
30 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
16.2 Definitions
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
TDA8023_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 July 2007
31 of 32
TDA8023
NXP Semiconductors
Low power IC card interface
18. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
16.4
17
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Contact information . . . . . . . . . . . . . . . . . . . . 31
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
18
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
8.1
8.2
Functional description . . . . . . . . . . . . . . . . . . . 6
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 6
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6
Without external divider on pin PORADJ . . . . . 6
With external divider on pin PORADJ. . . . . . . . 7
External capacitor on pin CDEL . . . . . . . . . . . . 7
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus conditions . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device addressing . . . . . . . . . . . . . . . . . . . . . . 9
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . 12
Capacitive configuration . . . . . . . . . . . . . . . . . 12
Inductive configuration . . . . . . . . . . . . . . . . . . 13
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.4.1
8.4.2
8.5
VCC buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.6
Sequencer and clock counter . . . . . . . . . . . . . 13
Activation sequence . . . . . . . . . . . . . . . . . . . . 13
Deactivation sequence . . . . . . . . . . . . . . . . . . 15
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.6.1
8.6.2
8.7
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal characteristics. . . . . . . . . . . . . . . . . . 16
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17
Application information. . . . . . . . . . . . . . . . . . 24
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26
10
11
12
13
14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Introduction to soldering . . . . . . . . . . . . . . . . . 27
Wave and reflow soldering . . . . . . . . . . . . . . . 27
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 28
14.1
14.2
14.3
14.4
15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 31
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16.1
16.2
16.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 July 2007
Document identifier: TDA8023_1
相关型号：
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