TDA8034HN [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, SOT616-1, MO-220, SOT616-1 HVQFN-24, Consumer IC:Other;
| 型号： | TDA8034HN |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, PLASTIC, SOT616-1, MO-220, SOT616-1 HVQFN-24, Consumer IC:Other 商用集成电路 |
| 文件： | 总30页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AN10792
TDA8034HN - Smart Card reader interface
Rev. 1.0 — 4 December 2012
Application note
Document information
Info
Content
Keywords
Abstract
TDA8034HN, Smart Card Interface, Pay TV, STB, NDS, ISO 7816-3
This application note describes the smart card interface integrated circuit
TDA8034HN.
This document helps to design the TDA8034HN in an application. The
general characteristics are presented and different application examples
are described.
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TDA8034HN - Smart Card reader interface
Revision history
Rev
Date
Description
1.0
20121204
First official release
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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1. Introduction
1.1 Presentation
The TDA8034HN is a smart card interface device forming the electrical interface between
a micro controller and a smart card. This device mainly supports asynchronous cards
(micro controller-based IC cards).
The electrical characteristics of the TDA8034HN are in accordance with NDS
requirements (IRD Electrical Interface Specifications doc n° LC-T056) and also comply
with ISO7816-3 for class A, B and C cards.
The TDA8034HN can be used in various applications such as pay-TV, Point-Of-Sale
terminals (POS), public phones, vending machines, and many conditional access
applications (i.e. internet ,...).
HOST
CPU
Config
ISO
UART
7816
TDA8034
ISO
ISO µC
Fig 1. Simplified interfacing view
In the whole document, the TDA8034HN will be referred as TDA8034.
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2. Power supply
2.1 Power supply pins
Three pins are used to supply the TDA8034: VDD(INTF), VDD and VDDP
.
VDD(INTF) is dedicated to the interface supply. All signals which are interfaced with the host
are referenced to this voltage supply.
The next table describes all the pins that must be referenced to VDD(INTF).
Table 1.
VDD(INTF) referenced pins
Comment
Pin name
CMDVCCN
RSTIN
Smart card activation. Controlled by a microcontroller GPIO
RST pin management. Controlled by a microcontroller GPIO
EN5V_3VN
Choice of the smart card voltage. Can be controlled by the microcontroller or
connected directly to GND or VDD(INTF)
EN1.8VN
CLKDIV1
CLKDIV2
PRESN
OFFN
Choice of the 1.8V smart card voltage. Can be controlled by the
microcontroller or connected directly to GND or VDD(INTF)
Control of the clock division. Can be controlled by the microcontroller or
connected directly to GND or VDD(INTF)
Control of the clock division. Can be controlled by the microcontroller or
connected directly to GND or VDD(INTF)
Not connected to the microcontroller but reference to VDD(INTF). The smart card
connector presence switch must use VDD(INTF)
Output to the host. Must be connected to the microcontroller and therefore
have the same level
IOUC
Smart card data. Controlled by the microcontroller
Management of AUX1. Controlled by the microcontroller
Management of AUX2. Controlled by the microcontroller
AUX1UC
AUX2UC
VDD is used to supply the core of the TDA8034 (mainly the digital part). It must be in the
range from 2.7 to 3.6 volts. In most of the application, if VDD(INTF) is in the range accepted
by VDD, VDD and VDD(INTF) can be connected together.
VDDP is the power supply for the card voltage generator. An LDO converts this voltage to
the level needed on the smart card side (5V, 3V or 1.8V). As there is no step-up
converter, it is mandatory that VDDP is higher than the required VCC.
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2.2 Supply supervisor
2.2.1 Main principles
The TDA8034 supervises the voltage level of VDD, VDDP and VDD(INTF). For VDD and VDDP
supervision, the threshold is internally fixed. For VDD(INTF), the threshold can be fixed
either internally or externally using the PORAdj pin.
The following figure explains the supervision for all the supplies.
Then the table gives the threshold values for each input.
V
VDD(INTF)
Vth+Vhys
Vth
t
TDA8034 reset
TDA8034 ON
(1) When one power supply input falls below its corresponding threshold, the TDA8034 is in reset
mode. When all the levels are above their threshold + the hysteresis, the TDA8034 is ON.
Fig 2. Supply supervisor principles
The hysteresis value is null when a PROADJ resistor bridge is used to fix the threshold
externally on VDD(INTF)
.
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2.2.2 Supervision with PORAdj used
The TDA8034 allows to fix externally the threshold on VDD(INTF). This can be done by
using an external resistor bridge on the PORAdj pin.
The supervision principle is given in the next two pictures:
TDA8034HN
+
-
PORADJ
VDD(INTF)_Drop
Vbg
Fig 3. VDD(INTF) supervision – PORADJ level detector
The TDA8034 compares the pin voltage level on pin PORADJ to an internal voltage
reference called Vbg.
When PORADJ falls below Vbg, the TDA8034 is reset:
V
VPORADJ
VBG
t
TDA8034 reset
Fig 4. VDD(INTF) supervision – Reset when PORADJ falls
Warning: in this particular case, the hysteresis on the supervisor is null. Then the
threshold is the same when the supply rises as when it falls.
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To detect a drop on VDD(INTF), a voltage level referred to V DD(INTF) must be connected to
PORADJ. This voltage level can be obtained with a resistor bridge:
VDD(INTF)
R1
VDD(INTF)
PORADJ
1
2
3
4
5
6
18
VDD 17
EN5V3VN
R2
VDDP
VCC
13
14
RSTIN
TDA8034HN
EN1.8VN
CMDVCCN
CLKDIV1
RST 15
CLK
16
Fig 5. VDD(INTF) supervision – Resistor bridge
In this case VPORADJ = VDD(INTF).R2/(R1+R2) and VDD(INTF) is monitored indirectly: the
TDA8034 enters the reset mode when VDD(INTF).R2/(R1 + R2) falls below Vbg.
This corresponds to a “virtual” threshold on VDD(INTF) which value is obtained when
Vbg = VDD(INTF).R2/(R1+R2) VDD(INTF) = Vbg.(1+R1/R2)
This virtual threshold is the Vth corresponding to VDD(INTF). This is called virtual as
VDD(INTF) is never compared to Vth. Only VPORADJ is compared to Vbg. The following
drawing shows this behavior:
V
VDD(INTF)
(1)
Vth
VPORADJ
VBG
t
TDA8034 reset
(1) When VDD(INTF) falls below Vth_VDDI, VPORADJ falls below Vbg then the drop-off is detected
Fig 6. VDD(INTF) supervision – Virtual VDD(INTF) threshold Vth
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The resistor bridge is needed only in the case a specific threshold on VDD(INTF) must be
chosen for the application, but in the general case, VDD(INTF) can be input directly on
PORADJ.
VDD(INTF)
VDD(INTF)
PORADJ
1
2
3
4
5
6
18
VDD 17
EN5V3VN
VDDP
VCC
13
14
RSTIN
TDA8034HN
EN1.8VN
CMDVCCN
CLKDIV1
RST 15
CLK
16
Fig 7. VDD(INTF) supervision – No resistor bridge
This is a particular case of the previous description with R1 = 0Ω and R2 =∞.
Here Vth = Vbg.(1+R1/R2) = Vbg.
2.2.3 Summary
The following table gives the different threshold values for each supply input pin.
Table 2. Supply supervisor - Typical threshold values
VDD
VDDP
VDDP
VDD(INTF)
VDD(INTF)
(VCC = 5V)
(VCC < 5V) (No PORADJ (PORADJ bridge
bridge)
used)
Corresponding 2.35V
Typ. Vth
4.45V
2.55V
1.22V
1.22 x (1+R1/R2)
Corresponding 100mV
Typ. Vhys
100mV
100mV
60mV
0mV
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2.3 Low consumption
The TDA8034 offers two low consumption modes: shutdown and deep shutdown.
2.3.1 Shutdown mode
The shutdown mode is the default mode when the card is not active (CMDVCCN HIGH).
The typical consumption in this mode is around 30µA.
Due to this mode, the activation timing changes a bit compared to the TDA8024. Refer to
the “Activation” chapter to see the exact difference induced by this mode.
2.4 Deep shutdown mode
The deep shutdown mode is a very low consumption mode (10µA typically). This mode
can be entered when the card is not active (CMDVCCN HIGH) by tying EN5V3VN and
EN1V8N to the LOW state.
In this mode, the supervisors are turned off, but the presence detection is still available:
the OFFN pin follows the status of the presence (PRESN inverted).
This mode can for example be used when no card is present. In this case, the TDA8034
cannot be used and the host can only wait for a card insertion before activating it. The
following figure gives a usage example with 5V smart cards:
VCC
PRESN
OFFN
tdebounce
CMDVCCN
EN5V3VN
EN1V8N
Active
mode
Shutdown
mode
Deep shutdown mode
Shutdown mode
Active mode
Fig 8. Deep shutdown mode example
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3. Input Clock
There are two possibilities to provide the clock to the TDA8034: using a crystal or
applying an external clock provided by the microcontroller.
Any value of crystal can be used from 2MHz to 26MHz.
The XTAL pins are referenced to VDD. In the case of a crystal, the high level of the clock
is equal to VDD, and in case of an input clock, it must be referenced to VDD.
The type of clock is detected automatically by the TDA8034. So there is no specific
configuration.
The clock is not mandatory outside of the card session. This means that if a crystal is
used, it will only toggle when CMDVCCN is low. There is no activity on XTAL1 when
CMDVCCN is HIGH.
If an external clock signal is applied to XTAL1, it is mandatory to start it before
CMDVCCN is LOW, but it is not necessary to apply it when the card must not be
activated.
The following figures represent the two configurations and the way they are used.
Clock input
N.C.
VDD(INTF)
PORADJ
1
2
3
18
VDD(INTF)
PORADJ
1
2
3
18
VDD 17
EN5V3VN
VDD 17
EN5V3VN
TDA8034HN
VDDP
13
TDA8034HN
RSTIN
VDDP
13
RSTIN
V
V
CMDVCCN
CMDVCCN
XTAL1
XTAL1
t
Clock must be
present
Clock can be
stopped
t
Clock type
detection
Card
deactivation
a. XTAL
Fig 9. TDA8034 clock
b. External clock
When the clock comes from the host (input on XTAL1), the clock generated on the smart
card side is inverted:
When a falling edge occurs on XTAL1, the corresponding edge on CLK is rising, and
when the clock rises on XTAL1, CLK falls.
This cannot be an issue for the communication with the smart card as the process is
asynchronous.
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4. Card connector
4.1 Presence pin
One input pin is available to detect the card presence: PRESN.
This pin is active LOW and embeds an internal current to VDD(INTF). Therefore, when the
pin is left open, the card is assumed to be absent.
The current sourced depends on the state of the pin. When the pin is HIGH, the current
is typ. 45µA, and when the pin is LOW, the current is typ. 2µA.
VDD(INTF)
VDD(INTF)
45µA
2µA
PRESN
PRESN
VDD(INTF)
Or
OPEN
TDA8034
TDA8034
a. PRESN HIGH 45µA
Fig 10. Internal PRESN source current
b. PRESN LOW 2µA
The way to connect the switch of a smart card connector depends on its gender
(normally open or normally closed).
4.1.1 Normally open presence switch
The TDA8034 is planned to be used with this type of card connector without any external
component. The connection of this card connector presence switch is shown in the next
figure:
Card
connector
TDA8034
Presence switch
(normally open)
PRESN
Fig 11. Normally open card connector connection
When the card is not inserted, the switch is open, and the internal current source drives
the pin at HIGH level. The PRESN pin is not active and the card is assumed to be
absent.
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When the card is inserted, the switch is closed and the PRESN pin is connected directly
to the ground. The pin is active and the card is seen as present.
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4.1.2 Normally closed presence switch
To use this type of card connector, an external resistor is mandatory, and the schematics
must be used as shown hereafter:
Card
connector
TDA8034
VDD(INTF)
Presence switch
(normally close)
PRESN
R
Fig 12. Normally closed card connector connection
When the card is not inserted, the switch is closed and PRESN is HIGH. The pin is not
active so the card is seen as absent.
A current equal to VDD(INTF)/R will be consumed.
When the card is inserted, the switch will be open. Then the PRESN pin will have a
typical 45µA current sourced into the resistor (the maximum value of this current Imax, is
given to 60µA).
The resistor must be customized to have a voltage level on the PRESN pin lower than its
minimum VIL in order to have a LOW level on the PRESN pin.
The minimum VIL (VIL_min) of the PRESN pin is equal to 0.3.VDD(INTF)
R must be customized to achieve this equation:
.
R
max.Imax < VIL_min
Rmax = 1.2 x R. It corresponds to the maximum value of a 20% resistor.
For instance, with VDD(INTF) = 3.3V, we must have:
1.2 x R x 60.10-6 < 0.3 x 3.3
R < 13.750 kΩ. The higher standard resistor that can achieve this constraint is 13kΩ.
The following table gives the standard value to be used with these schematics,
depending on the VDD(INTF) value.
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Table 3.
VDD(INTF)
Pull down resistor wrt VDD(INTF)
Standardized resistor value
1.6V ≤ VDD(INTF) < 1.8V
1.8V ≤ VDD(INTF) < 2V
2V ≤ VDD(INTF) < 2.2V
2.2V ≤ VDD(INTF) < 2.4V
2.4V ≤ VDD(INTF) < 2.7V
2.7V ≤ VDD(INTF) < 2.9V
2.9V ≤ VDD(INTF) < 3.2V
3.2V ≤ VDD(INTF)
6.2kΩ
7.5kΩ
8.2kΩ
9.1kΩ
10kΩ
11kΩ
12kΩ
13kΩ
4.1.3 Debouncing
With some card connectors, depending on the mechanical characteristics of the switch,
bouncing may be seen on the PRESN pin when a card is inserted or extracted. This
bouncing is managed by the TDA8034 which does not transfer exactly the PRESN state
to the OFFN pin.
When the card is inserted, the TDA8034 waits for the PRESN pin to be stable for several
milliseconds before assuming that the card is inserted. When the card is extracted, the
chip acts as soon as the presence is not active. This behavior is summarized in Fig 13:
PRESN
Debouncing
time
OFFN
Card insertion
Card extraction
Fig 13. Debouncing feature
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4.2 Schematics
To connect the smart card connector to the TDA, only two capacitors are mandatory as
external components. The schematic reference is given in Fig 14.
The C1 capacitor must be placed near the TDA8034 and C2 must be connected close to
the card connector.
The advised values for C1 and C2 are respectively 470nF and 220nF. These values are
mandatory to have a ripple on VCC in the specified limits.
Pins C4 and C8 of the card connector (connected to pins AUX1 and AUX2) are optional.
They can be left unconnected unless some specific operation using these pins is
required.
It is not advised to leave pin VPP (C6) unconnected. It can be connected directly to VCC
or GND in accordance with latest ISO 7816 standards. Connecting it to VCC allows it to
be compliant with older cards which might not support VPP connected to the Ground.
For more flexibility, the design should include a 0 ohm serial resistor between VPP and
VCC. Then the application can be easily adapted if needed.
VDD(INTF)
PORADJ
VDD
1
2
3
4
5
6
18
17
16
EN5V3VN
RSTIN
VDDP
TDA8034HN
EN1V8N
CMDVCCN
CLKDIV1
VCC 15
C5
470nF
14
RST
CLK
13
C6 220nF
Card connector
C5
C1
C2
C3
C4
C6
C7
C8
R4 0Ω
Fig 14. HVQFN24 Card connector design
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5. Card configuration
The chip can be configured dynamically to operate with the connected card. Two
parameters can be controlled: the voltage level and the frequency of the clock signal to
the card.
5.1 Card voltage
The voltage level is configured with the following pins:
• EN_1.8VN
• EN_5V/3VN
These pins must be connected to an output of the host. This connection is recommended
even for applications using a dedicated 5V card, in order to be easily compliant with the
next generation cards.
The voltage level has to be configured before activation. The application MUST NOT
change the value of these pins when the card is activated.
To change the voltage level of the card, the host must deactivate the card, change the
voltage level value and then re-activate the card.
These pins are also used for the deep shutdown mode.
The following table gives the action of each combination of these inputs.
Table 4.
Select voltage pin behavior
EN5V3VN
Command
EN1V8N
Deep Shutdown
VCC = 1,8V
VCC = 3V
0
1
0
1
0
0
1
1
VCC = 5V
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5.2 Card clock
5.2.1 Frequency selection
Two signals are used to select the card clock:
• CLKDIV1
• CLKDIV2
These signals must be connected to the host and determine the division ratio of the input
frequency in the clock which is sent to the card when activated.
The following table describes the frequency corresponding to CLKDIV1/2 values. fXTAL is
the frequency applied on XTAL1 (crystal or external source).
Table 5.
TDA8034 - Clock division selection
CLKDIV2
CLKDIV1
CLK
0
0
1
1
0
1
1
0
fXTAL/8
fXTAL/4
fXTAL/2
fXTAL
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5.2.2 Frequency switch
5.2.2.1 General behavior
CLKDIV1 and CLKDIV2 can be changed freely when the card is not active. The values
will be adopted on activation.
When the card is active, the frequency applied to the card can be switched by changing
CLKDIV1 and CLKDIV2 as shown in the following figure:
XTAL1
CMDVCCN
VCC
tcs
CLKDIV1
CLKDIV
2
CLK
ts1
ts2
fXTAL
fXTAL/4
fXTAL/8
Fig 15. Clock switch during activation
The clock starts with the value specified at activation. Then the clock frequency switch
occurs after a maximum of 10 XTAL1 periods after a change is seen on CLKDIV1/2
(ts<tsmax = 10 clock cycles).
5.2.2.2 Simultaneous change on CLKDIV1 and CLKDIV2
When both CLKDIV1 and CLKDIV2 have to be changed simultaneously, a maximum
delay of 1 XTAL1 period (tcs) is required between the two edges.
If this timing is not respected, an undesired frequency can be observed during the
frequency switchover as shown in the next figure: a switch from fXTAL to fXTAL/4 is
performed, but a frequency of fXTAL/2 is seen during the switchover.
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XTAL1
CMDVCCN
VCC
CLKDIV1
CLKDIV2
CLK
tS2
tS1
fXTAL/2
fXTAL
fXTAL/4
Fig 16. Unwanted frequency during the switch
6. Card Activation / Deactivation
6.1 Difference TDA8024 – TDA8034
6.1.1 Activation timing
The electrical interface between the host and the TDA is based on GPIOs and is exactly
the same for TDA8034 as for TDA8024.
In the card management, the only difference between the TDA8024 and TDA8034 is the
delay between CMDVCCN Low and VCC High.
This time is very low for the TDA8024 while it is equal to 3.47ms in the TDA8034 (see
next chapter).
6.1.2 Software
When the TDA8034 is implemented in a design, the software already developed for the
TDA8024 can be reused, with a little modification in one case:
If, for the TDA8024, the delay between VCC High and RST High had been set to a low
value (below 3.5ms), this delay must be changed to a highest value, as described in the
next chapter.
If the delay is greater than 3.5ms, then the same code can be reused without any
change.
6.2 Activation
To activate the card, two signals are controlled by the host: CMDVCCN and RSTIN.
The first signal sets the card power supply, the second controls the reset pin of the card.
In the simplest mode, two actions are required from the host to activate the card: reset
CMDVCCN and then set RSTIN. The activation sequence is shown in Fig 17.
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CMDVCCN
VCC
I/O
CLK
N x T min
RSTIN
RST
(1) N = 400 for ISO, 40000 for NDS/EMV
Fig 17. Card activation sequence
The input clock must be OK for this sequence to occur. If the clock is supplied externally
(no crystal), the clock must be present and stable before the falling edge of CMDVCCN.
The only constraint on the host is due to the standard specifications:
For the ISO 7816, the host must wait at least 400 clock cycles after the clock is active,
before asserting RST.
In NDS and EMV specifications, the delay must be 40000 clock cycles
However in this mode, the host has no way of knowing when the clock starts. So it is not
possible to count precisely the number of cycles.
To be sure that the right number of clock cycles are respected, the host must know the
timing between CMDVCCN fall, VCC rise and CLK start.
These timings are given in the following figure
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CMDVCCN
VCC
I/O
CLK
RSTIN
RST
t0
t1
t2
Fig 18. Activation timing
During t0, the TDA8034 checks for the XTAL1 pin to detect if a crystal is present or if the
clock is supplied from the microcontroller, and then waits for the crystal to start.
This time is fixed, even if there is no crystal, and its maximum value is 3.2ms.
t1 is the time between the beginning of the activation and the start of the clock on the
smart card side. This time depends on the internal oscillator frequency and lasts at
maximum 272µs.
The host must then assume that the smart card clock doesn’t start before 3.47 ms after
CMDVCCN has been set to LOW.
To set RSTIN, the host must wait at least 400 (ISO) or 40000 (NDS/EMV) clock cycles
after the start of CLK. Therefore t2 depends on the input clock and on the division applied
to supply the clock to the smart card and must be managed by the host.
The time between CMDVCCN low and RSTIN high, must respect this condition:
t0+t1+t2 > 3.47ms + 400/fCLK or
t0+t1+t2 > 3.47ms + 40000/fCLK
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6.3 Deactivation
The deactivation is managed entirely by the TDA8034 sequencer. Deactivation occurs
when one of the following events happens:
• Rising edge of CMDVCCN (normal host deactivation)
• A fault is detected:
− Card removal
− Overheating
− Short-circuit or high current on VCC
− VDD(INTF), VDD or VDDP drop
The deactivation sequence is automatic and fully compliant with the standard. For more
details on the activation or deactivation sequence and their timings, refer to the TDA8034
data sheet and ISO 7816-3 standard.
7. Card operation
7.1 I/O, Aux1, Aux2
The TDA8034 acts as a simple transceiver incorporating a voltage level shifting
adaptation for these signals, once the card is activated.
As there is no other conversion, the host must manage entirely the protocol defined by
ISO 7816 (Baudrate, timing, frame…).
The TDA8034 only limits the current on the pins. There is a limitation of 15mA in both
directions.
• I/O is linked to I/OUC,
• AUX1 to AUX1UC, and
• AUX2 to AUX2UC.
I/OUC must be connected directly to an I/O of the host. AUX1UC and AUX2UC can as
well be connected to the host or left open if C4 and C8 pin are not used on the card.
7.2 Warm reset
The host can operate a warm reset with the TDA8034: as the RST card pin is the copy of
the RSTIN pin, the host just needs to apply a falling edge on RSTIN, followed by a rising
edge, and the card shall send its ATR again.
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8. Fault detection
The TDA8034 supervises several parameters and warns the host when a problem
occurs. The OFFN pin is used to manage this communication with the host. The table
below gives the state of the chip in accordance with CMDVCCN and OFFN values.
Table 6.
Chip state regarding CMDVCCN and OFFN
CMDVCCN OFFN
State
Comment
HIGH
HIGH
Card is present
and not active
HIGH
LOW
LOW
Card is absent
HIGH
Card is active and This is the state of all card sessions
no fault has been
detected
LOW
LOW
A fault has been
detected (card
has been
The cause of the deactivation is not
yet known.
deactivated)
Rising edge Stays LOW
The fault detected Setting CMDVCCN allows checking if
was the card
removal
the deactivation is due to card
removal.
In this case the OFFN pin will stay
low after CMDVCCN is high.
Rising edge Rising edge The fault detected
was not a card
If OFFN follows CMDVCCN, the fault
is due to a supply voltage drop, a
VCC over-current detection or
overheating.
removal (card is
still present)
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9. Electrical design recommendations
9.1 Decoupling
To ensure proper behavior of the TDA8034, some external components have to be used.
All supply pins must be protected against noise.
VCC pin (card contact) needs to be connected to two capacitors: 470nF plus 220nF as
described in chapter 4: one near the TDA8034 chip and one near the card connector.
These capacitors type must be low ESR.
VDD(INTF)and VDD must be protected by 100nF.
VDDP must be protected by two capacitors: one 100 nF to protect particularly against
high frequency noise and one 10 µF to absorb slower variations.
VDD(INTF)
C2
100nF
VDD(INTF)
PORADJ
VDD
1
2
3
4
5
6
18
17
16
VDD
C1
100nF
EN5V3VN
RSTIN
VDDP
VDDP
TDA8034HN
C3
100nF
EN1V8N
CMDVCCN
CLKDIV1
VCC 15
C4
10µF
14
13
RST
CLK
Fig 19. Power supply decoupling strategy
9.2 Layout
For noise reduction optimization, the layout of the design must adhere to the following
guidelines.
9.2.1 Decoupling capacitors
Capacitors are mandatory to protect the supply pins as well as the VCC pin (TDA8034
pin and Card connector pin).
Place decoupling capacitors as close as possible to the pin that they protect.
This means that the capacitor must be physically soldered near the chip or the card
connector pin, but also with a short and good connection (low resistance) between the
protected pin and its capacitor.
The connection between the capacitor pin and the ground must be short low resistive as
well.
9.2.2 Clock wires
Clock (card) or oscillator signals can cause crosstalk to other signals. It is advised to
isolate these signals: make the connections as short as possible and keep them far from
other signals.
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The best is to shield these signals with ground when possible.
9.2.3 Card ground connection
There is no ground pin dedicated to the smart card connector on the TDA8034.
Therefore the C5 pin of the card connector must be connected to the main ground layer
with a short and low resistive connection.
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9.3 Summary
(1)
VDD(INTF)
Microcontroller
VDD(INTF)
R1
(5)
R2
VDD(INTF)
(2)
C1
100nF
VDD
VDDP
(2)
C2
100nF
(2)
(2)
VDD(INTF)
PORADJ
VDD
1
2
3
4
5
6
18
17
16
C3
100nF
C4
10µF
EN5V3VN
RSTIN
VDDP
TDA8034HN
EN1V8N
CMDVCCN
CLKDIV1
VCC 15
C5
14
RST
470nF
CLK
13
(3)
(4) C6 220nF
Card connector
C5
C1
C2
C3
C4
C6
C7
C8
R4 0Ω
(1) Microcontroller and TDA8034 must use the same VDD(INTF) supply
(2) Place these capacitor close to the pin they protect (VDD(INTF), VDD, VDDP)
(3) Low ESR 470nF capacitor. Must be placed close to the chip’s VCC pin
(4) Low ESR 220nF capacitor. Must be placed close to the C1 contact of the card connector
(5) Optional resistor bridge. If this bridge is not required, connect PORAdj pin to VDD(INTF)
Fig 20. Reference design with TDA8034HN
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10. Legal information
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
10.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
10.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of non-
infringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
In no event shall NXP Semiconductors, its affiliates or their suppliers be
liable to customer for any special, indirect, consequential, punitive or
incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
10.3 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
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11. List of figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Simplified interfacing view.................................3
Supply supervisor principles .............................5
VDD(INTF) supervision – PORADJ level detector .6
VDD(INTF) supervision – Reset when PORADJ
falls ...................................................................6
Fig 5.
Fig 6.
VDD(INTF) supervision – Resistor bridge..............7
VDD(INTF) supervision – Virtual VDD(INTF) threshold
Vth ....................................................................7
Fig 7.
VDD(INTF) supervision – No resistor bridge..........8
Deep shutdown mode example.........................9
TDA8034 clock................................................10
Internal PRESN source current.......................11
Normally open card connector connection......11
Normally closed card connector connection....13
Debouncing feature.........................................14
HVQFN24 Card connector design ..................15
Clock switch during activation.........................18
Unwanted frequency during the switch ..........19
Card activation sequence................................20
Activation timing..............................................21
Power supply decoupling strategy ..................24
Reference design with TDA8034HN ...............26
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
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12. List of tables
Table 1. VDD(INTF) referenced pins ...................................4
Table 2. Supply supervisor - Typical threshold values....8
Table 3. Pull down resistor wrt VDD(INTF) ........................14
Table 4. Select voltage pin behavior.............................16
Table 5. TDA8034 - Clock division selection.................17
Table 6. Chip state regarding CMDVCCN and OFFN...23
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13. Contents
10.1
10.2
10.3
Definitions.........................................................27
Disclaimers.......................................................27
Trademarks ......................................................27
1.
1.1
Introduction .........................................................3
Presentation.......................................................3
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.4
Power supply.......................................................4
Power supply pins..............................................4
Supply supervisor...............................................5
Main principles ...................................................5
Supervision with PORAdj used ..........................6
Summary............................................................8
Low consumption ...............................................9
Shutdown mode .................................................9
Deep shutdown mode ........................................9
11.
12.
13.
List of figures.....................................................28
List of tables ......................................................29
Contents.............................................................30
3.
Input Clock.........................................................10
4.
4.1
4.1.1
4.1.2
4.1.3
4.2
Card connector..................................................11
Presence pin....................................................11
Normally open presence switch .......................11
Normally closed presence switch.....................13
Debouncing......................................................14
Schematics.......................................................15
5.
5.1
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
Card configuration ............................................16
Card voltage.....................................................16
Card clock ........................................................17
Frequency selection.........................................17
Frequency switch .............................................18
General behavior..............................................18
Simultaneous change on CLKDIV1 and
CLKDIV2..........................................................18
6.
6.1
6.1.1
6.1.2
6.2
Card Activation / Deactivation..........................19
Difference TDA8024 – TDA8034......................19
Activation timing...............................................19
Software...........................................................19
Activation..........................................................19
Deactivation .....................................................22
6.3
7.
7.1
7.2
Card operation...................................................22
I/O, Aux1, Aux2................................................22
Warm reset.......................................................22
8.
Fault detection...................................................23
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
Electrical design recommendations................24
Decoupling.......................................................24
Layout ..............................................................24
Decoupling capacitors......................................24
Clock wires.......................................................24
Card ground connection...................................25
Summary..........................................................26
10.
Legal information ..............................................27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2012.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 December 2012
Document identifier: AN10792
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