TDA8505 [NXP]
SECAM encoder; SECAM编码器
| 型号： | TDA8505 |
| 厂家： | 
NXP |
| 描述： | SECAM encoder |
| 文件： | 总32页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8505
SECAM encoder
July 1994
Preliminary specification
Supersedes data of May 1993
File under Integrated Circuits, IC02
Philips Semiconductors
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
FEATURES
GENERAL DESCRIPTION
• Two input stages, R, G, B and Y, −(R−Y), −(B−Y) with
multiplexing.
The TDA8505 is a highly integrated SECAM encoding IC
that is designed for use in all applications that require
transformation of R, G and B signals or Y, U and V signals
to a standard SECAM signal.
• Chrominance processing, highly integrated, includes
vertical identification, low frequency pre-emphasis and
high frequency pre-emphasis (anti-Cloche) and
bandpass filter.
The specification of the input signals is fully compatible
with those of the TDA8501 PAL/NTSC encoder.
• Fully controlled FM modulator which produces a signal
in accordance with the SECAM standard without
adjustments.
• Two reference oscillators, one for D'R f0 (4.40625 MHz)
and one for D'B f0 (4.250 MHz). These oscillators are
tuned by PLL loop with the frequency of the line sync as
reference. Crystal tuning, or tuning by external
reference source, of the reference oscillators is
possible.
• Output stages, CVBS and separated Y + SYNC and
CHROMA. For CVBS output, signal amplitude 2 V (p−p)
nominal, thus only an external emitter follower is
required for 75 Ω driving.
• Sync separator circuit and pulse shaper, to generate the
required pulses for the processing, line, frame, FH/2 and
chrominance blanking.
• A 3-level sandcastle pulse is generated for PAL/NTSC
to SECAM transcoding.
• FH/2 input for locking with another decoder.
• Colour killing on the internal colour difference signals.
• Internal bandgap reference.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
SDIP32
MATERIAL
CODE
TDA8505
32
plastic
SOT232-1
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
BLOCK DIAGRAM
LMA95-13
a n d b o o k , f u l l p a g e w
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PINNING
D'R and D'B are the colour difference signals at the output of the multiplexer circuit; D'R = −1.9(R−Y) and
D'B = +1.5(B−Y), for an EBU bar of 75% the amplitudes are equal.
SYMBOL
−(R−Y)
PIN
1
DESCRIPTION
colour difference input signal, for EBU bar of 75% 1.05 V (peak-to-peak value)
multiplexer control; input HIGH = RGB, input LOW = −(R−Y), −(B−Y) and Y
colour difference input signal, for EBU bar of 75% 1.33 V (peak-to-peak value)
MCONTR
−(B−Y)
FH/2
2
3
4
line pulse input divided-by-2 for synchronizing two or more encoders; when not used this
pin is connected to ground
Y
5
6
luminance input signal 1 V nominal without sync
TEST
test pin; must be connected to VCC (pin 8), or left open-circuit
RED input signal for EBU bar of 75% 0.7 V (peak-to-peak value)
analog supply voltage for encoder part; 5 V nominal
GREEN input signal for EBU bar of 75% 0.7 V (peak-to-peak value)
analog ground
R
7
VDDA
8
G
9
VSSA
10
11
12
B
BLUE input signal for EBU bar of 75% 0.7 V (peak-to-peak value)
Y/Y+SYNC
when this control input is LOW, Y without sync is connected to pin 5, input blanking at
pin 5 is active; when input is HIGH, Y+SYNC is connected to pin 5, input blanking at pin 5
is not active
LPFDR
FADJ
LPFDB
FLT
13
14
15
16
17
18
19
modulator control loop filter output; black level of D'R = 4.40625 MHz
adjustment pin for 4.286 MHz of HF pre-emphasis filter
modulator control loop filter output; black level of D'B = 4.250 MHz
filter tuning loop capacitor output
Vref
2.5 V internal reference voltage output
CHROMA
Vext
chrominance output, amplitude corresponds with Y+SYNC at the output of the delay line
external power supply for sandcastle generation; when not used this pin is connected to
ground
SAND
20
21
22
23
24
25
3-level sandcastle output pulse
CVBS
composite SECAM output 2 V (peak-to-peak value) nominal
Y+SYNC output after an internal resistor of 2 kΩ; a notch filter can be connected
Y+SYNC input, connected to the output of the delay line
loop filter output for 4.40625 MHz reference oscillator
NOTCH
Y+SYNC IN
LPF4.4
Y+SYNC OUT
Y+SYNC output, 2 V (peak-to-peak value) nominal, connected to the input of the
delay line
XTAL/PLL
VIDENT
26
27
control pin; input HIGH = crystal tuning, input LOW = PLL tuning, both without vertical
identification, 2.5 V = PLL tuning with vertical identification
VCO4.25
when used for PLL tuning a capacitor is connected; when used for crystal tuning a crystal
has to be connected (in series with a capacitor)
COLKIL
CS
28
29
colour killing; input HIGH = active, internal colour difference signals are blanked
composite sync input, 0.3 V (peak-to-peak value) nominal
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
SYMBOL
VSSD
PIN
DESCRIPTION
30
31
digital ground
LPF4.25
loop filter output for 4.25 MHz reference oscillator; connected to pin 17 (Vref) when
external tuning by crystal or signal source
VDDD
32
supply voltage for the digital part
handbook, halfpage
V
(R Y)
1
2
32
31
30
DDD
MCONTR
LPF4.25
V
3
(B Y)
FH/2
Y
SSD
4
29 CS
5
COLKIL
28
TEST
6
27 VCO4.25
XTAL/PLL
R
7
26
VIDENT
V
Y+SYNC OUT
8
25
DDA
TDA8505
G
9
24 LPF4.4
23 Y+SYNC IN
22 NOTCH
V
10
11
12
SSA
B
21
Y/Y SYNC
CVBS
20 SAND
LPFDR 13
FADJ 14
19
18
17
V
ext
LPFDB 15
CHROMA
V
FLT
16
ref
MLA952 - 3
Fig.2 Pin configuration.
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
The Y output signal of the multiplexer is added to the sync
pulse of the sync separator.
FUNCTIONAL DESCRIPTION
The following three important circuits are integrated:
• Encoder circuit
The Y input (pin 5) is different to the other 5 inputs. The
timing of the internal clamping is after the sync period and
there is no vertical blanking.
• Modulator control circuit
• Sync separator and pulse shaper.
The input blanking of Y can be switched off by a HIGH at
pin 12, and the internal sync separator signal is not added
to the Y signal. In this way the Y+SYNC is allowed at pin 5
and after clamping internally connected directly to pin 25.
Encoder circuit
INPUT STAGE
The colour difference signals are switched sequentially by
H/2 and fed to the low frequency pre-emphasis circuit.
R, G and B inputs are connected to the matrix via a
clamping and a blanking circuit.
The colour-killing input signal at pin 28 can be used for
completely blanking the internal colour difference signals
at the input of the low frequency pre-emphasis filter.
For an EBU colour bar of 75% the amplitude of the signal
must be 0.7 V (peak-to-peak value). The outputs of the
matrix are Y, D'R and D'B.
The second part of the input stage contains inputs for
colour difference signals and a luminance signal. The
condition for 75% colour bar is
LOW FREQUENCY PRE-EMPHASIS
This filter is fully integrated, Fig.3 illustrates the nominal
response.
−(R−Y) = 1.05 V (peak-to-peak value) at pin 1,
−(B−Y) = 1.33 V (peak-to-peak value) at pin 3 and
Y = 1 V (peak-to-peak value) without sync at pin 5. After
clamping and blanking the amplitude and polarity are
corrected such that the signals are equal to the signals of
the matrix output. Signals are connected to a switch. Fast
switching between the two input parts is possible by the
multiplexer control pin (pin 2).
The transfer is guaranteed within the illustrated area for
the whole ambient temperature range by a compensation
circuit.
MLA953 - 1
4
H
(dB)
2
0
2
4
6
8
10
10
4
5
6
7
10
10
10
f (Hz)
Fig.3 Nominal response for the low frequency pre-emphasis filter.
6
July 1994
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
level of D'R. The modulator control also sets the DC level
at pin 15 to adjust the FM frequency to 4.250 MHz at the
black level of D'B.
VERTICAL IDENTIFICATION
After the low frequency pre-emphasis the signal is
clamped and, if desired the vertical identification sawtooth
waveform can be added. The generation of the vertical
identification is switched on/off by the logic level input at
pin 26.
At the start of every line the FM modulator is stopped and
is started again by a short duration pulse of the pulse
shaper. These stop/start pulses are operating such that
after two lines starting in the same phase, the start phase
of the third line is shifted 180 degrees. This sequence is
inverted during each vertical blanking.
Figure 4 shows the sawtooth waveform at the input of the
FM modulator with the corresponding frequency values
after modulation.
The FM signal is fed to the internal HF pre-emphasis filter.
Vertical identification is only possible if PLL tuning is
selected.
HF PRE-EMPHASIS AND BANDPASS FILTER
An HF pre-emphasis filter combined with a bandpass filter
is integrated.
GAIN + LIMITER
The gain of this amplifier is sequentially switched, so that
the amplitude of D'R is 280/230 times the amplitude of D'B
(based on an EBU colour bar). The signal is limited at a
lower and upper level to ensure that the FM modulator
frequencies are always between 3.9 MHz and 4.756 MHz.
A DC offset between D'R and D'B is added which
corresponds with the limiter levels.
Figures 5 and 6 illustrate the frequency response. Two
resistors in series with a potentiometer at pin 14 adjusts
the frequency to 4.286 MHz with a tolerance of ±20 kHz.
A tuning circuit integrated with an external capacitor
connected to pin 16 guarantees a stable frequency
response for the whole temperature range.
The output of the bandpass filter is connected directly to
the chrominance blanking circuit.
FM MODULATOR
The signal of the gain + limiter stage is fed to the FM
modulator.
The modulator control adjusts the DC level at pin 13 to set
the frequency of the FM signal to 4.406 MHz at the black
frequency
after
modulation
64 µs
64 µs
15 µs
5 µs
4.756 MHz
35 kHz
D'R
4.406 MHz
4.250 MHz
D'B
3.90 MHz
35 kHz
MLA954
18 µs
6 µs
Fig.4 Vertical identification sawtooth waveform input.
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July 1994
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
MLA955 - 1
0
H
(dB)
20
40
60
80
100
10
5
6
7
8
10
10
10
f (Hz)
Fig.5 Frequency response of the HF pre-emphasis and bandpass filter; H as a function of frequency (1).
MLA956 - 1
16
H
(dB)
14
12
10
8
upper limit
nominal
lower limit
6
4
2
0
2
3.7
3.9
4.1
4.3
4.5
4.7
4.9
f (MHz)
Fig.6 Frequency response of the HF pre-emphasis and bandpass filter; H as a function of frequency (2).
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
The outputs of the 272 divider are also used for pulse
shaping.
CHROMINANCE BLANKING
The chrominance signal is blanked by the internally
generated chrominance blanking pulse. The output of this
blanking stage is connected to the chrominance and
CVBS output circuits.
Within the vertical blanking period, another two Phase
Locked Loops (PLLs) synchronizes the FM modulator
during two lines with the 4.406 MHz reference VCO and
during the following 2 lines with the 4.250 MHz reference
VCO. The loop filters are connected to pins 13 and 15
respectively.
Y+SYNC, CVBS, AND CHROMA OUTPUTS
The Y output signal of the matrix is added to the composite
sync signal of the sync separator. The output of this adder
at pin 25 is connected to the input of an external delay line
which is necessary for correct timing of the Y+SYNC signal
corresponding with the chrominance signal. The signal
amplitude at pin 25 is 2 V (peak-to-peak value) nominal,
so at the output of the delay line Y+SYNC is
It is necessary to use low-leakage capacitors for these
loop filters.
TUNING BY CRYSTAL OR EXTERNAL SIGNAL SOURCE
When the frequency of the sync pulse at pin 29 is not
stable or is incorrect it is possible to tune the FM modulator
using an external 4.250 MHz crystal connected to pin 27.
The 4.25 MHz loop at pin 31 has to be connected to pin 17
(Vref). A stable line frequency reference is generated by
the 272 divider circuit which is used for the 4.406 MHz
reference loop.
1 V (peak-to-peak value).
The delay line has to be DC-coupled between
pins 25 and 23 to ensure the required DC level at
pin 23. The output resistor of the delay line has to be
connected to pin 17 where (Vref = 2.5 V).
An external signal source, instead of a crystal, can be
connected at pin 27 via a capacitor in series with a resistor.
The output of the delay line is connected to pin 23 which is
the input of a buffer operational amplifier. The output of the
buffer operational amplifier is connected to pin 22 and to
the CVBS adder stage via an internal resistor of 2 kΩ. An
external notch filter can be connected to pin 22. The CVBS
signal amplitude output at pin 21 is 2 V (peak-to-peak
value) nominal. An external emitter follower is used to
provide a 75 Ω output load.
The minimum AC current of 50 µA is determined by the
resistor values (Rint + Rext) and the output voltage of the
signal source (see Fig.7).
When crystal tuning is used no vertical identification
is possible.
Crystal tuning is recommended for VTR signals.
The amplitude of the chrominance output signal which is
connected to pin 18 corresponds with the Y+SYNC signal
at the output of the delay line.
Modulator control circuit
The modulator control circuit has two tuning modes which
are controlled by the input at pin 26:
handbook, halfpage
• Tuning by line frequency
TDA8505
• Tuning by crystal or external signal source.
µ
50 A
I
R
R
ext
signal
source
int
27
OSCILLATOR
TUNING BY LINE FREQUENCY
800 Ω
V (p-p)
1 nF
Two reference voltage controlled oscillators (VCOs) are
integrated, the 4.4 MHz VCO with an internal capacitor
and the 4.25 MHz VCO with an external capacitor at
pin 27.
MSA732 - 1
A PLL loop with divider circuits directly couples the
frequencies of the two VCOs with the line frequency of the
sync separator sync signal.
The loop filter for the 4.40625 MHz reference is at pin 24
and the loop filter for the 4.250 MHz reference is at pin 31.
Fig.7 Tuning circuit for external signal source.
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
Figures 9 and 10 show the generated pulses during
Sync separator and pulse shaper
vertical blanking for PLL tuning or crystal tuning
respectively. Figure 11 shows the pulses during line
blanking.
The composite sync input at pin 29 together with the
outputs of the 272 divider of the 4.250 MHz reference loop
are the sources for all pulses necessary for the processing.
The pulses are used for:
• Clamping
Transcoding application
A sandcastle pulse is necessary for the PAL/NTSC
demodulator (i.e. TDA4510) for transcoding PAL or NTSC
to SECAM.
• Video blanking
• FH/2
Most of the demodulator ICs use a sandcastle pulse with
an amplitude of 12 V or 8 V. A 12 V or 8 V sandcastle is
not possible with the TDA8505 because of the 5 V power
supply.
• Chrominance blanking
• Stop/start of modulator
• Vertical identification
• Timing for the modulator control
• Sandcastle pulse shaping at pin 20.
To generate a 3-level sandcastle pulse at pin 20
(see Fig.8) an external supply voltage must be connected
to pin 19.
External FH/2 at pin 4 is only necessary when two or more
SECAM encoders have to be locked in the same phase.
The phase of the internal FH/2 can be locked with an
external FH/2 connected at pin 4. A reset of the internal
FH/2 is possible by forcing pin 4 to a HIGH level. This
HIGH level corresponds with D'R. Pin 4 is connected to
ground when not used.
The PAL or NTSC CVBS signal is connected to the
composite sync input (pin 29) for PLL tuning and pulse
shaping. As previously mentioned the Y input at pin 5 can
be used as the Y+SYNC input for the filtered Y+SYNC PAL
or NTSC signal, when pin 12 is at a HIGH level.
V
ext
4.5 V 0.2 V
2.5 V 0.2 V
0.5 V
MSA733 - 1
Fig.8 3-level sandcastle pulse.
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
July 1994
12
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
Fig.11 Pulses during line blanking.
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July 1994
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all voltages referenced to VSSA pin 10.
SYMBOL
VDDA
VDDD
Vext
PARAMETER
analog supply voltage for encoder part
digital supply voltage
MIN.
MAX.
UNIT
0
0
0
5.5
5.5
V
V
external supply voltage for sandcastle generation
storage temperature
13.2
+150
+70
V
Tstg
−65
−25
°C
°C
Tamb
operating ambient temperature
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient in free air
60
K/W
DC CHARACTERISTICS
VCC and VDD = 5 V; Tamb = 25 °C; all voltages referenced to pins 10 and 30; unless otherwise specified.
SYMBOL
VDDA
VDDD
IDDA
PARAMETER
analog supply voltage for encoder part (pin 8)
digital supply voltage (pin 32)
MIN.
4.5
TYP.
5.0
MAX.
UNIT
5.5
5.5
−
V
V
4.5
5.0
39
4
analog supply current
−
mA
mA
V
IDDD
digital supply current
−
−
Vext
external supply voltage for sandcastle generation
total power dissipation
0
8 to 12 13.2
Ptot
−
215
2.5
−
mW
V
Vref
reference voltage output (pin 17)
2.425
2.575
AC CHARACTERISTICS
VCC and VDD = 5 V; Tamb = 25 °C; composite sync signal connected to pin 29; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
Encoder circuit: input stage (pins 1, 3, 5, 7, 9 and 11; black level = clamping level
UNIT
Vn(max)
Vn(min)
Ibias(max)
VI
voltage from black level positive
voltage from black level negative
maximum input bias current
input voltage clamped
1.2
0.9
−
−
−
−
−
−
1
−
V
only pins 1, 3 and 5
VI = V17
V
µA
V
input capacitor
−
V17
connected to ground
ZI
input clamping impedance
II = 1 mA
IO = 1 mA
−
−
80
80
−
−
Ω
Ω
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Multiplexer control (pin 2; note 1)
VIL
LOW level input voltage Y, −(R−Y)
and −(B−Y)
0
1
−
−
−
0.4
V
V
VIH
HIGH level input voltage R, G
and B
5
II
input current
−
−
−3
µA
tsw
switching time
50
−
ns
Control input Y/Y+SYNC (pin 12)
VIL
LOW level input voltage
blanking pin 5 active;
internal sync added to Y
0
4
−
−
1
5
V
V
VIH
HIGH level input voltage
blanking pin 5 inactive;
internal sync not added
to Y
II(max)
maximum input current
−
−
1
µA
XTAL/PLL and VIDENT input (pin 26)
VIL
VIH
VI
LOW level input voltage
HIGH level input voltage
input voltage
PLL mode; vertical
identification off
0
4
−
−
1
5
−
V
V
V
crystal tuning; vertical
identification off
−
pin 26 connected to
pin 17; PLL tuning;
vertical identification on;
see Fig.4
V17
II
input current
−
−
−6
µA
COLKIL input (pin 28)
VIL
LOW level input voltage
inactive
active
0
4
−
−
−
−
1
5
1
V
VIH
HIGH level input voltage
maximum input current
V
II(max)
µA
FH/2 input (pin 4)
VIL
LOW level input voltage
inactive
active
0
4
−
−
−
−
1
5
1
V
VIH
HIGH level input voltage
maximum input current
V
II(max)
µA
LF pre-emphasis (see Fig.3)
HF pre-emphasis and bandpass (see Figs 5 and 6)
FADJ input (pin 14) resistor value for correct adjustment; see Fig.1
input sensitivity
−
−
1.75
−
kHz/mV
nA
II(max)
maximum input current
−
100
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FLT output (pin 16)
VDCL
VDCH
VDC
limited DC LOW level output
voltage
IO = 200 µA
−
−
0.27
−
−
V
V
V
limited DC HIGH level output
voltage
II = 200 µA
1.8
DC level output voltage
tbf
0.86
tbf
Y+SYNC output (pin 25)
RO
output resistance
−
−
40
−
Ω
Isink(max)
maximum sink current
200
1
−
µA
mA
V
Isource(max)
maximum source current
black level output voltage
sync voltage amplitude
Y voltage amplitude
−
−
VBL
VSYNC
VY
B
−
1.6
600
1400
−
−
570
1330
10
−
630
1470
−
mV
mV
MHz
ns
bandwidth frequency response
group delay time tolerance
RL = 10 kΩ; CL = 10 pF
RL = 10 kΩ; CL = 10 pF
td
−
20
360
td
sync delay time from
pin 29 to pin 25
220
290
ns
td
Y delay time from pin 5 to pin 25
−
10
−
ns
Y+SYNC input (pin 23; note 2)
Ibias
input bias current
−
−
−
−
1
1
µA
VI(max)
maximum Y voltage amplitude
V
NOTCH output (pin 22)
RO
output resistance
1750
−
2000
V23
−
2250
Ω
VDC
DC output voltage level
maximum sink current
−
−
V
Isink(max)
300
µA
CHROMA output (pin 18)
Isink(max)
Isource(max)
VDC
maximum sink current
200
1
−
−
−
−
−
µA
mA
V
maximum source current
DC voltage level
−
−
2.5
5
∆VDC
variation of DC voltage level
chrominance signal
blanked
−
mV
chrominance signal not
blanked
−
5
−
mV
RO
output resistance
−
−
−
120
165
205
−
−
−
Ω
VO(p-p)
chrominance output voltage
amplitude (peak-to-peak value)
f = 4.25 MHz
f = 4.406 MHz
mV
mV
July 1994
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Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
FREQUENCY OF CHROMINANCE SIGNAL (NOTE 3)
fOR
black level of D'R
black level of D'B
maximum frequency
minimum frequency
deviation of D'R
−
−
4406
−
−
kHz
fOB
4250
4756
3900
280
kHz
kHz
kHz
kHz
kHz
fmax
fmin
4721
3865
252
4791
3935
308
∆D'R
∆D'B
EBU bar of 75%
deviation of D'B
EBU bar of 75%
207
230
253
CVBS output (pin 21)
Isink(max)
Isource(max)
Vblack
GY
maximum sink current
250
1
−
−
−
−
−
−
−
µA
mA
V
maximum source current
black level voltage
−
−
1.6
6
gain Y+SYNC (pin 23 to pin 21)
gain CHROMA (pin 18 to pin 21)
output resistance
−
dB
dB
Ω
GCHR
RO
−
6
−
120
LPFDR output (pin 13)
VO DC control voltage level
tbf
−
2.4
0.2
−
tbf
−
V
control sensitivity
kHz/mV
nA
ILO
output leakage current
−
50
LPFDB output (pin 15)
VO DC control voltage level
tbf
−
2.1
1.5
−
tbf
−
V
control sensitivity
kHz/mV
nA
ILO
output leakage current
−
50
LPF4.4 output (pin 24)
VO DC control voltage level
tbf
−
2.3
1.5
−
tbf
−
V
control sensitivity
kHz/mV
nA
ILO
output leakage current
−
100
LPF4.25 output (pin 31; Cext = 270 pF)
VO
DC control voltage level
control sensitivity
tbf
−
2.3
5.3
−
tbf
−
V
kHz/mV
nA
ILO
output leakage current
−
100
VCO4.25 (pin 27; note 4)
CS input (pin 29)
VI(p-p)
sync pulse input amplitude
75
300
600
mV
(peak-to-peak value)
slicing level
−
−
−
50
4
−
−
−
%
II
input current
µA
µA
IO(max)
maximum output current
during sync
100
July 1994
17
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
SYMBOL
ext (pin 19)
Iext
SAND output (pin 20; Vext = 13.2 V); see Fig.8
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
external supply current
−
−
1.5
mA
Isink(max)
Isource(max)
VTL
maximum sink current
maximum source current
top voltage level
100
100
−
−
−
−
−
−
µA
µA
V
V
ext < 10 V
ext > 10 V
Vext − 0.
1
V
10
−
−
V
Notes
1. The threshold level of pin 2 is 700 ± 20 mV. The specification of the HIGH and LOW levels is in accordance with the
scart fast blanking.
2. The black level of input signal must be 2 V; amplitude 1 V (peak-to-peak value) nominal (Y = 700 mV,
SYNC = 300 mV).
3. The tolerances of fOR and fOB are with the printed-circuit board <±5 kHz. This value can be influenced by the print
layout.
4. The oscillator operates in series-resonance. The resonance resistance of the crystal must be <60 Ω and parallel
capacitance of the crystal <10 pF.
INTERNAL CIRCUITRY
PIN
NAME
−(R−Y)
CIRCUIT
DESCRIPTION
1
−(R−Y) input; connected via 47 nF
capacitor; 1.05 V (peak-to-peak
value) for EBU bar of 75%;
see also pins 3, 5, 7, 9 and 11
July 1994
18
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
CIRCUIT
DESCRIPTION
2
MCONTR
multiplexer control input:
<0.4 V Y, U and V
>1 V R, G and B
3
4
−(B−Y)
see pin 1
−(B−Y) input; connected via 47 nF
capacitor; 1.33 V (peak-to-peak
value) for EBU bar of 75%
FH/2
FH/2 input; forcing possibility;
when not used this pin is
connected to ground
5
6
Y
see pin 1
Y input; connected via 47 nF
capacitor; 1 V (peak-to-peak
value) for EBU bar of 75%
TEST
test pin; connected to VCC or left
open-circuit
July 1994
19
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
CIRCUIT
DESCRIPTION
7
8
R
see pin 1
RED input; connected via 47 nF
capacitor; 0.7 V (peak-to-peak
value) for EBU bar of 75%
VDDA
analog supply voltage for encoder
part; 5 V nominal
9
G
see pin 1
GREEN input; connected via
47 nF capacitor; 0.7 V
(peak-to-peak value) for EBU bar
of 75%
10
VSSA
analog ground
11
12
B
see pin 1
BLUE input; connected via 47 nF
capacitor; 0.7 V (peak-to-peak
value) for EBU bar of 75%
Y/Y+SYNC
control pin:
0 V Y without sync supplied to
pin 5
5 V Y with sync supplied to pin 5
July 1994
20
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
LPFDR
CIRCUIT
DESCRIPTION
13
modulator control loop filter with
low leakage capacitors
14
FADJ
adjustment pin for 4.286 MHz:
potentiometer in series with two
resistors between ground and
pin 17
15
16
LPFDB
FLT
see pin 13
modulator control loop filter with
low leakage capacitors
filter control pin; 220 nF capacitor
to ground
July 1994
21
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
CIRCUIT
DESCRIPTION
17
Vref
2.5 V reference voltage
decoupling with 47 µF and 22 nF
capacitors
18
CHROMA
chrominance output
19
Vext
pin for external power supply, for
sandcastle pulse; Vext > 8 V; if not
used, the pin should be connected
to ground
20
SAND
sandcastle pulse
July 1994
22
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
CVBS
CIRCUIT
DESCRIPTION
21
22
23
24
composite SECAM output
NOTCH
pin for external notch filter
Y+SYNC IN
input of the delayed Y+SYNC
signal of the delay line; black level
must be 2 V
LPF4.4
see pin 13
loop filter for 4.40625 MHz
reference oscillator
July 1994
23
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
CIRCUIT
DESCRIPTION
25
26
27
Y+SYNC OUT
output of the delayed Y+SYNC
signal, connected to the delay line
via a resistor
XTAL/PLL
VIDENT
control pin:
without vertical identification:
0 V PLL tuning
5 V crystal tuning
with vertical identification:
2.5 V PLL tuning
VCO4.25
tuning of 4.25 MHz oscillator:
PLL tuning:
C = 270 pF to ground
crystal tuning:
crystal in series with a
capacitor to ground
external tuning:
signal via 1 nF capacitor in
series with a resistor
July 1994
24
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
COLKIL
CIRCUIT
DESCRIPTION
28
colour killing input:
0 V not active
5 V active, internal D'R and D'B
are blanked
29
CS
composite sync signal input;
amplitude <600 mV
(peak-to-peak value)
30
VSSD
digital ground
July 1994
25
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PIN
NAME
LPF4.25
CIRCUIT
DESCRIPTION
31
loop filter for 4.25 MHz reference
oscillator; connected to pin 17 if
crystal or external tuning
32
VDDD
supply voltage digital part; 5 V
nominal
July 1994
26
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
PACKAGE OUTLINE
29.4
28.5
10.7
10.2
3.8
max
4.7
max
3.2
2.8
0.51
min
0.18 M
0.32 max
1.6
max
0.53
max
1.778
(15x)
10.16
1.3 max
12.2
10.5
MSA270
32
17
16
9.1
8.7
1
Dimensions in mm.
Fig.12 Plastic shrink dual in-line package; 32 leads (400 mil) (SDIP32; SOT232-1).
July 1994
27
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
SOLDERING
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
July 1994
28
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
NOTES
July 1994
29
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
NOTES
July 1994
30
Philips Semiconductors
Preliminary specification
SECAM encoder
TDA8505
NOTES
July 1994
31
Philips Semiconductors – a worldwide company
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SCD32
© Philips Electronics N.V. 1994
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533061/1500/03/pp32
Date of release: July 1994
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Document order number:
Philips Semiconductors
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