TDA8787HL [NXP]
10-bit, 3.0 V analog-to-digital interface for CCD cameras; 10位， 3.0V，模拟 - 数字接口，用于CCD摄像机
| 型号： | TDA8787HL |
| 厂家： | 
NXP |
| 描述： | 10-bit, 3.0 V analog-to-digital interface for CCD cameras |
| 文件： | 总20页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8787
10-bit, 3.0 V analog-to-digital
interface for CCD cameras
1998 Oct 15
Preliminary specification
Supersedes data of 1998 Mar 27
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
FEATURES
APPLICATIONS
• Low-power, low-voltage CCD camera systems.
• Correlated Double Sampling (CDS), Automatic Gain
Control (AGC), 10-bit Analog-to-Digital Converter (ADC)
and reference regulator included
GENERAL DESCRIPTION
• Fully programmable via a 3-wire serial interface
• Sampling frequency up to 18 MHz
The TDA8787 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit ADC
together with its reference voltage regulator.
• AGC gain range of 36 dB (in steps of 0.1 dB)
• Low power consumption of only 190 mW (typ.)
• Power consumption in standby mode of 4.5 mW (typ.)
AGC gain is controlled via the serial interface.
• 3.0 V operation and 2.5 to 3.6 V operation for the digital
outputs
The ADC input clamp level is controlled via the serial
interface.
• Active control pulses polarity selectable via serial
interface
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.
• 8-bit DAC included for analog settings
• TTL compatible inputs, CMOS compatible outputs.
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
analog supply voltage
digital supply voltage
CONDITIONS
MIN.
2.7
TYP. MAX. UNIT
3.0
3.0
2.6
55
8
3.6
3.6
3.6
70
11
V
VCCD
VCCO
ICCA
2.7
2.5
−
V
digital outputs supply voltage
analog supply current
digital supply current
V
all clamps active
mA
mA
mA
ICCD
ICCO
−
digital outputs supply current
fpix = 18 MHz; CL = 20 pF;
−
1
2
input ramp response time is 800 µs
ADCres
ADC resolution
−
10
−
−
−
−
−
−
−
−
bits
mV
Vi(CDS)(p-p)
maximum CDS input voltage
(peak-to-peak value)
VCC = 2.85 V
650
800
18
5
VCC ≥ 3.0 V
−
mV
fpix(max)
fpix(min)
DRAGC
Ntot(rms)
maximum pixel rate
minimum pixel rate
AGC dynamic range
−
MHz
MHz
dB
−
−
36
0.25
total noise from CDS input to
ADC output
AGC gain = 0 dB; see Fig.8
VCCA = VCCD = VCCO = 3 V
−
LSB
Ptot
total power consumption
−
190
−
mW
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8787HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
1998 Oct 15
2
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e
PBK
CLK
OE
V
V
SHP
SHD
DGND3
2
AGND2 CLPOB CLPDM
AGND5
43
CCD3
1
CCA2
18
47
48
17
13
12
11
40
37
20
19
39
38
26
DGND1
V
CCD1
CDS CLOCK GENERATOR
DGND2
V
CCD2
OGND
7
8
CPCDS1
CPCDS2
CLAMP
36
35
34
33
32
31
30
29
28
27
D9
D8
COMPARATOR
42
41
4
V
CCA3
D7
D6
D5
D4
D3
D2
D1
D0
AGND3
AGC
CORRELATED
DOUBLE
SAMPLING
IN
DATA
FLIP-
FLOP
PRE-
BLANKING
OUTPUT
BUFFER
SHIFT
SHIFTER
10-bit ADC
CLAMP
DAC
V
6
5
ref
V
CCA1
9-BIT
REGISTER
7-BIT
25
44
TDA8787
V
REGISTER
CCO
AGND1
OFD DAC
9
OFDOUT
SERIAL
8-BIT
REGISTER
REGULATOR
DCLPC
INTERFACE
15
46
22
21
24
10
14
16
3
45
23
MGM541
OAGC
OAGCC
SCLK
VSYNC
TEST1 TEST2 TEST3 AGND4
SEN
SDATA
STDBY
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
PINNING
SYMBOL
VCCD3
PIN
DESCRIPTION
1
digital supply voltage 3
digital ground 3
DGND3
AGND4
IN
2
3
analog ground 4
4
input signal from CCD
analog ground 1
AGND1
VCCA1
CPCDS1
CPCDS2
OFDOUT
STDBY
PBK
5
6
analog supply voltage 1
clamp storage capacitor pin 1
clamp storage capacitor pin 2
7
8
9
analog output of the additional 8-bit control DAC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
standby mode control input (LOW: TDA8787 active; HIGH: TDA8787 standby)
pre-blanking control input
CLPDM
CLPOB
TEST1
TEST2
TEST3
AGND2
VCCA2
VCCD1
DGND1
SDATA
SCLK
SEN
clamp pulse input at dummy pixel
clamp pulse input at optical black
test pin input 1 (should be connected to AGND2)
test pin input 2 (should be connected to AGND1)
test pin input 3 (should be connected to AGND2)
analog ground 2
analog supply voltage 2
digital supply voltage 1
digital ground 1
serial data input for serial interface control
serial clock input for serial interface
strobe pin for serial interface
vertical sync pulse input
VSYNC
VCCO
OGND
D0
output supply voltage
digital output ground
ADC digital output 0 (LSB)
D1
ADC digital output 1
D2
ADC digital output 2
D3
ADC digital output 3
D4
ADC digital output 4
D5
ADC digital output 5
D6
ADC digital output 6
D7
ADC digital output 7
D8
ADC digital output 8
D9
ADC digital output 9 (MSB)
output enable control input (LOW: outputs active; HIGH: outputs in high impedance)
digital supply 2
OE
VCCD2
DGND2
CLK
digital ground 2
data clock input
1998 Oct 15
4
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
SYMBOL
PIN
DESCRIPTION
AGND3
VCCA3
41
42
43
44
45
46
47
48
analog ground 3
analog supply 3
AGND5
DCLPC
OAGC
OAGCC
SHP
analog ground 5
regulator decoupling pin
AGC output (test pin)
AGC complementary output (test pin)
preset sample-and-hold pulse input
data sample-and-hold pulse input
SHD
V
1
2
3
4
5
36
35
34
33
D9
D8
D7
D6
CCD3
DGND3
AGND4
IN
32 D5
31
AGND1
V
6
D4
CCA1
TDA8787
CPCDS1
CPCDS2
OFDOUT
7
30 D3
8
9
29 D2
28 D1
STDBY 10
PBK 11
27 D0
26 OGND
V
25
CLPDM 12
CCO
MGM542
Fig.2 Pin configuration.
1998 Oct 15
5
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
MAX.
+7.0
UNIT
note 1
note 1
note 1
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
output stages supply voltage
supply voltage difference
between VCCA and VCCD
between VCCA and VCCO
between VCCD and VCCO
input voltage
−0.3
−0.3
+7.0
+7.0
−1.0
−1.0
−1.0
−0.3
−
+1.0
+1.0
+1.0
+7.0
±10
V
V
V
V
Vi
referenced to AGND
Io
data output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
−55
−20
−
+150
+75
operating ambient temperature
junction temperature
150
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
76
K/W
1998 Oct 15
6
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
VCCD
VCCO
analog supply voltage
digital supply voltage
2.7
2.7
2.5
3.0
3.0
2.6
3.6
3.6
3.6
V
V
V
digital outputs supply
voltage
ICCA
ICCD
ICCO
analog supply current
digital supply current
all clamps active
−
−
−
55
8
70
11
2
mA
mA
mA
digital outputs supply
current
CL = 20 pF on all data
outputs; input ramp
frequency
1
Digital inputs
INPUTS: SHP, SHD, STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE AND PBK
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.6
V
2.2
−2
VCCD
+2
V
0 ≤ Vi ≤ VCCD
µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width
in number of pixels
AGC code = 383 for
maximum 4 LSB error
18
1.5
−
−
−
pixels
mS
−
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
2.7
3.5
−
OPTICAL BLACK CLAMP (DRIVEN BY CLPOB)
Gshift
gain from CPCDS1 and 2
to AGC inputs
0.27
ILSB(cp)
charge pump current for
±1 LSB error at ADC
output
AGC code = 0
−
−
±350
±10
−
−
µA
µA
AGC code = 383
Ipush(cp)
Ipull(cp)
available push current of
the charge pump
−
−
650
−
−
µA
µA
available pull current of
the charge pump
−650
1998 Oct 15
7
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum peak-to-peak
CDS input amplitude
(video signal)
VCC = 2.85 V
CC ≥ 3.0 V
650
−
−
−
mV
V
800
−
mV
Vreset(max)
Ii(IN)
tCDS(min)
th(IN-SHP)
maximum CDS input reset
pulse amplitude
500
−
−
mV
input current into pin IN
(pin 4)
at floating gate level
−1
11
3
−
+1
−
µA
ns
ns
CDS control pulses
minimum active time
video input = Vi(CDS)(p-p)
2 LSB error at ADC output
;
15
5
CDS input hold time
(pin IN) compared to
control pulse SHP
VCCA = VCCD = 30 V;
Tamb = 25 °C; see Fig.9
7
th(IN-SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
VCCA = VCCD = 30 V;
Tamb = 25 °C; see Fig.9
3
5
7
ns
Amplifier
DRAGC
AGC dynamic range
−
36
−
dB
dB
∆GAGC
maximum AGC gain step
−0.3
−
+0.3
Analog-to-Digital Converter (ADC)
LEi
integral linearity error
fpix = 18 MHz; ramp input
fpix = 18 MHz; ramp input
−
−
±1.3
±0.5
±2.5
±0.9
LSB
LSB
LEd
differential linearity error
Total chain characteristics (CDS + AGC + ADC)
fpix(max)
tCLKH
maximum pixel frequency
CLK pulse width HIGH
CLK pulse width LOW
18
15
15
10
−
−
−
−
−
−
−
−
MHz
ns
tCLKL
ns
td(SHD-CLK)
time delay between
SHD and CLK
see Fig.9
ns
tsu(PBK-CLK)
Vi(IN)
set-up time of PBK
compared to CLK
10
−
−
ns
video input dynamic signal AGC code = 00
for ADC full-scale output
800
−
−
−
−
mV
mV
AGC code = 383
12.7
Ntot(rms)
total output noise (RMS
value)
see Fig.8
AGC gain = 0 dB
AGC gain = 9 dB
−
0.25
0.8
−
−
LSB
LSB
mV
−
−
OCCD(max)
maximum offset between
CCD floating level and
CCD dark pixel level
−70
+70
Vn(i)(eq)(rms)
equivalent input noise
voltage (RMS value)
−
110
−
µV
1998 Oct 15
8
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control
DAC (OFD) output voltage
(peak-to-peak value)
Ri = 1 MΩ
−
1.0
−
V
VOFDOUT(0)
DC output voltage for
code 0
−
−
−
AGND
−
−
−
V
VOFDOUT(255) DC output voltage for
code 255
AGND + 1.0
250
V
TCDAC
DAC output range
ppm/°C
temperature coefficient
ZOFDOUT
IOFDOUT
DAC output impedance
−
−
2000
−
Ω
OFD output current drive static
−
100
µA
Digital outputs (fpix = 18 MHz; CL = 22 pF)
VOH
VOL
IOZ
HIGH-level output voltage IOH = −1 mA
LOW-level output voltage IOL = 1 mA
V
0
CCO − 0.5
−
−
−
VCCO
0.5
V
V
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
+20
µA
th(o)
td(o)
output hold time
output delay time
see Fig.9
11
−
−
−
ns
ns
ns
pF
CL = 22 pF; VCCO = 3.0 V
CL = 22 pF; VCCO = 2.7 V
28
27
−
tbf
tbf
22
−
CL
output load capacitance
−
Serial interface
fSCLK(max)
maximum frequency of
serial interface
5
−
−
MHz
1998 Oct 15
9
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
IN
N + 1
N + 2
N + 3
N
t
CDS(min)
2.2 V
SHP
SHD
0.6 V
t
h(IN-SHP)
t
CDS(min)
2.2 V
0.6 V
0.6 V
t
h(IN-SHD)
t
CLKH
2.2 V
CLK
0.6 V
0.6 V
t
d(SHD-CLK)
N − 1
50%
N
SDATA
t
h(o)
t
d(o)
2.2 V
0.6 V
PBK
MGM764
t
su(PBK-CLK)
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
1998 Oct 15
10
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
IN
N + 1
N + 2
N + 3
N
2.2 V
SHP
SHD
0.6 V
t
CDS(min)
2.2 V
t
h(IN-SHP)
2.2 V
0.6 V
t
t
CDS(min)
h(IN-SHD)
2.2 V
2.2 V
CLK
0.6 V
CLKL
t
t
d(SHD-CLK)
N − 1
50%
N
SDATA
t
h(o)
t
d(o)
2.2 V
0.6 V
PBK
FCE088
t
su(PBK-CLK)
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
MGM543
1.0
OFDOUT DAC
voltage
output
(V)
0
255
0
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
11
1998 Oct 15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
(1)
(1)
4 pixels
4 pixels
CLPOB
CLPDM
WINDOW
WINDOW
AGCOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
(2)
CLPDM
(active HIGH)
PBK
(active HIGH)
PBK window
MGM544
(1) In case the number of clamp pixels is limited to 18tW(clamp); otherwise this timing interval can be smaller.
(2) When dummy pixels are not available.
Fig.6 Line frequency timing diagram.
FCE057
42
handbook, halfpage
AGC
gain 36
(dB)
30
24
18
12
6
0
−6
0
64
128
192
256
320
384
AGC input code
Fig.7 AGC gain as a function of AGC input code.
12
1998 Oct 15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
FCE098
10
handbook, halfpage
N
tot(rms)
(LSB)
8
6
4
2
0
0
64
128
192
256
320
383
AGC code
Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account as no signal is inputted.
Fig.8 Total noise performance as a function of AGC gain.
1998 Oct 15
13
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
SDATA
SCLK
SHIFT REGISTER
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1
LSB
MSB
10
LATCH
SEN
SELECTION
8
9
7
6
CONTROL PULSE
POLARITY
AGC GAIN
LATCHES
ADC CLAMP
LATCHES
OFDOUT DAC
LATCHES
LATCHES
8-bit DAC
AGC control
ADC clamp
control
control pulses
polarity settings
MGM546
Fig.9 Serial interface block diagram.
t
su2
t
hd4
MSB
LSB
D0
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
SDATA
SCLK
SEN
t
t
su1
su3
t
hd3
MGM547
tsu1 = tsu2 = tsu3 = 10 ns (min.); thd3 = thd4 = 10 ns (min.).
Fig.10 Loading sequence of control input data via the serial interface.
14
1998 Oct 15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
Table 1 Serial interface programming
ADDRESS BITS
DATA BITS D9 TO D0
A1
A0
0
0
1
1
0
1
0
1
AGC gain control (D8 to D0); bit D9 should be set to logic 0
DAC OFDOUT output control (D7 to D0); bits D8 and D9 should be set to logic 0
ADC clamp reference control (D6 to D0); bits D7, D8 and D9 should be set to logic 0
control pulses (pins SHP, SHD, CLPDM, CLPOB, PBK and CLK) polarity settings
Table 2 Polarity settings
SYMBOL
PIN
SERIAL CONTROL BIT(1) ACTIVE EDGE OR LEVEL
SHP and SHD
CLK
47 and 48
D0
D1
D2
D3
D5
D6
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
40
12
13
11
24
CLPDM
CLPOB
PBK
VSYNC
Note
1. Bit D4 is not used.
Table 3 Standby selection
STDBY
ADC DIGITAL OUTPUTS D9 TO D0
ICCA + ICCO + ICCD (TYP.)
1
0
logic state LOW
active
1 mA
64 mA
1998 Oct 15
15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
APPLICATION DIAGRAM
V
V
CCD
CCA
100
nF
100
nF
1 µF
V
(2) (2)
CCD
(2)
CCD
1 µF
48 47 46 45 44 43 42 41 40 39 38 37
V
CCD3
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
V
36
35
34
33
32
31
30
29
28
27
26
25
CCD
DGND3
AGND4
IN
1 µF
2
3
4
AGND1
5
100
nF
V
CCA1
V
CCA
6
TDA8787HL
CPCDS1
CPCDS2
OFDOUT
STDBY
PBK
7
1 µF
8
9
10
11
12
1 µF
OGND
V
CLPDM
CCO
V
CCD
100
nF
13 14 15 16 17 18 19 20 21 22 23 24
V
CCD
(1)
serial
interface
100
nF
100
nF
V
V
CCD
CCA
MGM548
(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN-SHP) and th(IN-SHD) (see Chapter “Characteristics”).
Fig.11 Application diagram.
1998 Oct 15
16
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
94-12-19
97-08-01
SOT313-2
1998 Oct 15
17
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
•The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Oct 15
18
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Oct 15
19
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© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1998 Oct 15
Document order number: 9397 750 04259
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