TDA9852H [NXP]
I2C-bus controlled BTSC stereo/SAP decoder and audio processor; I2C总线控制BTSC立体声/ SAP解码器和音频处理器
| 型号： | TDA9852H |
| 厂家： | 
NXP |
| 描述： | I2C-bus controlled BTSC stereo/SAP decoder and audio processor |
| 文件： | 总40页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9852
I2C-bus controlled BTSC
stereo/SAP decoder and audio
processor
1997 Mar 11
Preliminary specification
Supersedes data of 1996 Feb 28
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
FEATURES
• Quasi alignment-free application due to automatic
adjustment of channel separation via I2C-bus
• High integration level with automatically tuned
integrated filters
• Input level adjustment I2C-bus controlled
• Alignment-free SAP processing
• dbx noise reduction circuit
• Power supply
GENERAL DESCRIPTION
The TDA9852 is a bipolar-integrated BTSC stereo
decoder with hi-fi audio processor (I2C-bus controlled) for
application in TV sets, VCRs and multimedia.
• I2C-bus transceiver.
Stereo decoder
• Stereo pilot PLL circuit with ceramic resonator,
automatic adjustment procedure for stereo channel
separation, two pilot thresholds selectable via I2C-bus.
Audio processor
• Selector for internal and external signals (line in)
• Automatic volume level control
(control range +6 to −15 dB)
• Interface for external noise reduction circuits
• Volume control (control range +16 to −71 dB)
• Special loudness characteristic automatically controlled
in combination with volume setting (control range 28 dB)
• Audio signal zero crossing detection between any
volume step switching
• Mute control at audio signal zero crossing
• Mute control via I2C-bus.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA9852
SDIP42 plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
SOT307-2
TDA9852H QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm
1997 Mar 11
2
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
LICENSE INFORMATION
A license is required for the use of this product. For further information, please contact
COMPANY
THAT Corporation
BRANCH
Licensing Operations
ADDRESS
734 Forest St.
Marlborough, MA 01752
USA
Tel.: (508) 229-2500
Fax: (508) 229-2590
Tokyo Office
405 Palm House, 1-20-2 Honmachi
Shibuya-ku, Tokyo 151
Japan
Tel.: (03) 3378-0915
Fax: (03) 3374-5191
QUICK REFERENCE DATA
SYMBOL
VCC
PARAMETER
CONDITIONS
MIN.
8.0
TYP. MAX. UNIT
supply voltage
supply current
8.5
75
250
500
−
9.0
95
−
V
ICC
−
mA
mV
mV
dB
dB
%
Vcomp(rms) input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −
VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −
−
GLA
input level adjustment control
stereo channel separation
total harmonic distortion L + R
signal handling (RMS value)
control range
−3.5
25
−
+4.0
−
αcs
fL = 300 Hz; fR = 3 kHz
fi = 1 kHz
35
0.2
−
THDL,R
VI, O(rms)
AVL
GC
−
THD < 0.5%
2
−
V
−15
−71
−
−
+6
+16
−
dB
dB
dB
volume control range
−
LB
maximum loudness boost
signal-to-noise ratio
fi = 40 Hz
17
S/N
line out (mono); Vo = 0.5 V (RMS)
CCIR noise weighting filter
(peak value)
−
−
60
73
−
−
dB
DIN noise weighting filter
(RMS value)
dBA
S/N
signal-to-noise ratio
audio section; Vo = 2 V (RMS);
gain = 0 dB
CCIR noise weighting filter
(peak value)
−
−
94
−
−
dB
DIN noise weighting filter
(RMS value)
107
dBA
1997 Mar 11
3
External Input Right
(EIR)
R3
C11
C10
Q1
C3
R1
R2
C4
C5
C7
C20
C16
C28
C8
C9
CERAMIC
RESONATOR
MURATA
C2
26
C6
34
C12
CSB503F58
LOR LIR
33 36
(28) (29) (32) (30) (31)
VIR
40
27
28
(24)
29 30
(25) (26)
31
(27)
32
35
5
(44)
37
(33)
38 39
(34) (35) (36)
41
(37)
(22) (23)
(38)
42
VOLUME
RIGHT
LOUDNESS
CONTROL
OUTR
OUT
RIGHT
STEREO DECODER
TDA9852
COMP
C1
(20)
24
DEMATRIX
STEREO/
SAP
SWITCH
AUTOMATIC
VOLUME AND
LEVEL CONTROL
INPUT
LEVEL
ADJUST
INPUT
SELECT
ZERO
CROSSING
+
EFFECTS
LINEOUT
SELECT
VOLUME
LEFT
LOUDNESS
CONTROL
(40)
1
STEREO
ADJUST
LOGIC
I2C
OUTL
SAP
DEMODULATOR
OUT
LEFT
DBX
SUPPLY
TRANSCEIVER
(14)
19
(13) (12)
18 17
(10)
15
(11) (9) (8) (7) (6) (5) (2)
(4)
9
(3) (19) (21) (1)
(17)
21
(18)
22
(43) (42)
(41)
2
16 14
13 12 11 10
7
8
23 25
6
20 (15)
(16)
4
3
(39)
R6
R7
C21
LIL
VIL
MHA309
LOL
C14
n.c.
C26
C29
C30
C27
SDA
SCL
C17
C18
C19
C22 C23 C24 C25
C15
C34
R4
R5
C47 C49
V
CC
External Input Left
(EIL)
AGND
DGND
The numbers given in parenthesis refer to the TDA9852H version.
ahdnbok,uflapegwidt
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Component list
Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENTS
VALUE
TYPE
REMARK
C1
C2
10 µF
470 nF
4.7 µF
220 nF
10 µF
2.2 µF
2.2 µF
15 nF
electrolytic
foil
63 V
C3
electrolytic
foil
63 V
C4
C5
electrolytic
electrolytic
electrolytic
foil
63 V; Ileak < 1.5 µA
C6
16 V
C7
63 V
C8
±5%
C9
15 nF
foil
±5%
C10
C11
C12
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C34
C47
C49
R1
2.2 µF
8.2 nF
150 nF
150 nF
100 µF
4.7 µF
4.7 µF
100 nF
10 µF
4.7 µF
47 nF
electrolytic
foil or ceramic
foil
16 V
±5% SMD 2220/1206
±5%
±5%
16 V
63 V
63 V
foil
electrolytic
electrolytic
electrolytic
foil
electrolytic
electrolytic
foil
63 V
63 V
±5%
1 µF
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
foil or ceramic
electrolytic
electrolytic
foil or ceramic
−
63 V
1 µF
63 V
10 µF
10 µF
2.2 µF
2.2 µF
4.7 µF
2.2 µF
8.2 nF
100 µF
220 µF
100 nF
2.2 kΩ
20 kΩ
2.2 kΩ
20 kΩ
2.2 kΩ
8.2 kΩ
63 V ±10%
63 V ±10%
16 V
63 V
63 V ±10%
16 V
±5% SMD 2220/1206
16 V
25 V
SMD 1206
R2
−
R3
−
R4
−
R5
−
R6
−
±2%
1997 Mar 11
5
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
COMPONENTS
VALUE
TYPE
−
REMARK
±2%
R7
Q1
160 Ω
CSB503F58
CSB503JF958
radial leads
alternative as SMD
PINNING
SYMBOL
OUTL
PINS
DESCRIPTION
SDIP42
QFP44
1
40
41
42
43
44
1
output, left channel
LDL
VIL
2
input loudness, left channel
input volume, left channel
output effects, left channel
automatic volume control capacitor
reference voltage 0.5VCC
3
EOL
CAV
4
5
Vref
6
LIL
7
2
input line control, left channel
AVL
SOL
LOL
CTW
CTS
8
3
input automatic volume control, left channel
output selector, left channel
output line control, left channel
capacitor timing wideband for dbx
capacitor timing spectral for dbx
capacitor wideband for dbx
capacitor spectral for dbx
variable emphasis output for dbx
variable emphasis input for dbx
capacitor noise reduction for dbx
capacitor mute for SAP
9
4
10
11
12
13
14
15
16
17
18
19
20
−
5
6
7
CW
8
CS
9
VEO
VEI
10
11
12
13
14
−
CNR
CM
CDEC
GND
AGND
DGND
SDA
SCL
VCC
COMP
VCAP
CP1
capacitor DC-decoupling for SAP
ground
15
16
17
18
19
20
21
22
23
24
25
26
27
analog ground
−
digital ground
21
22
23
24
25
26
27
28
29
30
31
serial data input/output (I2C-bus)
serial clock input (I2C-bus)
supply voltage
composite input signal
capacitor for electronic filtering of supply
capacitor for pilot detector
capacitor for pilot detector
capacitor for phase detector
capacitor for filter adjustment
ceramic resonator
CP2
CPH
CADJ
CER
CMO
capacitor DC-decoupling mono
1997 Mar 11
6
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
PINS
SYMBOL
DESCRIPTION
SDIP42
QFP44
CSS
32
33
34
35
36
37
38
39
40
41
42
−
28
29
30
31
32
33
34
35
36
37
38
39
capacitor DC-decoupling stereo/SAP
output line control, right channel
output selector, right channel
input automatic volume control, right channel
input line control, right channel
capacitor 2 pseudo function
capacitor 1 pseudo function
output effects, right channel
input volume, right channel
input loudness, right channel
output, right channel
LOR
SOR
AVR
LIR
CPS2
CPS1
EOR
VIR
LDR
OUTR
n.c.
not connected
V
1
2
33
32
31
C
PS2
ref
LIL
AVL
SOL
LOL
LIR
3
AVR
4
30 SOR
5
29
28
27
LOR
TDA9852H
C
6
C
TW
SS
C
7
C
TS
MO
C
8
26 CER
W
C
9
25
24
23
C
C
C
S
VEO
VEI
ADJ
PH
P2
10
11
MHA696
Fig.2 Pin configuration (QFP-version).
7
1997 Mar 11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
FUNCTIONAL DESCRIPTION
Stereo decoder
INPUT LEVEL ADJUSTMENT
The composite input signal is fed to the input level
adjustment stage. The control range is from
−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress
control 3 of Tables 5 and 6 and the level adjust setting of
Table 21 allows an optimum signal adjustment during the
set alignment. The maximum input signal voltage is
2 V (RMS).
handbook, halfpage
OUTL
LDL
VIL
1
2
3
4
5
6
7
8
9
42 OUTR
41 LDR
40 VIR
EOL
39 EOR
STEREO DECODER
C
38
37
C
C
AV
PS1
V
The output signal of the level adjustment stage is coupled
to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit.
The decoded sub-signal L − R is sent to the stereo/SAP
switch. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
The stereo channel separation is adjusted by an automatic
procedure to be performed during set production. For a
detailed description see Section “Adjustment procedure”.
The stereo identification can be read by the I2C-bus
(see Table 2). Two different pilot thresholds
ref
PS2
LIL
AVL
SOL
36 LIR
35 AVR
34 SOR
33 LOR
LOL 10
C
11
12
13
14
32
31
C
TDA9852
TW
SS
C
C
TS
MO
C
30 CER
W
C
29
28
27
26
25
C
C
C
C
V
S
ADJ
PH
P2
VEO 15
VEI 16
(data STS = 1; STS = 0) can be selected via the I2C-bus
(see Table 19).
C
17
18
19
NR
P1
SAP DEMODULATOR
C
M
CAP
The composite signal is fed from the output of the input
level adjustment stage to the SAP demodulator circuit
through a 5fH (fH = horizontal frequency) band-pass filter.
The demodulator level is automatically controlled.
The SAP demodulator includes internal noise and field
strength detectors that mute the SAP output in the event of
insufficient signal conditions. The SAP identification signal
can be read by the I2C-bus (see Table 2).
C
24 COMP
DEC
GND 20
SDA 21
23
V
CC
22 SCL
MHA310
SWITCH
The stereo/SAP switch feeds either the L − R signal or the
SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/switching circuit. Table 12
shows the different switch modes provided at the output
pins LOR and LOL.
Fig.3 Pin configuration (SDIP-version).
1997 Mar 11
8
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
dbx DECODER
EFFECTS
The circuit includes all blocks required for the noise
reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.
The audio processor section offers the following mode
selections: linear stereo, pseudo stereo, spatial stereo and
forced mono.The spatial mode provides an antiphase
crosstalk of 30% or 52% (switchable via I2C-bus;
see Table 10).
INTEGRATED FILTERS
VOLUME/LOUDNESS
The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.
The volume control range is from +16 dB to −71 dB in
steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume
control of each channel. The volume control blocks
operate in combination with the loudness control. The filter
is linear when maximum gain for volume control is
selected. The filter characteristic changes automatically
over a range of 28 dB down to a setting of −12 dB.
At −12 dB volume control the maximum loudness boost is
obtained. The filter characteristic is determined by external
components. The proposed application provides a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus
control (see Table 9). The left and right volume control
stages include two independent zero crossing detectors.
A change in volume is automatically activated but not
executed. The execution is enabled at the next zero
crossing of the signal. If a new volume step is activated
before the previous one has been processed, the previous
value will be executed first, and then the new value will be
activated. If no zero crossing occurs the next volume
transmission will enforce the last activated volume setting.
Audio processor
SELECTOR
The selector allows selecting either the internal line out
signals LOR or LOL (dematrix output) or the external line
in signals LIR and LIL and combines the left and right
signals in several modes (see Tables 5 and 6 for
subaddress and Table 11 for data). The input signal
capability of the line inputs (LIR/LIL) is 2 V (RMS).
The output of the selector is AC-coupled to the automatic
volume level control circuit via pins SOR/SOL and
AVR/AVL to avoid offset voltages.
AUTOMATIC VOLUME LEVEL CONTROL
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range of 0.1 to 1.1 V (RMS). The circuit
adjusts variations in modulation during broadcasting and
due to changes in the programme material. The function
can be switched off. To avoid audible ‘plops’ during the
permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay time can be changed via I2C-bus
(see Table 15). At power on, the discharged 4.7 µF
capacitor at CAV must be loaded by the internal decay
current. If AVL is chosen, this would result in an attenuated
AVL gain for about 10 seconds after power on. This can be
speeded up by choosing via I2C-bus an increased charge
current (about 10 times higher) for about the first
2 seconds after power on (see Table 6, CCD bit in
control 1 and Table 18).
The zero crossing is realized between adjoining steps and
between any steps, but not from any step to mute. In this
case the GMU bit is needed to use. In case only one
channel has to be muted, two steps are necessary.
The first step is a transmission of any step to −71 dB and
the second step is the −71 dB step to mute mode. The step
of −71 dB to mute mode has no zero crossing but this is
not relevant.
1997 Mar 11
9
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
• Effects, AVL, loudness off.
MUTE
• Line out setting bits: STEREO = 1, SAP = 0
(see Table 12)
The mute function can be activated independently with last
step of volume control at the left or right output. By setting
the general mute bit GMU via the I2C-bus all outputs are
muted. All channels include an independent zero cross
detector. The zero crossing mute feature can be selected
via bit TZCM:
• Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11)
• Start adjustment by transmission ADJ = 1 in register
ALI3; the decoder will align itself
• After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an
I2C-bus read operation from ALR1 and ALR2
TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero crossing.
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2
In the zero cross mode a change in the GMU polarity is
activated but not executed. The execution is enabled at
the next zero crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I2C-bus transmissions are
needed:
• Disconnect the capacitors of external inputs from
ground.
MANUAL ADJUSTMENT
a first transmission for mute execution
Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).
a second transmission about 100 ms later, which must
switch the zero crossing mode to forced mute
(TZCM = 0)
• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
a third transmission to reactivate the zero crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.
• Composite input L = 300 Hz; 14% modulation
• Adjust channel separation by varying wideband data
• Composite input L = 3 kHz; 14% modulation
• Adjust channel separation by varying spectral data
Adjustment procedure
• Iterative spectral/wideband operation for optimum
adjustment
COMPOSITE INPUT LEVEL ADJUSTMENT
• Store data in non-volatile memory.
Feed in from FM demodulator the composite signal with
100% modulation (25 kHz deviation) L + R; fi = 300 Hz.
Set input level control via I2C-bus monitoring line out
(500 mV ±20 mV). Store the setting in a non-volatile
memory.
TIMING CURRENT FOR RELEASE RATE
Due to possible internal and external spreading, the timing
current can be adjusted via I2C-bus, see Table 20, as
recommended by dbx.
AUTOMATIC ADJUSTMENT PROCEDURE
• Capacitors of external inputs LIL and LIR must be
grounded at EIL and EIR
• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via I2C-bus
1997 Mar 11
10
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Requirements for the composite input signal to ensure correct system performance
SYMBOL
PARAMETER
CONDITIONS
MIN.
162
TYP.
250
MAX. UNIT
COMPL+R(rms) composite input level for 100% measured at COMP
363
mV
modulation L + R; 25 kHz
deviation; fi = 300 Hz;
RMS value
∆COMP
composite input level
spreading under operating
conditions
T
amb = −20 to +70 °C; aging;
−0.5
−
+0.5
dB
power supply influence
Zo
output impedance
note 1
−
−
low-ohmic 5
kΩ
Hz
kHz
%
flf
low frequency roll-off
high frequency roll-off
25 kHz deviation L + R; −2 dB
−
−
−
−
5
fhf
25 kHz deviation L + R; −2 dB 100
−
THDL,R
total harmonic distortion L + R fi = 1 kHz; 25 kHz deviation
−
−
0.5
1.5
fi = 1 kHz; 125 kHz deviation;
note 2
%
S/N
signal-to-noise ratio
L + R/noise
CCIR 468-2 weighted quasi
peak; L + R; 25 kHz deviation;
fi = 1 kHz; 75 µs de-emphasis
critical picture modulation;
note 3
44
54
−
−
dB
with sync only
−
−
−
−
dB
dB
αSB
side band suppression mono
mono signal: 25 kHz deviation, 46
into unmodulated SAP carrier; fi = 1 kHz; side band: SAP
SAP carrier/side band
carrier frequency ±1 kHz
αSP
spectral spurious attenuation
L + R/spurious
50 Hz to 100 kHz;
mainly n × fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference
n = 1, 5
n = 4, 6
n = 2, 3
35
40
26
−
−
−
−
−
−
dB
dB
dB
Notes
1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input
impedance (see Chapter “Characteristics”, Section “Input level adjustment control”) must be taken into account.
2. In order to prevent clipping at over-modulation
(maximum deviation in the BTSC system for 100% modulation is 73 kHz).
3. For example colour bar or flat field white; 100% video modulation.
1997 Mar 11
11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
PARAMETER
MIN.
MAX.
UNIT
supply voltage
0
9.5
V
Vn
voltage of all other pins to pin VCC
operating ambient temperature
storage temperature
0
VCC
+70
+150
V
Tamb
Tstg
Ves
−20
−65
°C
°C
electrostatic handling; note 1
Note
1. Human body model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; Charge device model: C = 200 pF; R = 0 Ω; V = 300 V.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
SOT270-1
SOT307-2
43
60
K/W
K/W
1997 Mar 11
12
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
CHARACTERISTICS
All voltages are measured relative to GND; VCC = 8.5 V; Rs = 600 Ω; RL = 10 kΩ; CL = 2.5 nF; AC-coupled; fi = 1 kHz;
Tamb = 25 °C; gain control Gv = 0 dB; balance in mid position; loudness off; see Fig.1; unless otherwise specified.
SYMBOL
General
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VCC
ICC
supply voltage
8.0
8.5
75
9.0
V
supply current
−
−
95
mA
V
Vref
internal reference voltage at
pin Vref
4.25
−
Input level adjustment control
GLA
input level adjustment control
−3.5
−
−
+4.0
−
dB
dB
V
Gstep
Vi(rms)
step resolution
0.5
−
maximum input voltage level
(RMS value)
2
−
Zi
input impedance
29.5
35
40.5
kΩ
Stereo decoder
MPXL+R(rms) input voltage level for 100%
modulation L + R; 25 kHz
input level adjusted via I2C-bus
(L + R; fi = 300 Hz);
−
250
−
mV
deviation (RMS value)
monitoring LINE OUT
MPXL−R
input voltage level for 100%
modulation L − R; 50 kHz
deviation (peak value)
−
707
−
mV
MPX(max)
maximum headroom for L + R, fmod < 15 kHz; THD < 15%
L, R
9
−
−
−
dB
MPXpilot(rms) nominal stereo pilot voltage
level (RMS value)
−
50
mV
STon(rms)
pilot threshold voltage stereo
on (RMS value)
data STS = 1
data STS = 0
data STS = 1
data STS = 0
−
−
35
30
−
mV
mV
mV
mV
dB
−
−
SToff(rms)
pilot threshold voltage stereo
off (RMS value)
15
10
−
−
−
−
Hys
hysteresis
2.5
500
−
OUTL+R
output voltage level for 100% input level adjusted via I2C-bus 480
modulation L + R at LINE OUT (L + R; fi = 300 Hz);
monitoring LINE OUT
520
mV
αcs
stereo channel separation L/R aligned with dual tone 14%
at LINE OUT
modulation for each channel;
see Section “Adjustment
procedure” in Chapter
“Functional description”
fL = 300 Hz; fR = 3 kHz
fL = 300 Hz; fR = 8 kHz
fL = 300 Hz; fR = 10 kHz
25
20
15
35
30
25
−
−
−
dB
dB
dB
1997 Mar 11
13
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
fL, R
PARAMETER
CONDITIONS
14% modulation;
MIN.
TYP.
MAX. UNIT
L, R frequency response
fref = 300 Hz L or R
fi = 50 Hz to 10 kHz
fi = 12 kHz
−3
−
−
−
dB
dB
−
−
−3
0.2
THDL,R
S/N
total harmonic distortion L, R
at LINE OUT
modulation L or R
1.0
%
1% to 100%; fi = 1 kHz
signal-to-noise ratio
mono mode; CCIR 468-2
weighted; quasi peak;
500 mV output signal
50
60
−
dB
Stereo decoder, oscillator (VCXO); note 1
fo
nominal VCXO output
frequency (32fH)
with nominal ceramic
resonator
−
503.5
−
−
kHz
kHz
Hz
fof
spread of free-running
frequency
with nominal ceramic
resonator
500.0
±190
507.0
∆fH
capture range frequency
(nominal pilot)
±265
−
SAP demodulator; note 2
SAPi(rms)
nominal SAP carrier input
voltage level (RMS value)
15 kHz frequency deviation of
intercarrier
−
150
−
−
mV
mV
mV
SAPon(rms)
SAPoff(rms)
threshold voltage SAP on
(RMS value)
−
85
−
threshold voltage SAP off
35
−
(RMS value)
SAPhys
SAPLEV
hysteresis
−
−
2
−
−
dB
SAP output voltage level at
LINE OUT
mode selector in position
SAP/SAP; fmod = 300 Hz;
100% modulation
500
mV
fres
frequency response
14% modulation;
50 Hz to 8 kHz; fref = 300 Hz
−3
−
−
dB
%
THD
total harmonic distortion
fi = 1 kHz
−
0.5
2.0
1997 Mar 11
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
LINE OUT at pins LOL and LOR
Vo(rms)
nominal output voltage
(RMS value)
100% modulation
−
500
−
−
mV
dB
HEADo
Zo
output headroom
9
−
output impedance
−
80
120
Ω
VO
DC output voltage
0.45VCC 0.5VCC
0.55VCC
V
RL
output load resistance
output load capacitance
crosstalk L, R into SAP
5
−
−
kΩ
nF
dB
CL
−
−
2.5
−
αct
100% modulation; fi = 1 kHz;
L or R; mode selector switched
to SAP/SAP
50
75
crosstalk SAP into L, R
100% modulation; fi = 1 kHz;
SAP; mode selector switched
to stereo
50
70
−
dB
dB
∆VST-SAP
output voltage difference if
switched from L, R to SAP
250 Hz to 6.3 kHz
−
−
3
dbx noise reduction circuit
tadj stereo adjustment time
see Section “Adjustment
procedure” in Chapter
“Functional description”
−
−
−
1
s
Is
nominal timing current for
nominal release rate of
spectral RMS detector
Is can be measured at pin CTS
via current meter connected to
1⁄2VCC + 1 V
24
−
µA
∆Is
spread of timing current
timing current range
−15
−
−
+15
−
%
Is range
It
7 steps via I2C-bus
±30
1⁄3Is
%
timing current for release rate
of wideband RMS detector
−
−
µA
Relrate
nominal RMS detector
release rate
nominal timing current and
external capacitor values
wideband
spectral
−
−
125
381
−
−
dB/s
dB/s
1997 Mar 11
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Circuit section from pins LIL and LIR to pins OUTL and OUTR; note 3
B
roll-off frequencies
C6, C7, C10, C26, C27 and
C29 = 2.2 µF; Zi = Zi(min)
low frequency (−3 dB)
−
−
20
Hz
kHz
%
high frequency (−0.5 dB)
20
−
−
THD
total harmonic distortion
Vi = 1000 mV; Gv = 0 dB;
−
0.2
0.5
AVL on
Vi = 2000 mV; Gv = 0 dB;
AVL on
−
−
−
0.2
0.5
−
%
%
%
Vi = 1000 mV; Gv = 0 dB;
AVL off
0.02
0.02
Vi = 2000 mV; Gv = 0 dB;
−
AVL off
RR
ripple rejection
Vr(rms) < 200 mV; fi = 100 Hz
notes 4 and 5
47
50
−
−
dB
dB
αct
crosstalk between bus inputs
and signal outputs
−
110
Vno
noise output voltage
CCIR 468-2 weighted; quasi
peak; AVL off; loudness off;
Gv = 0 dB
−
−
40
8
80
µV
µV
measured in dBA; AVL off;
loudness off; Gv = 0 dB
−
αcs
channel separation
Vi = 1 V; fi = 1 kHz
75
75
−
−
−
−
dB
dB
Vi = 1 V; fi = 12.5 kHz
Effect controls
αspat1
αspat2
ϕ
anti-phase crosstalk by spatial
effect
−
−
−
52
30
−
−
−
−
%
%
−
phase shift by pseudo-stereo
see Fig.4
1997 Mar 11
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Automatic volume level control (AVL)
Zi
input impedance
8.8
11.0
tbf
13.2
kΩ
Vi(rms)
maximum input voltage
(RMS value)
THD < 0.2%
2
−
V
Gv
gain, maximum boost
maximum attenuation
5
6
7
dB
dB
dB
14
−
15
1.5
16
−
Gstep
equivalent step width between
the input stages
(soft switching system)
Viop(rms)
input level at maximum boost
(RMS value)
−
0.1
−
V
input level at maximum
attenuation (RMS value)
−
1.125
200
−
−
V
Vo(rms)
output level in AVL operation
(RMS value)
see Fig.5
160
−
250
6
mV
mV
VDC OFF
DC offset between different
gain steps
voltage at pin CAV
6.50 to 6.33 V or
6.33 to 6.11 V or
6.11 to 5.33 V or
5.33 to 2.60 V; note 6
Ratt
discharge resistors for attack
time constant
AT1 = 0; AT2 = 0; note 7
AT1 = 1; AT2 = 0; note 7
AT1 = 0; AT2 = 1; note 7
AT1 = 1; AT2 = 1; note 7
340
590
0.96
1.7
420
730
1.2
2.1
2.0
tbf
520
910
1.5
2.6
2.4
−
Ω
Ω
kΩ
kΩ
µA
µA
Idec
charge current for decay time normal mode; CCD = 0; note 8 1.6
power-on speed-up; CCD = 1;
−
note 8
Selector from pins LOL, LOR, LIL and LIR to pins SOL and SOR
Zi
input impedance
16
86
80
2
20
96
96
2.3
24
−
kΩ
dB
dB
V
αs
input isolation of one selected Vi = 1 V; fi = 1 kHz
source to the other input
Vi = 1 V; fi = 12.5 kHz
−
Vi(rms)
maximum input voltage
(RMS value)
THD < 0.5%
−
VDC OFF
DC offset voltage at selector
output by selection of any
inputs
−
−
25
mV
Zo
RL
CL
Gv
output impedance
−
5
0
−
80
−
120
−
Ω
output load resistance
output load capacitance
voltage gain, selector
kΩ
nF
dB
−
2.5
−
0
1997 Mar 11
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Audio control part; input pins VIL and VIR to pins OUTX and OUTS
Zi
volume input impedance
output impedance
8.0
10.0
80
12.0
kΩ
Ω
Zo
−
120
−
RL
output load resistance
output load capacitance
5
−
kΩ
nF
V
CL
0
−
2.5
−
Vi(rms)
maximum input voltage
(RMS value)
THD < 0.5%
2.0
2.15
Vno
noise output voltage
CCIR 468-2 weighted;
quasi peak
Gv = 16 dB
Gv = 0 dB
−
−
−
−
−
−
−
110
33
10
16
71
1
220
50
−
µV
µV
µV
dB
dB
dB
dB
mute position
Gc
total continuous control range maximum boost
maximum attenuation
−
−
Gstep
step resolution
−
step error between adjoining
step
−
0.5
∆Ga
attenuator set error
Gv = +16 to −50 dB
Gv = −51 to −71 dB
Gv = +16 to −50 dB
−
−
2
dB
−
−
3
dB
∆GL
gain tracking error
mute attenuation
−
−
2
dB
αm
80
−
−
−
dB
VDC OFF
DC step offset between any
adjacent step
Gv = +16 to 0 dB
Gv = 0 to −71 dB
Gv = +16 to +1 dB
Gv = 0 to −71 dB
0.2
−
10.0
5
mV
mV
mV
mV
−
DC step offset between any
step to mute
−
2
15
10
−
1
Loudness control part
LB maximum loudness boost
loudness on; referred to
loudness off; boost is
determined by external
components; see Fig.6
fi = 40 Hz
−
17
4.5
−
−
dB
dB
fi = 10 kHz
−
−
LG
Muting at power supply drop for OUTR and OUTS
VCC-DROP supply drop for mute active
loudness control range
−12
+16
−
V
CAP − 0.7 −
V
Power-on reset; note 9
VRESET(STA) start of reset voltage
increasing supply voltage
decreasing supply voltage
increasing supply voltage
−
−
5
6
2.5
5.8
6.8
V
V
V
4.2
5.2
VRESET(END) end of reset voltage
1997 Mar 11
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Digital part (I2C-bus pins); note 10
VIH
VIL
IIH
HIGH level input voltage
LOW level input voltage
HIGH level input current
LOW level input current
LOW level output voltage
3
−
−
−
−
−
VCC
V
−0.3
−10
−10
−
+1.5
+10
+10
+0.4
V
µA
µA
V
IIL
VOL
IIL = 3 mA
Notes to the characteristics
1. The oscillator is designed to operate together with MURATA resonator CSB503F58. Change of the resonator supplier
is possible, but the resonator specification must be close to CSB503F58.
2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.
3. Frequency range 20 Hz to 20 kHz; select in to input line control; effects: linear stereo.
Vbus(p-p)
4. Crosstalk: 20 log
--------------------
Vo(rms)
5. The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).
6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.
7. Attack time constant = CAV × Ratt.
–G1
–G2
----------
----------
C
AV × 0.76 V 10 20 – 10 20
8. Decay time =
-------------------------------------------------------------------------------
Idec
Example: CAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s.
9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver
is in the reset position.
10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it”
(order number 9398 393 40011).
1997 Mar 11
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
I2C-BUS PROTOCOL
I2C-bus format to read (slave transmits data)
S
SLAVE ADDRESS
R/W
A
DATA
MA
DATA
P
Table 1 Explanation of I2C-bus format to read (slave transmits data)
NAME
DESCRIPTION
S
START condition; generated by the master
101 101 1
Standard SLAVE ADDRESS (MAD)
R/W
A
1 (read); generated by the master
acknowledge; generated by the slave
slave transmits an 8-bit data word
acknowledge; generated by the master
STOP condition; generated by the master
DATA
MA
P
Table 2 Definition of the transmitted bytes after read condition
MSB
LSB
D0
FUNCTION
BYTE
D7
D6
D5
D4
D3
D2
D1
Alignment read 1
Alignment read 2
ALR1
ALR2
Y
Y
SAPP
SAPP
STP
STP
A14
A24
A13
A23
A12
A22
A11
A21
A10
A20
Table 3 Function of the bits in Table 2
BITS
FUNCTION
STP
stereo pilot identification (stereo received = 1)
SAP pilot identification (SAP received = 1)
stereo alignment read data
for wideband expander
SAPP
A1X to A2X
A1X
A2X
for spectral expander
Y
indefinite
The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next
data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word
ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.
1997 Mar 11
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
I2C-bus format to write (slave receives data)
S
SLAVE ADDRESS
R/W
A
SUBADDRESS
A
DATA
A
P
Table 4 Explanation of I2C-bus format to write (slave receives data)
NAME
DESCRIPTION
S
START condition
101 101 1
Standard SLAVE ADDRESS (MAD)
R/W
0 (write)
A
acknowledge; generated by the slave
see Table 5
SUBADDRESS (SAD)
DATA
P
see Table 6
STOP condition
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5 Subaddress second byte after MAD
MSB
D7
LSB
D0
FUNCTION
Volume right
REGISTER
D6
D5
D4
D3
D2
D1
VR
VL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
Volume left
Control 1 (note 1)
Control 2
CON1
CON2
CON3
ALI1
ALI2
ALI3
Control 3
Alignment 1
Alignment 2
Alignment 3
Note
1. In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1.
Table 6 Definition of third byte, third byte after MAD and SAD
MSB
LSB
D0
FUNCTION
Volume right
REGISTER
D7
0
D6
VR6
D5
VR5
VL5
D4
D3
D2
D1
VR
VL
VR4
VL4
CCD
1
VR3
VL3
0
VR2
VL2
SC2
EF2
L2
VR1
VL1
SC1
EF1
L1
VR0
VL0
SC0
EF0
L0
Volume left
Control 1
0
VL6
CON1
CON2
CON3
ALI1
ALI2
ALI3
GMU
AVLON
LOFF
Control 2
SAP STEREO TZCM
LMU
L3
Control 3
0
0
0
0
0
0
Alignment 1
Alignment 2
Alignment 3
0
A14
A24
0
A13
A23
1
A12
A22
TC2
A11
A21
TC1
A10
A20
TC0
STS
ADJ
0
0
AT1
AT2
1997 Mar 11
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Table 7 Function of the bits in Table 6
BITS
FUNCTION
VR0 to VR6
VL0 to VL6
GMU
volume control right
volume control left
mute control for all outputs (generate mute)
AVL on/off
AVLON
CCD
increased AVL decay current on/off
switch loudness on/off
LOFF
SC0 to SC2
STEREO, SAP
TZCM
selection between line in and line out
mode selection for line out
zero cross mode in mute operation (right and left output stage)
mute control for line out
LMU
EF0 to EF2
L0 to L3
ADJ
selection between mono, stereo linear, spatial stereo and pseudo mode
input level adjustment
stereo adjustment on/off
A1X to A2X
A1X
stereo alignment data
for wideband expander
A2X
for spectral expander
AT1 and AT2
TC0 to TC2
STS
attack time at AVL
timing current alignment data
stereo level switch
Table 8 Volume setting
DATA
FUNCTION
Gv (dB)
V6
V5
V4
V3
V2
V1
V0
16
15
14
13
12
11
10
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
7
6
5
4
3
2
1
1997 Mar 11
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
DATA
V3
FUNCTION
Gv (dB)
V6
V5
V4
V2
V1
V0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
−16
−17
−18
−19
−20
−21
−22
−23
−24
−25
−26
−27
−28
−29
−30
−31
−32
−33
−34
−35
−36
−37
−38
1997 Mar 11
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
DATA
V3
FUNCTION
Gv (dB)
V6
V5
V4
V2
V1
V0
−39
−40
−41
−42
−43
−44
−45
−46
−47
−48
−49
−50
−51
−52
−53
−54
−55
−56
−57
−58
−59
−60
−61
−62
−63
−64
−65
−66
−67
−68
−69
−70
−71
Mute
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1997 Mar 11
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Table 9 Loudness setting
Table 11 Selector setting
CHARACTERISTIC
DATA LOFF
DATA
FUNCTION(1)
With loudness
Linear
0
1
SC2
SC1
SC0
Inputs LOR and LOL
Inputs LOR and LOR
Inputs LOL and LOL
Inputs LOL and LOR
Inputs LIR and LIL
Inputs LIR and LIR
Inputs LIL and LIL
Inputs LIL and LIR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 10 Effects setting
DATA
EF1
FUNCTION
EF2
EF0
Stereo linear on
Pseudo on
0
0
0
0
0
1
0
1
0
Spatial stereo;
30% anti-phase crosstalk
Note
Spatial stereo;
50% anti-phase crosstalk
0
1
1
1
1
1
1. Input connected to outputs SOR and SOL.
Forced mono
Table 12 Switch setting at line out
LINE OUT SIGNALS AT
DATA
SETTING BITS
STEREO SAP
TRANSMISSION STATUS
INTERNAL SWITCH, READABLE BITS: STP, SAPP
LOL
SAP
LOR
SAP
SAP received
1
1
Mute
Left
mute
right
no SAP received
STEREO received
no STEREO received
SAP received
1
1
1
0
0
0
1
0
0
1
1
0
Mono
Mono
Mono
Mono
mono
SAP
mute
mono
no SAP received
independent
Table 13 Zero cross detection setting
FUNCTION
DATA TZCM
Direct mute control
0
1
Mute control delayed until the next zero crossing
Table 14 Mute setting
DATA
GMU
DATA
LMU
FUNCTION
FUNCTION
Forced mute at OUTR, OUTL and OUTS
Audio processor controlled outputs
1
0
forced mute at LOR and LOL
1
0
stereo processor controlled outputs
1997 Mar 11
25
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Table 15 AVL attack time
Table 21 Level adjust setting
DATA
DATA
GL
(dB)
FUNCTION
AT1
AT2
L3
L2
L1
L0
Ratt = 420 Ω
Ratt = 730 Ω
0
1
0
1
0
0
1
1
+4.0
+3.5
+3.0
+2.5
+2.0
+1.5
+1.0
+0.5
0.0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R
att = 1200 Ω
att = 2100 Ω
R
Table 16 ADJ bit setting
FUNCTION
Stereo decoder operation mode
DATA
0
1
Auto adjustment of channel separation
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
−3.5
Table 17 AVLON bit setting
FUNCTION
DATA
Automatic volume control off
Automatic volume control on
0
1
Table 18 CCD bit setting
FUNCTION
DATA
Load current for normal AVL decay time
Increased load current
0
1
Table 19 STS bit setting (pilot threshold stereo on)
FUNCTION DATA
STon ≤ 35 mV
STon ≤ 30 mV
1
0
Table 20 Timing current setting
DATA
TC1
FUNCTION
IS RANGE
TC2
TC0
+30%
+20%
+10%
Nominal
−10%
−20%
−30%
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1997 Mar 11
26
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Table 22 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2
DATA
FUNCTION
D4
D3
D2
D1
D0
AX4
AX3
AX2
AX1
AX0
Gain increase
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Nominal gain
Gain decrease
1997 Mar 11
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
MHA311
0
(1)
phase
(degree)
(2)
−100
(3)
−200
−300
−400
2
3
4
5
10
10
10
10
10
f (Hz)
(1) see Table 23.
(2) see Table 23.
(3) see Table 23.
Fig.4 Pseudo (phase in degrees) as a function of frequency (left output).
Table 23 Explanation of curves in Fig.4
CAPACITANCE AT PIN CPS1
CAPACITANCE AT PIN CPS2
(nF)
CURVE
EFFECT
(nF)
1
2
3
15
5.6
5.6
15
47
68
normal
intensified
more intensified
1997 Mar 11
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
MHA312
300
7
V
V
CAV
(V)
o(rms)
(mV)
(1)
(2)
6
250
200
5
4
3
2
1
(3)
160
100
10
−2
−1
10
1
10
V
(V)
I(rms)
(1) VCAV
AVL measured at pin EOL/EOR.
Y1 axis output level in AVL operation with typically 200 mV.
(2) Vo max(rms)
(3) Vo min(rms)
Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to −15 dB.
Fig.5 Automatic level control diagram.
MHA313
25
16
14
15
5
9
4
−1
−6
−5
−11
−16
−21
−26
−31
−15
−25
−36
−35
2
3
4
10
10
10
10
f (Hz)
Fig.6 Volume control with loudness (including low roll-off frequency).
29
1997 Mar 11
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
INTERNAL PIN CONFIGURATIONS
1
4.25 V
+
2
4.25 V
+
1.33 kΩ
80 Ω
MHA315
MHA314
Fig.7 Pins OUTL, SOL, SOR and OUTR.
Fig.8 Pins LDL and LDR.
3
4.25 V
4
4.25 V
+
+
10.58 kΩ
4.8 kΩ
15
kΩ kΩ
6.8
MHA317
MHA316
Fig.9 Pins VIL and VIR.
Fig.10 Pins EOL and EOR.
6
+
5
+
3.4
kΩ
3.4
kΩ
MHA318
MHA319
Fig.11 Pin CAV
.
Fig.12 Pin Vref.
1997 Mar 11
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
8
4.25 V
1
2
+
7
4.25 V
+
3
1.75 kΩ
20 kΩ
20 kΩ
MHA320
8
MHA321
Fig.13 Pins LIL and LIR.
Fig.14 Pins AVL and AVR.
10
4.25 V
+
11
+
5 kΩ
MHA323
MHA322
Fig.15 Pins LOL and LOR.
Fig.16 Pins CTW and CTS
.
13 4.25 V
15
+
+
6
kΩ
MHA325
MHA324
Fig.17 Pins CW and CS.
Fig.18 Pin VEO.
1997 Mar 11
31
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
16
17 4.25 V
+
+
600 Ω
10
MHA327
kΩ
MHA326
Fig.19 Pin VEI.
Fig.20 Pin CNR.
18
+
19 4.25 V
+
MHA329
20 kΩ
20 kΩ
MHA328
Fig.21 Pin CM.
Fig.22 Pin CDEC.
21 5 V
22 5 V
1.8 kΩ
1.8 kΩ
MHA331
MHA330
Fig.23 Pin SDA.
Fig.24 Pin SCL.
1997 Mar 11
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
24 4.25 V
+
23
apply +8.5 V to this pin
+
MHA332
30
kΩ
MHA333
Fig.25 Pin VCC
.
Fig.26 Pin COMP.
25
26 4.25 V
+
+
4.7
kΩ
300 Ω
3.5
kΩ
5 kΩ
MHA335
MHA334
Fig.27 Pin VCAP
.
Fig.28 Pin CP1.
27 4.25 V
28 4.25 V
+
+
8.5 12
MHA336
kΩ
kΩ
MHA337
10 kΩ
10 kΩ
Fig.29 Pin CP2.
Fig.30 Pin CPH.
1997 Mar 11
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
30
29
+
+
3
kΩ
MHA339
MHA338
Fig.31 Pin CADJ
.
Fig.32 Pin CER.
38
31 4.25 V
+
+
15
kΩ
10 kΩ
10 kΩ
MHA341
MHA340
Fig.33 Pins CMO and CSS
.
Fig.34 Pins CPS1 and CPS2.
1997 Mar 11
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
PACKAGE OUTLINES
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
D
M
E
A
2
A
L
A
1
c
e
(e )
1
w M
Z
b
1
M
H
b
42
22
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
2
max.
(1)
(1)
Z
1
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
3.2
2.9
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-02-13
95-02-04
SOT270-1
1997 Mar 11
35
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
1997 Mar 11
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
SDIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
REPAIRING SOLDERED JOINTS
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
QFP
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering techniques are suitable for all QFP
packages.
REPAIRING SOLDERED JOINTS
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Mar 11
37
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 11
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
TDA9852
NOTES
1997 Mar 11
39
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874
Indonesia: see Singapore
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp40
Date of release: 1997 Mar 11
Document order number: 9397 750 01766
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