TDA9853 [NXP]
I2C-bus controlled economic BTSC stereo decoder and audio processor; I2C总线控制的经济BTSC立体声解码器和音频处理器
| 型号： | TDA9853 |
| 厂家： | 
NXP |
| 描述： | I2C-bus controlled economic BTSC stereo decoder and audio processor |
| 文件： | 总28页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9853H
I2C-bus controlled economic BTSC
stereo decoder and audio
processor
Product specification
2000 Dec 11
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
FEATURES
• Voltage Controlled Amplifier (VCA) noise reduction
circuit
• Stereo or mono selectable at the AF outputs
• Stereo pilot PLL circuit with ceramic resonator
• Automatic pilot cancellation
GENERAL DESCRIPTION
The TDA9853H is a bipolar-integrated BTSC stereo
decoder and audio processor for application in TV sets,
VCRs and multimedia PCs.
• I2C-bus transceiver.
Audio processor
• Selector for internal and external signals (line in)
• Automatic Volume Level (AVL) control
(control range +6 to −15 dB)
• Volume control (control range +12 to −63 dB)
• Mute control via I2C-bus
• 4 fixed tone settings.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TDA9853H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 × 14 × 2.2 mm SOT205-1
2000 Dec 11
2
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
7.8
TYP. MAX. UNIT
VCC
8
9
V
ICC
supply current
25
33
500
45
−
mA
mV
Vo(rms)
output voltage (RMS value)
composite input voltage 250 mV (RMS)
for 100% modulation L + R
−
(25 kHz deviation); fmod = 300 Hz
αcsL,R
THDL,R
S/N
stereo channel separation
L and R
14% modulation; fL = 300 Hz; fR = 3 kHz 15
20
−
dB
%
total harmonic distortion
L and R
signal-to-noise ratio at line out mono via I2C-bus; referenced to 500 mV
100% modulation L or R; fmod = 1 kHz
−
0.2
1
and at AF output
output signal; volume 0 dB
CCIR 468-2 weighted; quasi peak
DIN noise weighting filter (RMS value)
THD < 0.5%
50
−
60
73
−
−
dB
dBA
V
−
VI, O(rms) signal handling (RMS value)
2
−
AVL
Gc
AVL control range
volume control range
linear tone control
−15
−63
−
−
+6
+12
−
dB
dB
dB
dB
−
Llinear
0
Lbass(max) tone control with maximum
bass
referenced to linear position;
fmod = 20 Hz
10
12
−
Lbass(min) tone control with minimum
bass
referenced to linear position;
fmod = 20 Hz
3.5
6
5
−
−
−
dB
dB
dB
Ltreble(max) tone control with maximum
treble
referenced to linear position;
fmod = 20 kHz
8
Ltreble(min) tone control with minimum
treble
referenced to linear position;
−
−1.5
fmod = 20 kHz
2000 Dec 11
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ahdnbok,uflapegwidt
External Input Right
(EIR)
C3
C4
C5
C6
C7
C8
C10
C11
Q1
R1
C9
C12
C2
P2
C
C
2
C
3
C
C
C
SS
CER
43
VAR
VIR
24
TC1R TC2R BCR
LOR
25
LIR
26
AV
29
P1
PH
42
MO
23
21
20
19
5
6
AUTOMATIC
VOLUME
AND
LEVEL CONTROL
C1
VOLUME
RIGHT
CONTROL
TONE
RIGHT
CONTROL
DEMATRIX
AND
MODE SELECT
composite
baseband
input
4
L + R
COMP
FDI
18
INPUT
SELECT
STEREO DECODER
OUTR
35
33
L − R
TDA9853H
R2
DETECTOR
AND
VOLTAGE CONTROLLED
AMPLIFIER
FILTER
AND
REFERENCE
VOLUME
LEFT
CONTROL
TONE
LEFT
CONTROL
2
16
FDO
I C-BUS
SUPPLY
OUTL
TRANSCEIVER
R3
32
31
C
30
41
28
V
36
27
V
9
8
7
40 39 38 37 11
VAL
10
13
14
15
BPU
TW
AGND
LOL LIL
R
VIL
TC1L TC2L BCL
W
CAP
ref
FR
MAD
SCL
C23
C22
C21
C20
C19
C15
C14
C18
C17
R4
C16
C13
SDA
V
CC
MHB789
DGND
External Input Left
(EIL)
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
Component list
Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENT VALUE TYPE REMARK
C1
2.2 µF
220 nF
2.2 µF
220 nF
2.2 µF
2.2 µF
2.2 µF
4.7 µF
2.2 µF
3.3 nF
150 pF
56 nF
electrolytic
foil
63 V
63 V
C2
C3
electrolytic
foil
C4
C5
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
foil
63 V
63 V
63 V
C6
C7
C8
63 V ±10%
C9
63 V
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
R1
foil
foil
56 nF
foil
150 pF
3.3 nF
2.2 µF
2.2 µF
100 µF
100 µF
10 µF
foil
foil
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
electrolytic
foil
63 V
63 V
16 V
16 V
63 V
63 V
1 µF
4.7 nF
22 nF
foil
3.3 kΩ
15 kΩ
1.3 kΩ
100 kΩ
R2
R3
R4
Q1
CSB503F58
radial leads
CSB503JF958
alternative as SMD
2000 Dec 11
5
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
not connected
VIR
LOR
LIR
24 volume control input; right channel
25 line output; right channel
26 line input; right channel
n.c.
1
2
3
4
5
6
7
8
9
CP2
connector 2 for pilot detector capacitor
connector 1 for pilot detector capacitor
composite input signal
CP1
Vref
27 reference voltage (0.5VCC)
COMP
CMO
CSS
VCAP
28 capacitor for electronic filtering of
supply
capacitor for DC-decoupling mono
capacitor for DC-decoupling stereo
resistor for filter reference
CAV
TW
CW
29 capacitor for AVL
30 capacitor timing
RFR
31 capacitor for VCA and band-pass filter
lower corner frequency
LIL
line input; left channel
LOL
VIL
line output; left channel
BPU
32 band-pass filter upper corner
frequency
10 volume control input; left channel
11 AVL output; left channel
12 not connected
VAL
FDO
n.c.
33 fixed de-emphasis output
34 not connected
n.c.
TC1L
TC2L
BCL
OUTL
n.c.
13 treble capacitor 1; left channel
14 treble capacitor 2; left channel
15 bass capacitor; left channel
16 left channel output
FDI
35 fixed de-emphasis input
36 analog ground
AGND
DGND
SDA
MAD
37 digital ground
38 serial data input/output
17 not connected
39 programmable address bit
(module address)
OUTR
BCR
TC2R
TC1R
n.c.
18 right channel output
19 bass capacitor; right channel
20 treble capacitor 2; right channel
21 treble capacitor 1; right channel
22 not connected
SCL
VCC
CPH
CER
n.c.
40 serial clock input
41 supply voltage
42 capacitor for phase detector
43 ceramic resonator
44 not connected
VAR
23 AVL output; right channel
2000 Dec 11
6
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
n.c.
1
2
3
4
5
6
7
8
9
33 FDO
32 BPU
C
P2
C
31
C
W
P1
COMP
30 TW
C
29
28
27
C
V
MO
AV
TDA9853H
C
SS
CAP
ref
R
V
FR
LIL
26 LIR
25 LOR
24 VIR
23 VAR
LOL
VIL 10
VAL 11
MHB790
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Automatic volume level control
Stereo decoder
The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range between 0.1 to 1.1 V (RMS). The
circuit adjusts variations in modulation during broadcasting
and because of changes in the programme material; this
function can be switched off. To avoid audible plops during
the permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay times can be changed via the I2C-bus.
The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator. The
main L + R signal passes a 75 µs fixed de-emphasis filter
and is fed into the dematrix circuit. The decoded sub-signal
L − R is applied to the Volume Controlled Amplifier (VCA)
circuit. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
Mode selection
The L − R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via
the I2C-bus (see Table 9).
Integrated filters
The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled by the filter reference circuit via
the external resistor R4.
The dematrix outputs can be muted via the I2C-bus
(see Table 14).
2000 Dec 11
7
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
Audio processor
TREBLE FUNCTION
SELECTOR
Two external capacitors C15 = 3.3 nF and C14 = 150 pF
for each channel in combination with a linear operational
amplifier and internal resistors provide a treble range of
+8 dB for high treble and −1.5 dB for low treble.
The selector enables the selection of either the internal line
output signals LOR and LOL (dematrix output) or the
external line input signals LIR and LIL (see Table 16). The
input signal capability of the line inputs (LIR/LIL) is
2 V (RMS). The output of the selector is DC-coupled to the
automatic volume level control circuit.
MUTE
The mute function can be activated independently with the
last step of volume control at the left or right output. By
setting the general mute bit GMU the audio outputs OUTL
and OUTR are muted.
VOLUME
The volume control range is from +12 dB to −63 dB in
steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume
control of each channel.
BASS FUNCTION
A single external 56 nF capacitor for each channel in
combination with a linear operational amplifier and internal
resistors provides a bass range of +12 dB for high bass
and +5 dB for low bass.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER
VCC
CONDITIONS
MIN. MAX. UNIT
supply voltage
−
9.5
V
VSDA, VSCL
voltage at pins SDA and SCL referenced
to GND
V
CC ≤ 9 V
CC > 9 V
−0.3
−0.3
0
+VCC
+9
V
V
V
Vn
voltage of all other pins to GND
ambient temperature
VCC
+70
V
Tamb
Tstg
Ves
−20
−65
−200
°C
storage temperature
+150 °C
+200
electrostatic handling voltage
note 1
note 2
V
−2000 +2000 V
Notes
1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually
0.75 µH + 10 Ω).
2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
70
K/W
2000 Dec 11
8
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
CHARACTERISTICS
All voltages are measured relative to GND; VCC = 8 V; Rs = 600 Ω; AC-coupled; RL = 10 kΩ; CL = 2.5 nF; fmod = 1 kHz
mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); pilot 50 mV (RMS);
Gv = 0 dB; linear tone control; AVL off; Tamb = 25 °C; see Fig.1; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VCC
ICC
supply voltage
7.8
25
8
9
V
supply current
33
45
mA
V
Vref
internal reference voltage at
pin Vref
0.45VCC 0.5VCC
0.55VCC
Input stage
Vi(max)(rms)
maximum input voltage
(RMS value)
2
−
−
V
Zi
input impedance
20
25
32
kΩ
Stereo decoder
HR
headroom for L + R, L and R
f
mod = 300 Hz; THD < 15%
9
−
−
−
dB
Vpil(rms)
nominal stereo pilot voltage
(RMS value)
−
50
mV
Vth(on)(rms)
Vth(off)(rms)
pilot threshold voltage, stereo
on (RMS value)
−
−
−
35
mV
mV
pilot threshold voltage, stereo
off (RMS value)
15
−
hys
hysteresis
−
−
2.5
−
−
dB
Vo(rms)
output voltage (RMS value)
100% modulation L + R;
fmod = 300 Hz
500
mV
αcs(L,R)
THDL,R
S/N
stereo channel separation
L and R
14% modulation; fL = 300 Hz; 15
fR = 3 kHz
20
−
dB
%
total harmonic distortion
L and R
100% modulation L or R;
fmod = 1 kHz
−
0.2
1
signal-to-noise ratio at line
output and AF output
mono via I2C-bus; referenced
to 500 mV output signal
CCIR 468-2 weighted;
quasi peak
50
−
60
73
−
−
−
−
dB
DIN noise weighting filter
(RMS value)
dBA
dB
αmute
mute attenuation at LOL, LOR, 100% modulation L + R;
63
VAL and VAR
fmod = 300 Hz; mute via bit E6
Stereo decoder, oscillator (VCXO); note 1
fo
nominal VCXO output
frequency (32fH)
with nominal ceramic
resonator
−
503.5
−
−
kHz
kHz
Hz
∆ffr
∆fcr
spread of free-running
frequency
with nominal ceramic
resonator
500
±190
507
−
capture range frequency
nominal pilot
±265
2000 Dec 11
9
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Audio control part; input pins VIL and VIR to pins OUTL and OUTR
VO
DC output voltage
0.45VCC 0.5VCC
0.55VCC
V
Zi
volume input impedance
output impedance
25
−
30
80
−
38
120
−
kΩ
Ω
Zo
RL
output load resistance
output load capacitance
5
kΩ
nF
V
CL
0
−
2.5
−
Vi(max)(rms)
maximum input voltage
(RMS value)
THD < 0.5%
tbf
2
THD
Vno
total harmonic distortion
noise output voltage
1 V (RMS) input voltage
−
0.05
−
%
CCIR 468-2 weighted;
quasi peak
Gv = 10 dB
−
−
−
−
−
−
−
110
33
10
12
63
1
220
50
−
µV
µV
µV
dB
dB
dB
dB
Gv = 0 dB
mute position
Gc
volume control range
step resolution
maximum boost
maximum attenuation
−
−
Gstep
−
step error between adjoining
step
Gv = +12 to −15 dB and
−
0.5
Gv = −16 to −63 dB; note 2
∆Ga
attenuator set error
Gv = +12 to −50 dB
Gv = −51 to −63 dB
Gv = +12 to −50 dB
−
−
2
dB
−
−
3
dB
∆GL
gain tracking error
mute attenuation
−
−
2
dB
αm
80
−
−
−
dB
VDC(OS)
DC step offset between any
adjacent step
Gv = +12 to 0 dB
Gv = 0 to −63 dB
Gv = +12 to 0 dB
Gv = −1 to −63 dB
0.2
−
10
5
mV
mV
mV
mV
−
DC step offset between any
step to mute
−
2
15
10
−
1
Tone control part
Llinear
linear tone control
−
0
−
−
dB
dB
Lbass(max)
tone control with maximum
bass
referenced to linear position;
fmod = 20 Hz
10
12
Lbass(min)
Ltreble(max)
Ltreble(min)
tone control with minimum
bass
referenced to linear position;
fmod = 20 Hz
3.5
6
5
−
−
−
dB
dB
dB
tone control with maximum
treble
referenced to linear position;
fmod = 20 kHz
8
tone control with minimum
treble
referenced to linear position;
fmod = 20 kHz
−
−1.5
2000 Dec 11
10
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
SYMBOL
VCA
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Is
nominal timing current for
nominal release rate of VCA
detector
Is can be measured at pin TW 6.5
via current meter connected to
0.5VCC + 1 V
8
9.5
µA
Relrate
nominal detector release rate nominal timing current and
external capacitor values
−
125
−
dB/s
Automatic volume level control
Gv
voltage gain
maximum boost; note 3
5
6
7
dB
dB
dB
maximum attenuation; note 3
14
−
15
1.5
16
−
Gstep
equivalent step width between
the input stages (soft switching
system)
Vi(rms)
input voltage (RMS value)
maximum boost; note 3
−
0.1
−
V
maximum attenuation; note 3
−
1.125
200
−
V
Vo(AVL)(rms) output voltage in AVL
operation (RMS value)
160
250
mV
Voffset(DC)
DC offset voltage between
different gain steps
voltage at pin CAV
−
−
20
mV
6 to 5.83 V or 5.83 to 5.61 V or
5.61 to 4.83 V or 4.83 to 2.1 V;
note 4
Ratt
discharge resistors for attack
time constant
AT1 = 0; AT2 = 0; note 5
AT1 = 1; AT2 = 0; note 5
AT1 = 0; AT2 = 1; note 5
AT1 = 1; AT2 = 1; note 5
340
590
0.96
1.7
420
730
1.2
2.1
2
520
910
1.5
2.6
2.4
−
Ω
Ω
kΩ
kΩ
µA
µA
Idec
charge current for decay time normal mode; CCD = 0; note 6 1.6
Power-on speed-up; CCD = 1;
note 6
−
30
Selector internal and external
Zi
input impedance
16
70
70
−
20
76
76
2
25
−
kΩ
dB
dB
V
αs
input isolation of one selected Vi = 1 V; fi = 1 kHz
source to the other input
Vi = 1 V; fi = 12.5 kHz
−
Vi(max)(rms)
Gv
maximum input voltage
(RMS value)
THD < 0.5%
−
voltage gain, selector
−
−
0
−
−
dB
Line output; pins LOL and LOR
Vo(rms)
nominal output voltage
(RMS value)
100% modulation
500
mV
HRo
Zo
output headroom
9
−
−
dB
Ω
output impedance
−
80
120
0.55VCC
−
VO
RL
DC output voltage
output load resistance
output load capacitance
0.45VCC 0.5VCC
V
5
−
−
kΩ
nF
CL
−
2.5
2000 Dec 11
11
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Monitor output; pins VAL and VAR
VO
RL
CL
DC output voltage
−
5
−
0.5VCC
−
V
output load resistance
output load capacitance
−
−
−
kΩ
nF
with 100 Ω in series
2.5
Muting at power supply voltage drop for OUTR and OUTL
∆VCC
supply voltage drop for mute
active
−
VCAP − 0.7 −
V
Power-on reset; note 7
VPOR(start) start of reset voltage
increasing supply voltage
decreasing supply voltage
increasing supply voltage
−
−
−
−
2.5
−
V
V
V
tbf
tbf
VPOR(end)
end of reset voltage
−
Digital part (I2C-bus pins); note 8
(9)
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
LOW-level input current
LOW-level output voltage
3
−
−
−
−
−
VCC
V
−0.3
−10
−10
−
+1.5
+10
+10
0.4
V
µA
µA
V
IIL
VOL
IIL = 3 mA
Notes
1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change
of the resonator supplier is possible, but the resonator specification must be close to the specified ones.
2. 1.5 dB step error between −15 and −16 dB.
3. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off.
4. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.
5. Attack time constant = CCAV × Ratt with CCAV = C8 (see Fig.1).
–G1
----------
–G2
----------
C
CAV × 0.76 V 10 20 – 10 20
--------------------------------------------------------------------------------
6. Decay time =
Idec
a) Example: CCAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s.
7. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position.
8. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification.
Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011).
9. Maximum 9 V if VCC > 9 V.
2000 Dec 11
12
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
MHB791
12
gain
(dB)
(1)
8
(2)
(3)
4
0
(4)
−4
10
2
3
4
5
10
10
10
10
f (Hz)
(1) Maximum bass.
(2) Maximum treble.
(3) Minimum bass.
(4) Minimum treble.
Fig.3 Tone control.
2000 Dec 11
13
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
I2C-BUS PROTOCOL
I2C-bus format to read (slave transmits data)
S
SLAVE ADDRESS
R/W
A
DATA
AN
P
Table 1 Explanation of I2C-bus format to read (slave transmits data)
NAME
DESCRIPTION
S
START condition; generated by the master
1011011; pin MAD not connected
Standard SLAVE ADDRESS (MAD)
Pin programmable SLAVE ADDRESS
1011010; pin MAD connected to ground
logic 1 (read); generated by the master
acknowledge; generated by the slave
slave transmits an 8-bit data word
R/W
A
DATA
AN
P
acknowledge not; generated by the master
STOP condition; generated by the master
Table 2 Definition of the transmitted bytes after read condition
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Y
Y
Y
Y
Y
Y
PONR
STP
Table 3 Bit functions of Table 2
BIT
FUNCTION
STP
PONR
Y
stereo pilot identification (stereo received = 1)
Power-on reset; if PONR = 1, then Power-on reset is detected
indefinite
I2C-bus format to write (slave receives data)
SLAVE ADDRESS R/W
S
A
SUBADDRESS
A
DATA
A
P
Table 4 Explanation of I2C-bus format to write (slave receives data)
NAME
DESCRIPTION
S
START condition
Standard SLAVE ADDRESS
101 101 1; pin MAD not connected
101 101 0; pin MAD connected to ground
logic 0 (write)
Pin programmable SLAVE ADDRESS
R/W
A
acknowledge; generated by the slave
see Table 5
SUBADDRESS (SAD)
DATA
P
see Table 6
STOP condition
2000 Dec 11
14
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5 Subaddress definition (second byte after slave address)
MSB
D7
LSB
D0(1)
FUNCTION
D6
D5
D4
D3
D2
D1(1)
Volume right
Volume left
Control 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Control 2
Note
1. Significant subaddress bits.
Table 6 Data definition (third byte after slave address)
MSB
LSB
FUNCTION
D7
0
D6
B6
C6
E6
0
D5
B5
C5
E5
0
D4
B4
C4
E4
F4
D3
B3
C3
E3
F3
D2
B2
C2
E2
F2
D1
B1
C1
E1
F1
D0
B0
C0
E0
F0
Volume right
Volume left
Control 1
0
0
Control 2
0
Table 7 Bit functions of Table 6
BITS SYMBOL
B0 to B6
FUNCTION
VR0 to VR6
VL0 to VL6
STEREO
GMU
volume control right
volume control left
C0 to C6
E0
mode selection for line out
E1
mute control for OUTL and OUTR
AVL on/off
E2
AVLON
CCD
E3
increased AVL decay current on/off
attack time at AVL
E4 and E5
AT1 and AT2
LMU
E6
line out mute on/off
F0 and F1
TONE
selection between four fixed tone controls
selection between intern and extern
forced mono on/off at OUTL and OUTR
linear tone control on/off
F2
F3
F4
MODE
MONO
LITO
2000 Dec 11
15
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
Table 8 Volume setting
DATA
FUNCTION
Gv (dB)
V6
V5
V4
V3
V2
V1
V0
12
11
10
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
8
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
−12
−13
−14
−15
−16
−17
−18
−19
−20
−21
−22
−23
−24
−25
2000 Dec 11
16
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
DATA
FUNCTION
Gv (dB)
V6
V5
V4
V3
V2
V1
V0
−26
−27
−28
−29
−30
−31
−32
−33
−34
−35
−36
−37
−38
−39
−40
−41
−42
−43
−44
−45
−46
−47
−48
−49
−50
−51
−52
−53
−54
−55
−56
−57
−58
−59
−60
−61
−62
−63
Mute
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2000 Dec 11
17
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
Table 9 Mode setting
Table 14 Line out mute setting
FUNCTION MODE
FUNCTION
DATA
E6
READABLE BIT SETTING BIT
D0/STP
E0/STEREO
LOL
Left
LOR
right
MUTE LINE OUTPUT
logic 1 (stereo
received)
1
Line output mute
1
0
Line output active
Mono
Mono
Mono
mono
mono
mono
logic 1 (stereo
received)
0
1
0
Table 15 Tone setting
FUNCTION
logic 0 (no
stereo received)
DATA
TONE
F1
F0
logic 0 (no
stereo received)
Maximum bass and
maximum treble
1
1
Table 10 Mute setting
FUNCTION
Maximum bass and
minimum treble
1
0
0
0
1
0
DATA
E1
Minimum bass and
maximum treble
MUTE CONTROL FOR
OUTR AND OUTL
Minimum bass and
minimum treble
Forced mute at OUTR and OUTL
No forced mute at OUTR and OUTL
1
0
Table 16 Selector setting
Table 11 AVLON bit setting
FUNCTION
DATA
FUNCTION
DATA
MODE INTERNAL/EXTERNAL
External left and right
F2
1
AVL
E2
1
Automatic volume control on
Automatic volume control off
Internal left and right
0
0
Table 17 Mono setting
Table 12 CCD bit setting
FUNCTION
FUNCTION
DATA
DATA
E3
MONO AT OUTL AND OUTR
Forced mono
F3
1
AVL CURRENT
Increased load current
1
0
No forced mono
0
Load current for normal AVL decay time
Table 18 Linear setting
FUNCTION
Table 13 AVL attack time; see Chapter “Characteristics”
DATA
F4
note 5
MODE TONE
FUNCTION
DATA
Linear
Tone
1
0
R
att (Ω)
E5
E4
420
730
0
0
1
1
0
1
0
1
1200
2100
2000 Dec 11
18
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
INTERNAL PIN CONFIGURATIONS
2
+
3
+
8.5
kΩ
12
kΩ
3.5 kΩ
MHB793
MHB792
Fig.4 Pin 2: CP2.
Fig.5 Pin 3: CP1.
4
+
5, 6
+
25 kΩ
25 kΩ
25 kΩ
50 pF
100 pF
10 kΩ
10 kΩ
MHB795
MHB794
Fig.6 Pin 4: COMP.
Fig.7 Pin 5: CMO; pin 6: CSS.
4 V
8, 26
+
1 kΩ
+
20 kΩ
MHB797
7
MHB796
Fig.8 Pin 7: RFR
.
Fig.9 Pin 8: LIL; pin 26: LIR.
2000 Dec 11
19
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
4 V 10, 24
9, 25
4 V
+
+
30 kΩ
4 V
MHB798
MHB799
Fig.10 Pin 9: LOL; pin 25: LOR.
Fig.11 Pin 10: VIL; pin 24: VIR.
11, 23 4 V
+
13, 14
20, 21
4 V
+
+
80 Ω
5.4 kΩ
12 kΩ
MHB801
MHB800
Fig.13 Pin 13: TC1L; pin 14: TC2L; pin 20: TC2R;
pin 21: TC1R.
Fig.12 Pin 11: VAL; pin 23: VAR.
2000 Dec 11
20
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
4 V 15, 19
+
16, 18
+
28.5 kΩ
80 Ω
9.5 kΩ
4 V
MHB803
MHB802
Fig.14 Pin 15: BCL; pin 19: BCR.
Fig.15 Pin 16: OUTL; pin 18: OUTR.
27
+
28
3.4
kΩ
4.7 kΩ
300 Ω
3.4
kΩ
5 kΩ
MHB805
MHB804
Fig.16 Pin 27: Vref.
Fig.17 Pin 28: VCAP.
29
30
+
+
MHB807
MHB806
Fig.18 Pin 29: CAV
.
Fig.19 Pin 30: TW.
2000 Dec 11
21
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
+
35
31
+
+
6 kΩ
16 kΩ
32
MHB808
MHB809
Fig.20 Pin 31: CW.
Fig.21 Pin 32: BPU; pin 35: FDI.
38
33
1.8 kΩ
+
MHB810
MHB811
Fig.22 Pin 33: FDO.
Fig.23 Pin 38: SDA.
40
5 V
39
1.8 kΩ
+
1.8 kΩ
MHB812
MHB813
Fig.24 Pin 39: MAD (I2C-bus address switch).
Fig.25 Pin 40: SCL.
2000 Dec 11
22
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
42
4 V
41
+
+
MHB814
10 kΩ
10 kΩ
MHB815
Fig.26 Pin 41: VCC
.
Fig.27 Pin 42: CPH.
43
+
3 kΩ
MHB816
Fig.28 Pin 43: CER.
2000 Dec 11
23
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SOT205-1
y
X
A
33
23
Z
34
22
E
e
A
H
2
E
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
44
12
detail X
1
11
Z
v
M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.3
0.05 2.1
0.50 0.25 14.1 14.1
0.35 0.14 13.9 13.9
19.2 19.2
18.2 18.2
2.0
1.2
2.4
1.8
2.4
1.8
mm
1
2.60
0.25
2.35
0.3 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-08-01
99-12-27
SOT205-1
133E01
2000 Dec 11
24
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Dec 11
25
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Dec 11
26
Philips Semiconductors
Product specification
I2C-bus controlled economic BTSC stereo
decoder and audio processor
TDA9853H
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Dec 11
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
70
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp28
Date of release: 2000 Dec 11
Document order number: 9397 750 07474
相关型号：
©2020 ICPDF网 联系我们和版权申明