TDA9855/V2,112 [NXP]

TDA9855;
TDA9855/V2,112
型号: TDA9855/V2,112
厂家: NXP    NXP
描述:

TDA9855

光电二极管 商用集成电路
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INTEGRATED CIRCUITS  
DATA SHEET  
TDA9855  
I2C-bus controlled BTSC  
stereo/SAP decoder and audio  
processor  
1997 Nov 04  
Product specification  
Supersedes data of July 1994  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
FEATURES  
Quasi alignment-free BTSC stereo decoder due to  
automatic adjustment of channel separation via I2C-bus  
High integration level with automatically tuned  
integrated filters  
Input level adjustment I2C-bus controlled  
Alignment-free SAP processing  
dbx noise reduction circuit  
GENERAL DESCRIPTION  
The TDA9855 is a bipolar-integrated BTSC stereo/SAP  
decoder with hi-fi audio processor (I2C-bus controlled) for  
application in TV sets.  
I2C-bus transceiver.  
Audio processor  
Selector for internal and external signals (line in)  
Automatic volume level control  
Subwoofer or surround output with separate volume  
control  
Volume control  
Special loudness characteristic automatically controlled  
in combination with volume setting  
Bass and treble control  
Audio signal zero-crossing detection between any  
volume step switching  
Mute control at audio signal zero-crossing.  
ORDERING INFORMATION  
TYPE NUMBER  
PACKAGE  
NAME  
DESCRIPTION  
VERSION  
TDA9855  
SDIP52  
plastic shrink dual in-line package; 52 leads (600 mil)  
SOT247-1  
SOT188-2  
TDA9855WP  
PLCC68 plastic leaded chip carrier; 68 leads  
LICENSE INFORMATION  
A license is required for the use of this product. For further information, please contact  
COMPANY  
THAT Corporation  
BRANCH  
Licensing Operations  
ADDRESS  
734 Forest St.  
Marlborough, MA 01752  
USA  
Tel.: (508) 229-2500  
Fax: (508) 229-2590  
Tokyo Office  
405 Palm House, 1-20-2 Honmachi  
Shibuya-ku, Tokyo 151  
Japan  
Tel.: (03) 3378-0915  
Fax: (03) 3374-5191  
1997 Nov 04  
2
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
QUICK REFERENCE DATA  
SYMBOL  
VCC  
ICC  
PARAMETER  
supply voltage  
supply current  
CONDITIONS  
MIN.  
8.0  
TYP. MAX. UNIT  
8.5  
75  
9.0  
95  
V
50  
mA  
mV  
VCOMP(rms) input signal voltage (RMS value) 100% modulation L + R;  
fi = 300 Hz  
250  
VoR,L(rms)  
output signal voltage (RMS value) 100% modulation L + R;  
fi = 300 Hz  
500  
mV  
GLA  
input level adjustment control  
maximum gain  
maximum attenuation  
fL = 300 Hz; fR = 3 kHz  
fi = 1 kHz  
4
dB  
dB  
dB  
%
3.5  
35  
0.2  
αcs  
stereo channel separation  
total harmonic distortion L + R  
signal handling (RMS value)  
control range  
25  
THDL,R  
VI, O(rms)  
AVL  
THD < 0.5%  
2
V
15  
71  
+6  
+16  
dB  
dB  
dB  
Gc  
volume control range  
maximum loudness boost  
bass control range  
LB  
fi = 40 Hz  
17  
Gbass  
Gtreble  
Gs  
fi = 40 Hz  
12  
12  
14  
+16.5 dB  
treble control range  
fi = 15 kHz  
+12  
+14  
dB  
dB  
subwoofer control range  
signal-to-noise ratio  
fi = 40 Hz  
S/N  
line out (mono); Vo = 0.5 V (RMS)  
CCIR noise weighting filter  
(peak value)  
60  
73  
dB  
DIN noise weighting filter  
(RMS value)  
dBA  
audio section; Vo = 2 V (RMS);  
gain = 0 dB  
CCIR noise weighting filter  
(peak value)  
94  
dB  
DIN noise weighting filter  
(RMS value)  
107  
dBA  
1997 Nov 04  
3
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
BLOCK DIAGRAM  
HM8A37  
1997 Nov 04  
4
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Component list  
Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.  
COMPONENTS  
VALUE  
TYPE  
REMARK  
C1  
C2  
10 µF  
470 nF  
4.7 µF  
220 nF  
10 µF  
2.2 µF  
4.7 µF  
15 nF  
15 nF  
2.2 µF  
8.2 nF  
150 nF  
33 nF  
5.6 nF  
100 µF  
4.7 µF  
4.7 µF  
100 nF  
10 µF  
4.7 µF  
47 nF  
1 µF  
electrolytic  
foil  
63 V  
C3  
electrolytic  
foil  
63 V  
C4  
C5  
electrolytic  
electrolytic  
electrolytic  
foil  
63 V; Ileak < 1.5 µA  
C6  
16 V  
C7  
16 V  
C8  
±5%  
C9  
foil  
±5%  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
C22  
C23  
C24  
C25  
C26  
C27  
C28  
C29  
C30  
C31  
C32  
C33  
C34  
C35  
C36  
C37  
C39  
C40  
electrolytic  
foil or ceramic  
foil  
63 V  
±5% SMD 2220/1206  
±5%  
foil  
±5%  
foil or ceramic  
electrolytic  
electrolytic  
electrolytic  
foil  
±5% SMD 2220/1206  
16 V  
63 V  
63 V  
electrolytic  
electrolytic  
foil  
63 V  
63 V  
±5%  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
foil or ceramic  
foil  
63 V  
1 µF  
63 V  
10 µF  
10 µF  
2.2 µF  
2.2 µF  
4.7 µF  
2.2 µF  
8.2 nF  
150 nF  
33 nF  
5.6 nF  
100 µF  
150 nF  
4.7 µF  
4.7 µF  
4.7 µF  
4.7 µF  
63 V ±10%  
63 V ±10%  
16 V  
63 V  
63 V ±10%  
16 V  
±5% SMD 2220/1206  
±5%  
foil  
±5%  
foil or ceramic  
electrolytic  
foil  
±5% SMD 2220/1206  
16 V  
±5%  
16 V  
16 V  
16 V  
16 V  
electrolytic  
electrolytic  
electrolytic  
electrolytic  
1997 Nov 04  
5
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
COMPONENTS  
VALUE  
TYPE  
REMARK  
C45  
C47  
C49  
D1  
2.2 µF  
220 µF  
100 nF  
electrolytic  
16 V  
electrolytic  
25 V  
foil or ceramic  
SMD 1206  
general purpose diode  
R1  
2.2 kΩ  
20 kΩ  
2.2 kΩ  
20 kΩ  
2.2 kΩ  
8.2 kΩ  
160 Ω  
R2  
R3  
R4  
R5  
±2%  
R6  
R7  
±2%  
Q1  
CSB503F58  
CSB503JF958  
radial leads  
alternative as SMD  
PINNING  
SYMBOL  
PINS  
DESCRIPTION  
PLCC68  
SDIP52  
TL  
1
2
1
treble control capacitor, left channel  
not connected  
n.c.  
B1L  
B2L  
3
2
bass control capacitor, left channel  
bass control capacitor, left channel  
output subwoofer or output surround sound  
programmable address bit (module address)  
output, left channel  
4
3
OUTS  
MAD  
OUTL  
n.c.  
5
4
6
5
7
6
8 to 10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
not connected  
LDL  
VIL  
7
input loudness, left channel  
input volume control, left channel  
output effects, left channel  
8
EOL  
CAV  
Vref  
9
10  
11  
12  
automatic volume control capacitor  
reference voltage 0.5VCC  
LIL  
input line, left channel  
n.c.  
not connected  
AVL  
SOL  
LOL  
CTW  
CTS  
CW  
13  
14  
15  
16  
17  
18  
19  
20  
input automatic volume control, left channel  
output selector, left channel  
output line control, left channel  
capacitor timing wideband for dbx  
capacitor timing spectral for dbx  
capacitor wideband for dbx  
capacitor spectral for dbx  
CS  
VEO  
variable emphasis output for dbx  
1997 Nov 04  
6
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
PINS  
SYMBOL  
DESCRIPTION  
PLCC68  
SDIP52  
n.c.  
26  
27  
not connected  
VEI  
21  
variable emphasis input for dbx  
not connected  
n.c.  
28  
CNR  
CM  
29  
22  
23  
24  
capacitor noise reduction for dbx  
capacitor mute for SAP  
capacitor DC-decoupling for SAP  
not connected  
30  
CDEC  
n.c.  
31  
32  
AGND  
DGND  
GND  
SDA  
SCL  
VCC  
33  
analog ground  
34  
digital ground  
25  
26  
27  
28  
29  
30  
31  
32  
ground  
35  
serial data input/output (I2C-bus)  
serial clock input (I2C-bus)  
supply voltage  
36  
37  
COMP  
VCAP  
CP1  
38  
composite input signal  
39  
capacitor for electronic filtering of supply  
capacitor for pilot detector  
capacitor for pilot detector  
not connected  
40  
CP2  
41  
n.c.  
42  
CPH  
43  
33  
capacitor for phase detector  
not connected  
n.c.  
44, 45  
46  
CADJ  
CER  
CMO  
CSS  
34  
35  
36  
37  
38  
39  
40  
capacitor for filter adjustment  
ceramic resonator  
47  
48  
capacitor DC-decoupling mono  
capacitor DC-decoupling stereo/SAP  
output line control, right channel  
output selector, right channel  
input automatic volume control, right channel  
not connected  
49  
LOR  
SOR  
AVR  
n.c.  
50  
51  
52  
53  
LIR  
54  
41  
42  
43  
44  
45  
46  
input line control, right channel  
capacitor 2 pseudo function  
capacitor 1 pseudo function  
output effects, right channel  
input volume control, right channel  
input loudness, right channel  
not connected  
CPS2  
CPS1  
EOR  
VIR  
55  
56  
57  
58  
LDR  
n.c.  
59  
60 to 62  
63  
OUTR  
n.c.  
47  
48  
49  
output, right channel  
64  
not connected  
SW  
65  
filter capacitor for subwoofer  
1997 Nov 04  
7
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
PINS  
SYMBOL  
DESCRIPTION  
PLCC68  
SDIP52  
B2R  
B1R  
TR  
66  
67  
68  
50  
51  
52  
bass control capacitor, right channel  
bass control capacitor, right channel  
treble control capacitor  
n.c. 10  
60 n.c.  
59 LDR  
58 VIR  
57 EOR  
C
LDL 11  
VIL 12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
EOL  
C
56  
55  
PS1  
PS2  
AV  
V
C
ref  
54 LIR  
53 n.c.  
52 AVR  
51 SOR  
50 LOR  
C
LIL  
n.c.  
AVL  
SOL  
LOL  
TDA9855H  
C
49  
48  
SS  
TW  
C
C
MO  
TS  
47 CER  
C
C
W
C
46  
ADJ  
S
45 n.c.  
44 n.c.  
VEO  
n.c.  
MHA836  
Fig.2 Pin configuration (PLCC version).  
8
1997 Nov 04  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
FUNCTIONAL DESCRIPTION  
Decoder  
INPUT LEVEL ADJUSTMENT  
The composite input signal is fed to the input level  
adjustment stage. In order to compensate tolerances of  
the FM demodulator which supplied the composite input  
signal, the TDA9855 provides an input level adjustment  
stage. The control range is from 3.5 to +4.0 dB in steps of  
0.5 dB. The subaddress control 3 of Tables 5 and 6 and  
the level adjust setting of Table 22 allows an optimum  
signal adjustment during the set alignment in the  
production line. This value has to be stored in a  
non-volatile memory. The maximum input signal voltage is  
2 V (RMS).  
handbook, halfpage  
TL  
B1L  
1
2
52 TR  
51 B1R  
50 B2R  
49 SW  
48 n.c.  
47 OUTR  
46 LDR  
45 VIR  
44 EOR  
B2L  
3
OUTS  
MAD  
OUTL  
LDL  
4
5
6
7
VIL  
8
STEREO DECODER  
EOL  
9
The output signal of the level adjustment stage is coupled  
to a low-pass filter which suppresses the baseband noise  
above 125 kHz. The composite signal is then fed into a  
pilot detector/pilot cancellation circuit and into the MPX  
demodulator. The main L + R signal passes a 75 µs fixed  
de-emphasis filter and is fed into the dematrix circuit.  
The decoded sub-signal L R is sent to the stereo/SAP  
switch. To generate the pilot signal the stereo demodulator  
uses a PLL circuit including a ceramic resonator.  
The stereo channel separation can be adjusted by an  
automatic procedure or manually. For a detailed  
description see Section “Adjustment procedure”.  
The stereo identification can be read by the I2C-bus  
(see Table 2). Two different pilot thresholds can be  
selected via the I2C-bus (see Table 24).  
C
43  
C
10  
11  
PS1  
AV  
V
C
PS2  
42  
ref  
LIL 12  
AVL 13  
SOL 14  
LOL 15  
41 LIR  
40 AVR  
39 SOR  
38 LOR  
TDA9855  
C
C
16  
17  
18  
19  
37  
36  
TW  
SS  
C
C
MO  
TS  
C
35 CER  
W
C
C
34  
ADJ  
s
C
C
C
V
VEO 20  
VEI 21  
33  
32  
31  
30  
PH  
P2  
P1  
SAP DEMODULATOR  
The composite signal is fed from the output of the input  
level adjustment stage to the SAP demodulator circuit  
through a 5fH (fH = horizontal frequency) band-pass filter.  
The demodulator level is automatically controlled.  
The SAP demodulator includes internal noise and field  
strength detectors that mute the SAP output in the event of  
insufficient signal conditions. The SAP identification signal  
can be read by the I2C-bus (see Table 2).  
C
22  
23  
24  
NR  
C
CAP  
M
C
29 COMP  
DEC  
V
GND 25  
SDA 26  
28  
CC  
27 SCL  
MHA835  
SWITCH  
The stereo/SAP switch feeds either the L R signal or the  
SAP demodulator output signal via the internal dbx noise  
reduction circuit to the dematrix/line out select circuit.  
Table 21 shows the different switch modes provided at the  
output pins LOR and LOL.  
Fig.3 Pin configuration (SDIP version).  
1997 Nov 04  
9
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
control of each channel. The volume control blocks  
dbx DECODER  
operate in combination with the loudness control. The filter  
is linear when maximum gain for volume control is  
selected. The filter characteristic changes automatically  
over a range of 28 dB down to a setting of 12 dB.  
At 12 dB volume control the maximum loudness boost is  
obtained. The filter characteristic is determined by external  
components. The proposed application provides a  
maximum boost of 17 dB for bass and 4.5 dB for treble.  
The loudness may be switched on or off via I2C-bus  
control (see Table 14). The left and right volume control  
stages include two independent zero-crossing detectors.  
In the zero-crossing mode a change in volume is  
automatically activated but not executed. The execution is  
enabled at the next zero-crossing of the signal. If a new  
volume step is activated before the previous one has been  
processed, the previous value will be executed first, and  
then the new value will be activated. If no zero-crossing  
occurs the next volume transmission will enforce the last  
activated volume setting.  
The circuit includes all blocks required for the noise  
reduction system in accordance with the BTSC system  
specification. The output signal is fed through a 73 µs fixed  
de-emphasis circuit to the dematrix block.  
INTEGRATED FILTERS  
The filter functions necessary for stereo and SAP  
demodulation and part of the dbx filter circuits are provided  
on-chip using transconductor circuits. The required filter  
accuracy is attained by an automatic filter alignment  
circuit.  
Audio processor  
SELECTOR  
The selector allows selecting either the internal line out  
signals LOR or LOL (dematrix output) or the external line  
in signals LIR and LIL and combines the left and right  
signals in several modes (see Table 12). The input signal  
capability of the line inputs (LIR/LIL) is 2 V (RMS).  
The output of the selector is AC-coupled to the automatic  
volume level control circuit via pins SOR/SOL and  
AVR/AVL to avoid offset voltages.  
The zero-crossing mode is realized between adjoining  
steps and between any steps, but not from any step to  
mute. In this case the GMU bit is required for use. In case  
only one channel has to be muted, two steps are  
necessary. The first step is a transmission of any step to  
71 dB and the second step is the 71 dB step to mute  
mode. The step of 71 dB to mute mode has no  
zero-crossing but this is not relevant. This procedure has  
to be provided by software.  
AUTOMATIC VOLUME LEVEL CONTROL  
The automatic volume level stage controls its output  
voltage to a constant level of typically 200 mV (RMS) from  
an input voltage range of 0.1 to 1.1 V (RMS). The circuit  
adjusts variations in modulation during broadcasting and  
due to changes in the programme material. The function  
can be switched off. To avoid audible ‘plops’ during the  
permanent operation of the AVL circuit a soft blending  
scheme has been applied between the different gain  
stages. A capacitor (4.7 µF) at pin CAV determines the  
attack and decay time constants. In addition the ratio of  
attack and decay time can be changed via the I2C-bus  
(see notes 7 and 8 of Chapter “Characteristics”).  
BASS CONTROL  
A single external 33 nF capacitor for each channel in  
combination with a linear operational amplifier and internal  
resistors provides a bass control range of +16.5 to 12 dB  
in steps of 1.5 dB at low frequencies (40 Hz). Internally the  
basic step width is 3 dB, with intermediate steps obtained  
by a toggle function that provides an additional 1.5 dB  
boost or attenuation (see Table 9). It should be noted that  
both loudness and bass control together result in a  
maximum bass boost of 34.5 dB for low volume steps.  
EFFECTS  
TREBLE CONTROL  
The audio processor section offers the following mode  
selections: linear stereo, pseudo stereo, spatial stereo and  
forced mono.The spatial mode provides an antiphase  
crosstalk of 30% or 52% (switchable via the I2C-bus;  
see Table 18).  
The adjustable range of the treble control stage is from  
12 to +12 dB in steps of 3 dB. The filter characteristic is  
determined by an external 5.6 nF capacitor for each  
channel. The logic circuitry is arranged in a way that the  
same data words (06H to 16H) can be used for both tone  
controls if a bass control range from 12 to +12 dB and a  
treble control range from 12 to +12 dB with 3 dB steps  
are used (see Tables 9 and 10).  
VOLUME/LOUDNESS  
The volume control range is from +16 dB to 71 dB in  
steps of 1 dB and ends with a mute step (see Table 8).  
Balance control is achieved by the independent volume  
1997 Nov 04  
10  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
wideband expander is performed via the stereo channel  
separation adjust.  
SUBWOOFER; SURROUND SOUND CONTROL  
The subwoofer or the surround mode can be activated with  
the control bit SUR (see Table 6). A low bit provides an  
output signal 12(L + R) in subwoofer mode, a high bit  
selects surround mode and provides an output signal  
12(L R). The signal is fed through a volume control stage  
with a range from +14 to 14 dB in 2 dB steps on top of the  
main channel control to the output pin OUTS. The last  
setting is the mute position (see Table 11). The capacitor  
C35 at pin SW provides a 230 Hz low-pass filter in  
subwoofer mode. In surround mode this capacitor should  
be disconnected. If balance is not in mid position the  
selected left and right output levels will be combined.  
AUTOMATIC ADJUSTMENT PROCEDURE  
Capacitors of external inputs EIL and EIR must be  
grounded  
Composite input signal L = 300 Hz, R = 3.1 kHz,  
14% modulation for each channel; volume gain +16 dB  
via the I2C-bus; to avoid annoying sound level set GMU  
bit to logic 1 during adjustment procedure  
Effects, AVL, loudness off  
Selector setting SC0, SC1 and SC2 = 0, 0, 0  
(see Table 12)  
MUTE  
Line out setting bits: STEREO = 1, SAP = 0  
(see Table 21)  
The mute function can be activated independently with the  
last step of volume or subwoofer/surround control at the  
left, right or centre output. By setting the general mute bit  
GMU via the I2C-bus all audio part outputs are muted.  
All channels include an independent zero-crossing  
detector. The zero-crossing mute feature can be selected  
via bit TZCM:  
Start adjustment by transmission ADJ = 1 in register  
ALI3; the decoder will align itself  
After 1 second, stop alignment by transmitting ADJ = 0  
in register ALI3 read the alignment data by an I2C-bus  
read operation from ALR1 and ALR2  
(see Chapter “I2C-bus protocol”) and store it in a  
non-volatile memory; the alignment procedure  
overwrites the previous data stored in ALI1 and ALI2  
TZCM = 0: forced mute with direct execution  
TZCM = 1: execution in time with signal zero-crossing.  
Disconnect the capacitors of external inputs from  
ground.  
In the zero-crossing mode a change of the GMU bit is  
activated but not executed. The execution is enabled at  
the next zero-crossing of the signal. To avoid a large delay  
of mute switching, when very low frequencies are  
processed, or the output signal amplitude is lower than the  
DC offset voltage, the following I2C-bus transmissions are  
needed:  
MANUAL ADJUSTMENT  
Manual adjustment is necessary when no dual tone  
generator is available (e.g. for service).  
Spectral and wideband data have to be set to 10000  
A first transmission for mute execution  
(middle position for adjustment range)  
A second transmission approximately 100 ms later,  
which must switch the zero-crossing mode to forced  
mute (TZCM = 0)  
Composite input L = 300 Hz; 14% modulation  
Adjust channel separation by varying wideband data  
Composite input L = 3 kHz; 14% modulation  
Adjust channel separation by varying spectral data  
A third transmission to reactivate the zero-crossing  
mode (TZCM = 1). This transmission can take place  
immediately, but must follow before the next mute  
execution.  
Iterative spectral/wideband operation for optimum  
adjustment  
Store data in non-volatile memory.  
Adjustment procedure  
After every power-on, the alignment data and the input  
level adjustment data must be loaded from the non-volatile  
memory.  
COMPOSITE INPUT LEVEL ADJUSTMENT  
Apply the composite signal (from the FM demodulator)  
with 100% modulation (25 kHz deviation) L + R;  
fi = 300 Hz. Set input level control via the I2C-bus  
monitoring line output (500 mV ±20 mV). Store the setting  
in a non-volatile memory. Adjustment of the spectral and  
TIMING CURRENT FOR RELEASE RATE  
Due to possible internal and external spreading, the timing  
current can be adjusted via the I2C-bus (see Table 25) as  
recommended by dbx.  
1997 Nov 04  
11  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Requirements for the composite input signal to ensure correct system performance  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
162  
TYP.  
MAX. UNIT  
COMPL+R(rms) composite input level for 100% measured at pin COMP  
250  
363  
mV  
modulation L + R;  
25 kHz deviation;  
fi = 300 Hz; RMS value  
COMP  
composite input level  
spreading under operating  
conditions  
T
amb = 20 to +70 °C; aging;  
0.5  
+0.5  
dB  
power supply influence  
Zo  
output impedance  
note 1  
low-ohmic 5  
kΩ  
Hz  
kHz  
%
flf  
low frequency roll-off  
high frequency roll-off  
25 kHz deviation L + R; 2 dB  
5
fhf  
25 kHz deviation L + R; 2 dB 100  
THDL,R  
total harmonic distortion L + R fi = 1 kHz; 25 kHz deviation  
0.5  
1.5  
fi = 1 kHz; 125 kHz deviation;  
note 2  
%
S/N  
signal-to-noise ratio  
L + R/noise  
CCIR 468-2 weighted quasi  
peak; L + R; 25 kHz deviation;  
fi = 1 kHz; 75 µs de-emphasis  
critical picture modulation  
with sync only  
44  
54  
dB  
dB  
dB  
αSB  
side band suppression mono  
mono signal: 25 kHz deviation, 46  
into unmodulated SAP carrier; fi = 1 kHz; side band: SAP  
SAP carrier/side band  
carrier frequency ±1 kHz  
αSP  
spectral spurious attenuation  
L + R/spurious  
50 Hz to 100 kHz;  
40  
dB  
mainly n × fH; no de-emphasis;  
L + R; 25 kHz deviation,  
f = 1 kHz as reference  
Notes  
1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input  
impedance (see Chapter “Characteristics”, Section INPUT LEVEL ADJUSTMENT CONTROL) must be taken into  
account.  
2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is  
73 kHz).  
1997 Nov 04  
12  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VCC  
PARAMETER  
CONDITIONS  
MIN.  
MAX.  
9.5  
UNIT  
supply voltage  
0
0
V
V
Vn  
voltage of all other pins with respect to pin  
GND  
VCC  
Tamb  
Tstg  
operating ambient temperature  
storage temperature  
20  
+70  
°C  
°C  
V
65  
+150  
+2000  
+300  
Vesd  
electrostatic handling  
note 1  
note 2  
2000  
300  
V
Notes  
1. Human body model: C = 100 pF; R = 1.5 k.  
2. Charge device model: C = 200 pF; R = 0 .  
THERMAL CHARACTERISTICS  
SYMBOL  
Rth(j-a)  
PARAMETER  
thermal resistance from junction to ambient  
SOT247-1  
CONDITIONS  
in free air  
VALUE  
UNIT  
43  
38  
K/W  
K/W  
SOT188-2  
1997 Nov 04  
13  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
CHARACTERISTICS  
All voltages are measured relative to GND; VCC = 8.5 V; source resistance Rs 600 ; output load RL 10 k;  
CL 2.5 nF; AC-coupled; fi = 1 kHz; Tamb = 25 °C; volume gain control Gc = 0 dB; bass linear; treble linear;  
loudness off; AVL off; effects linear; composite input signal in accordance with BTSC standard; see Fig.1;  
unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
General  
VCC  
supply voltage  
8.0  
8.5  
75  
12VCC  
9.0  
V
ICC  
supply current  
50  
95  
mA  
V
VDC  
DC voltage at signal handling  
pins  
Decoder section  
INPUT LEVEL ADJUSTMENT CONTROL  
GLA  
input level adjustment control maximum gain  
2
4.0  
3.5  
0.5  
dB  
dB  
dB  
V
maximum attenuation  
Gstep  
step resolution  
Vi(rms)  
maximum input voltage level  
(RMS value)  
Zi  
input impedance  
29.5  
35  
40.5  
kΩ  
STEREO DECODER  
MPXL+R(rms) input voltage level for 100%  
modulation L + R; 25 kHz  
input level adjusted via I2C-bus  
(L + R; fi = 300 Hz);  
250  
mV  
deviation (RMS value)  
monitoring line out  
MPXLR  
input voltage level for 100%  
modulation L R; 50 kHz  
deviation (peak value)  
9
707  
mV  
dB  
MPX(max)  
maximum headroom for L + R, fmod < 15 kHz; THD < 15% for  
L, R  
75 µs equivalent input  
modulation  
MPXpilot(rms) nominal stereo pilot voltage  
level (RMS value)  
50  
mV  
STon(rms)  
pilot threshold voltage stereo  
on (RMS value)  
data STS = 1  
data STS = 0  
data STS = 1  
data STS = 0  
35  
30  
mV  
mV  
mV  
mV  
dB  
SToff(rms)  
pilot threshold voltage stereo  
off (RMS value)  
15  
10  
hys  
hysteresis  
2.5  
500  
OUTL+R  
output voltage level for 100% input level adjusted via I2C-bus 480  
modulation L + R at LINE OUT (L + R; fi = 300 Hz);  
monitoring LINE OUT  
520  
mV  
1997 Nov 04  
14  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
αcs  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
stereo channel separation L/R aligned with dual tone 14%  
at LINE OUT  
modulation; see Section  
“Adjustment procedure” in  
Chapter “Functional  
description”  
fL = 300 Hz; fR = 3 kHz  
fL = 300 Hz; fR = 8 kHz  
fL = 300 Hz; fR = 10 kHz  
25  
35  
30  
25  
dB  
dB  
dB  
20  
15  
fL, R  
L, R frequency response  
14% modulation;  
fref = 300 Hz L or R  
fi = 50 Hz to 11 kHz  
fi = 12 kHz  
3  
dB  
dB  
%
3  
0.2  
THDL,R  
S/N  
total harmonic distortion L, R  
at LINE OUT  
modulation L or R  
1.0  
1% to 100%; fi = 1 kHz  
signal-to-noise ratio  
mono mode; CCIR 468-2  
weighted; quasi peak;  
500 mV output signal  
50  
60  
dB  
STEREO DECODER, OSCILLATOR (VCXO); note 1  
fo  
nominal VCXO output  
frequency (32fH)  
with nominal ceramic  
resonator  
503.5  
kHz  
kHz  
Hz  
fof  
spread of free-running  
frequency  
with nominal ceramic  
resonator  
500.0  
±190  
507.0  
fH  
capture range frequency  
(nominal pilot)  
±265  
SAP DEMODULATOR; note 2  
SAPi(rms)  
nominal SAP carrier input  
voltage level (RMS value)  
15 kHz frequency deviation of  
intercarrier  
150  
mV  
mV  
mV  
SAPon(rms)  
SAPoff(rms)  
pilot threshold voltage SAP on  
(RMS value)  
85  
pilot threshold voltage SAP off  
35  
(RMS value)  
SAPhys  
SAPLEV  
hysteresis  
2
dB  
SAP output voltage level at  
LINE OUT  
LINE OUT (LOL, LOR) in  
position SAP/SAP;  
fmod = 300 Hz;  
500  
mV  
100% modulation  
fres  
frequency response  
14% modulation;  
50 Hz to 8 kHz; fref = 300 Hz  
3  
dB  
%
THD  
total harmonic distortion  
fi = 1 kHz  
0.5  
2.0  
1997 Nov 04  
15  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
LINE OUT AT PINS LOL AND LOR  
Vo(rms)  
nominal output voltage  
(RMS value)  
100% modulation  
500  
mV  
HEADo  
Zo  
output headroom  
9
dB  
output impedance  
80  
120  
VO  
DC output voltage  
0.45VCC 0.5VCC  
0.55VCC  
V
RL  
output load resistance  
output load capacitance  
idle crosstalk L, R into SAP  
5
kΩ  
nF  
dB  
CL  
2.5  
αct  
100% modulation; fi = 1 kHz;  
L or R; line out switched to  
SAP/SAP  
50  
idle crosstalk SAP into L, R  
100% modulation; fi = 1 kHz;  
SAP; line out switched to  
stereo  
50  
dB  
dB  
VST-SAP  
output voltage difference if  
switched from L, R to SAP  
250 Hz to 6.3 kHz  
3
dbx NOISE REDUCTION CIRCUIT  
tadj  
stereo adjustment time  
see Section “Adjustment  
procedure” in Chapter  
“Functional description”  
1
s
Is  
nominal timing current for  
nominal release rate of  
spectral RMS detector  
Is can be measured at pin 17  
(pin 22) via current meter  
connected to 12VCC + 1 V  
24  
µA  
Is  
spread of timing current  
15  
%
%
Is(range)  
timing current adjustment  
range  
7 steps via I2C-bus  
±30  
It  
timing current for release rate  
of wideband RMS detector  
13Is  
µA  
Relrate  
nominal RMS detector  
release rate  
nominal timing current and  
external capacitor values  
wideband  
spectral  
125  
381  
dB/s  
dB/s  
1997 Nov 04  
16  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
Audio part  
CIRCUIT SECTION FROM PINS LIL AND LIR TO PINS OUTL, OUTR AND OUTS; note 3  
B
roll-off frequencies  
C6, C7, C10, C26, C27 and  
C29 = 2.2 µF; Zi = Zi(min)  
low frequency (3 dB)  
20  
Hz  
kHz  
%
high frequency (0.5 dB)  
20  
THD  
total harmonic distortion  
Vi = 1 V (RMS); Gc = 0 dB;  
0.2  
0.5  
AVL on  
Vi = 2 V (RMS); Gc = 0 dB;  
AVL on  
0.2  
0.5  
%
%
%
Vi = 1 V (RMS); Gc = 0 dB;  
AVL off  
0.05  
0.02  
Vi = 2 V (RMS); Gc = 0 dB;  
AVL off  
PSRR  
power supply ripple rejection  
Vr(rms) < 200 mV; fi = 100 Hz  
notes 4 and 5  
47  
50  
dB  
dB  
αB  
crosstalk between bus inputs  
and signal outputs  
110  
Vno  
noise output voltage  
CCIR 468-2 weighted;  
quasi peak  
40  
80  
µV  
measured in dBA  
8
µV  
dB  
dB  
αcs  
channel separation  
Vi = 1 V; fi = 1 kHz  
Vi = 1 V; fi = 12.5 kHz  
75  
75  
SELECTOR (FROM PINS LOL, LOR, LIL AND LIR TO PINS SOL AND SOR)  
Zi  
input impedance  
16  
86  
80  
2
20  
96  
96  
2.3  
24  
kΩ  
dB  
dB  
V
αs  
input isolation of one selected f = 1 kHz; Vi = 1 V  
source to any other input  
f = 12.5 kHz; Vi = 1 V  
Vi(rms)  
Voffset  
maximum input voltage  
(RMS value)  
THD < 0.5%  
DC offset voltage at selector  
output by selection of any  
inputs  
25  
mV  
Zo  
RL  
CL  
Gc  
output impedance  
5
80  
120  
output load resistance (AC)  
output load capacitance  
voltage gain, selector  
kΩ  
nF  
dB  
2.5  
0
1997 Nov 04  
17  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
AUTOMATIC VOLUME LEVEL CONTROL (AVL)  
Zi  
input impedance  
8.8  
11.0  
13.2  
kΩ  
Vi(rms)  
maximum input voltage  
(RMS value)  
THD < 0.2%  
2
V
Gv  
gain, maximum boost  
maximum attenuation  
5
6
7
dB  
dB  
dB  
14  
15  
1.5  
16  
Gstep  
equivalent step width between  
the input stages  
(soft switching system)  
Vi(rms)  
input level at maximum boost see Fig.4  
(RMS value)  
0.1  
V
input level at maximum  
attenuation (RMS value)  
see Fig.4  
1.125  
200  
V
Vo(rms)  
output level in AVL operation  
(RMS value)  
see Fig.4  
160  
250  
6
mV  
mV  
VDC(OFF)  
DC offset between different  
gain steps  
voltage at pin CAV  
6.50 to 6.33 V or  
6.33 to 6.11 V or  
6.11 to 5.33 V or  
5.33 to 2.60 V; note 6  
Ratt  
discharge resistors for attack  
time constant  
AT1 = 0; AT2 = 0; note 7  
AT1 = 1; AT2 = 0; note 7  
AT1 = 0; AT2 = 1; note 7  
AT1 = 1; AT2 = 1; note 7  
340  
590  
0.96  
1.7  
420  
730  
1.2  
2.1  
2.0  
520  
910  
1.5  
2.6  
2.4  
kΩ  
kΩ  
µA  
Idec  
charge current for decay time normal mode; CCD = 0; note 8 1.6  
EFFECT CONTROLS  
αspat1  
αspat2  
ϕ
anti-phase crosstalk by spatial  
effect  
52  
30  
%
%
phase shift by pseudo-stereo  
see Fig.5  
VOLUME TONE CONTROL PART (INPUT PINS VIL AND VIR TO PINS OUTX AND OUTS)  
Zi  
volume input impedance  
output impedance  
8.0  
10.0  
80  
12.0  
120  
kΩ  
Zo  
RL  
output load resistance (AC)  
output load capacitance  
5
kΩ  
nF  
V
CL  
2.5  
Vi(rms)  
maximum input voltage  
(RMS value)  
THD < 0.5%  
2.0  
2.15  
Vno  
noise output voltage  
CCIR 468-2 weighted;  
quasi peak  
Gc = 16 dB  
Gc = 0 dB  
110  
33  
220  
50  
µV  
µV  
µV  
mute position  
10  
1997 Nov 04  
18  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
Gc  
PARAMETER  
total continuous control range maximum boost  
maximum attenuation  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
16  
71  
1
dB  
dB  
dB  
dB  
Gstep  
step resolution  
step error between any  
adjoining step  
0.5  
Ga  
attenuator set error  
Gc = +16 to 50 dB  
Gc = 51 to 71 dB  
Gc = +16 to 50 dB  
2
dB  
3
dB  
Gt  
gain tracking error  
mute attenuation  
2
dB  
αm  
80  
dB  
VDC(OFF)  
DC step offset between any  
adjacent step  
Gc = +16 to 0 dB  
Gc = 0 to 71 dB  
Gc = +16 to +1 dB  
Gc = 0 to 71 dB  
0.2  
10.0  
5
mV  
mV  
mV  
mV  
DC step offset between any  
step to mute  
2
15  
10  
1
LOUDNESS CONTROL PART  
LB  
maximum loudness boost  
loudness on; referred to  
loudness off; boost is  
determined by external  
components; see Fig.6  
fi = 40 Hz  
17  
dB  
dB  
fi = 10 kHz  
4.5  
BASS CONTROL (see Fig.7)  
Gbass  
bass control maximum boost  
fi = 40 Hz  
fi = 40 Hz  
fi = 40 Hz  
15.5  
11  
16.5  
12  
17.5  
13  
dB  
dB  
dB  
dB  
maximum attenuation  
step resolution  
Gstep  
1.5  
step error between any  
adjoining step  
0.5  
VDC(OFF)  
DC step offset between any  
adjacent step  
15  
mV  
TREBLE CONTROL (see Fig.8)  
Gtreble  
treble control maximum boost fi = 15 kHz  
11  
11  
12  
12  
13  
13  
15  
dB  
dB  
dB  
dB  
dB  
maximum attenuation  
maximum boost  
step resolution  
fi = 15 kHz  
fi > 15 kHz  
fi = 15 kHz  
Gstep  
3
step error between any  
adjoining step  
0.5  
VDC(OFF)  
DC step offset between any  
adjacent step  
10  
mV  
1997 Nov 04  
19  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX. UNIT  
SUBWOOFER OR SURROUND CONTROL  
Gs  
subwoofer control  
maximum boost; fi = 40 Hz  
12  
14  
14  
16  
16  
dB  
dB  
maximum attenuation;  
fi = 40 Hz  
12  
Gstep  
αm  
step resolution  
2
dB  
mute attenuation  
60  
dB  
VDC(OFF)  
DC step offset between any  
adjacent step  
Gs = 0 to +14 dB  
10  
5
mV  
mV  
mV  
Gs = 0 to 14 dB  
DC step offset between any  
step to mute  
Gs = +2 to +14 dB without  
input offset (pin SW connected  
to Vref)  
15  
Gs = +2 to +14 dB inclusive  
offset from OUTR, OUTL  
50  
mV  
Gs = 0 to 14 dB  
10  
6
mV  
RF  
internal resistor for low-pass  
filter with external capacitor at  
pin SW  
4
5
kΩ  
L + RREJ  
common mode rejection in  
surround sound at pin OUTS  
mono signal at VIL/VIR;  
f = 1 kHz; Vi = 1 V;  
balance = 0 dB  
26  
36  
dB  
MUTING AT POWER SUPPLY DROP FOR OUTL, OUTR AND OUTS  
VCC-DROP  
supply drop for mute active  
V
CAP 0.7 −  
V
POWER-ON RESET; note 9  
VRESET(STA) start of reset voltage  
increasing supply voltage  
decreasing supply voltage  
increasing supply voltage  
5
6
2.5  
V
V
V
4.2  
5.2  
5.8  
6.8  
VRESET(END) end of reset voltage  
Digital part (I2C-bus pins); note 10  
VIH  
VIL  
IIH  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level input current  
LOW-level input current  
LOW-level output voltage  
3
VCC  
+1.5  
+10  
+10  
0.4  
V
0.3  
10  
10  
V
µA  
µA  
V
IIL  
VOL  
IIL = 3 mA  
1997 Nov 04  
20  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Notes to the characteristics  
1. The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the  
resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855.  
2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.  
3. Select in to input line control.  
Vbus(p-p)  
4. Crosstalk: 20 log  
--------------------  
Vo(rms)  
5. The transmission contains:  
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics  
b) Clock frequency = 50 kHz  
c) Repetition burst rate = 400 Hz  
d) Maximum bus signal amplitude = 5 V (p-p).  
6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, 6 dB and 15 dB.  
7. Attack time constant = CAV × Ratt.  
Gv1  
Gv2  
------------  
20  
------------  
20  
C
AV × 0.76 V 10  
10  
8. Decay time =  
----------------------------------------------------------------------------------  
Idec  
Example: CAV = 4.7 µF; Idec = 2 µA; Gv1 = 9 dB; Gv2 = +6 dB decay time results in 4.14 s.  
9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver  
is in the reset position.  
10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.  
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it”  
(order number 9398 393 40011).  
1997 Nov 04  
21  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
I2C-BUS PROTOCOL  
I2C-bus format to read (slave transmits data)  
S
SLAVE ADDRESS  
R/W  
A
DATA  
MA  
DATA  
P
Table 1 Explanation of I2C-bus format to read (slave transmits data)  
NAME  
DESCRIPTION  
S
START condition; generated by the master  
101 101 1 pin MAD not connected  
Standard SLAVE ADDRESS  
Pin programmable SLAVE ADDRESS  
101 101 0 pin MAD connected to ground  
logic 1 (read); generated by the master  
acknowledge; generated by the slave  
slave transmits an 8-bit data word  
R/W  
A
DATA  
MA  
P
acknowledge; generated by the master  
STOP condition; generated by the master  
Table 2 Definition of the transmitted bytes after read condition  
MSB  
LSB  
D0  
FUNCTION  
BYTE  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Alignment read 1  
Alignment read 2  
ALR1  
ALR2  
Y
Y
SAPP  
SAPP  
STP  
STP  
A14  
A24  
A13  
A23  
A12  
A22  
A11  
A21  
A10  
A20  
Table 3 Function of the bits in Table 2  
BITS  
FUNCTION  
STP  
stereo pilot identification (stereo received = 1)  
SAP pilot identification (SAP received = 1)  
stereo alignment read data  
for wideband expander  
SAPP  
A1X to A2X  
A1X  
A2X  
for spectral expander  
Y
indefinite  
The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next  
data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word  
ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.  
1997 Nov 04  
22  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
I2C-bus format to write (slave receives data)  
S
SLAVE ADDRESS  
R/W  
A
SUBADDRESS  
A
DATA  
A
P
Table 4 Explanation of I2C-bus format to write (slave receives data)  
NAME  
DESCRIPTION  
S
START condition  
Standard SLAVE ADDRESS  
101 101 1 pin MAD not connected  
101 101 0 pin MAD connected to ground  
logic 0 (write)  
Pin programmable SLAVE ADDRESS  
R/W  
A
acknowledge; generated by the slave  
see Table 5  
SUBADDRESS (SAD)  
DATA  
P
see Table 6  
STOP condition  
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress  
and auto-increment of subaddress in accordance with the order of Table 5 is performed.  
Table 5 Subaddress second byte after slave address  
MSB  
D7  
LSB  
D0  
FUNCTION REGISTER  
HEX  
D6  
D5  
D4  
D3  
D2  
D1  
Volume right  
Volume left  
Bass  
VR  
VL  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
BA  
Treble  
TR  
Subwoofer  
Control 1  
Control 2  
Control 3  
Alignment 1  
Alignment 2  
Alignment 3  
SW  
CON1  
CON2  
CON3  
ALI1  
ALI2  
ALI3  
1997 Nov 04  
23  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 6 Definition of third byte after slave address  
MSB  
LSB  
FUNCTION  
Volume right  
REGISTER  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
VR  
VL  
0
VR6  
VR5  
VL5  
0
VR4  
VL4  
BA4  
TR4  
SW4  
X
VR3  
VL3  
BA3  
TR3  
SW3  
SUR  
LMU  
L3  
VR2  
VL2  
BA2  
TR2  
SW2  
SC2  
EF2  
L2  
VR1  
VL1  
BA1  
TR1  
0
VR0  
VL0  
BA0  
0
Volume left  
Bass  
0
VL6  
BA  
0
0
0
Treble  
TR  
0
0
0
Subwoofer  
Control 1  
Control 2  
Control 3  
Alignment 1  
Alignment 2  
Alignment 3  
SW  
0
SW5  
LOFF  
0
CON1  
CON2  
CON3  
ALI1  
ALI2  
ALI3  
GMU  
AVLON  
SC1  
EF1  
L1  
SC0  
EF0  
L0  
SAP STEREO TZCM VZCM  
0
0
0
0
0
0
0
A14  
A24  
0
A13  
A23  
1
A12  
A22  
TC2  
A11  
A21  
TC1  
A10  
A20  
TC0  
STS  
ADJ  
0
0
AT1  
AT2  
Table 7 Function of the bits in Table 6  
BITS  
FUNCTION  
VR0 to VR6  
VL0 to VL6  
BA0 to BA4  
TR1 to TR3  
SW2 to SW5  
GMU  
volume control right  
volume control left  
bass control  
treble control  
subwoofer, surround control  
mute control for outputs OUTL, OUTR and OUTS (generate mute)  
AVL on/off  
AVLON  
LOFF  
switch loudness on/off  
X
don’t care bit  
SUR  
surround/subwoofer SUR = 1 12(L R); SUR = 0 12(L + R)  
selection between line in and line out  
mode selection for line out  
SC0 to SC2  
STEREO, SAP  
TZCM  
zero-crossing mode in mute operation (treble and subwoofer/surround output stage)  
zero-crossing mode in volume operation  
mute control for dematrix + line out select  
selection between mono, stereo linear, spatial stereo and pseudo mode  
input level adjustment  
VZCM  
LMU  
EF0 to EF2  
L0 to L3  
ADJ  
stereo adjustment on/off  
A1X  
stereo alignment data for wideband expander  
stereo alignment data for spectral expander  
attack time at AVL  
A2X  
AT1 and AT2  
TC0 to TC2  
STS  
timing current alignment data  
stereo level switch  
1997 Nov 04  
24  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 8 Volume setting in registers VR and VL  
DATA  
Gc  
(dB)  
D6  
V6  
D5  
V5  
D4  
V4  
D3  
V3  
D2  
V2  
D1  
V1  
D0  
HEX  
V0  
16  
15  
14  
13  
12  
11  
10  
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
7F  
7E  
7D  
7C  
7B  
7A  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
6F  
6E  
6D  
6C  
6B  
6A  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
5F  
5E  
5D  
5C  
5B  
5A  
8
7
6
5
4
3
2
1
0
1  
2  
3  
4  
5  
6  
7  
8  
9  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
1997 Nov 04  
25  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
DATA  
Gc  
(dB)  
D6  
V6  
D5  
V5  
D4  
V4  
D3  
V3  
D2  
V2  
D1  
V1  
D0  
HEX  
V0  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
4F  
4E  
4D  
4C  
4B  
4A  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
3F  
3E  
3D  
3C  
3B  
3A  
39  
38  
37  
36  
35  
34  
33  
1997 Nov 04  
26  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
DATA  
Gc  
(dB)  
D6  
V6  
D5  
V5  
D4  
V4  
D3  
V3  
D2  
V2  
D1  
V1  
D0  
HEX  
V0  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
Mute  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32  
31  
30  
2F  
2E  
2D  
2C  
2B  
2A  
29  
28  
27  
Table 9 Bass setting in register BA  
DATA  
Gbass  
(dB)  
D4  
BA4  
D3  
BA3  
D2  
BA2  
D1  
BA1  
D0  
BA0  
HEX  
16.5  
15.0  
13.5  
12.0  
10.5  
9.0  
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
19  
18  
17  
16  
15  
14  
13  
12  
11  
7.5  
6.0  
4.5  
3.0  
10  
0F  
0E  
0D  
0C  
0B  
0A  
09  
08  
07  
06  
1.5  
0
1.5  
3.0  
4.5  
6.0  
7.5  
9.0  
10.5  
12.0  
1997 Nov 04  
27  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 10 Treble setting in register TR  
Table 12 Selector setting in register CON1  
DATA  
DATA  
Gtreble  
(dB)  
FUNCTION(1)  
D4  
TR4  
D3  
TR3  
D2  
TR2  
D1  
TR1  
D2  
SC2  
D1  
SC1  
D0  
SC0  
HEX  
12  
9
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16  
14  
12  
10  
0E  
0C  
0A  
08  
06  
Inputs LOR and LOL  
Inputs LOR and LOR  
Inputs LOL and LOL  
Inputs LOL and LOR  
Inputs LIR and LIL  
Inputs LIR and LIR  
Inputs LIL and LIL  
Inputs LIL and LIR  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
3
0
3  
6  
9  
12  
Note  
1. Input connected to outputs SOR and SOL.  
Table 11 Subwoofer/surround setting in register SW  
DATA  
Table 13 SUR bit setting in register CON1  
Gs  
(dB)  
D5  
SW5  
D4  
SW4  
D3  
SW3  
D2  
SW2  
FUNCTION  
Surround sound  
DATA D3  
HEX  
1
0
14  
12  
10  
8
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3C  
38  
34  
30  
2C  
28  
24  
20  
1C  
18  
14  
10  
0C  
08  
04  
00  
Subwoofer  
Table 14 LOFF bit setting in register CON1  
CHARACTERISTIC  
With loudness  
Linear  
DATA D5  
6
0
1
4
2
0
Table 15 AVLON bit setting in register CON1  
2  
4  
6  
8  
10  
12  
14  
Mute  
FUNCTION  
DATA D6  
Automatic volume control off  
Automatic volume control on  
0
1
1997 Nov 04  
28  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 16 Mute setting in register CON1  
DATA D7  
GMU  
FUNCTION  
Forced mute at OUTR, OUTL and OUTS  
Audio processor controlled outputs  
1
0
Table 17 Mute setting in register CON2  
DATA D3  
LMU  
FUNCTION  
Forced mute at LOR and LOL  
1
0
Stereo processor controlled outputs  
Table 18 Effects setting in register CON2  
DATA  
FUNCTION  
D2  
D1  
D0  
EF2  
EF1  
EF0  
Stereo linear on  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
Pseudo on  
Spatial stereo; 30% anti-phase crosstalk  
Spatial stereo; 50% anti-phase crosstalk  
Forced mono  
Table 19 Zero-crossing detection setting in register CON2  
DATA D5  
TZCM  
FUNCTION  
Direct mute control  
0
1
Mute control delayed until the next zero-crossing  
Table 20 Zero-crossing detection setting in register CON2  
DATA D4  
VZCM  
FUNCTION  
Direct volume control  
0
1
Volume control delayed until the next zero-crossing  
1997 Nov 04  
29  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 21 Switch setting at line out  
SETTING BITS IN  
REGISTER CON2  
DATA  
LINE OUT SIGNALS AT  
TRANSMISSION STATUS  
INTERNAL SWITCH, READABLE BITS IN  
REGISTER ALR1, ALR2: D6 (SAPP), D5 (STP)  
D7  
SAP  
D6  
STEREO  
LOL  
SAP  
LOR  
SAP  
SAP received  
1
1
0
0
1
1
0
1
1
1
1
0
0
0
Mute  
Left  
mute  
right  
no SAP received  
STEREO received  
no STEREO received  
SAP received  
Mono  
Mono  
Mono  
Mono  
mono  
SAP  
mute  
mono  
no SAP received  
independent  
Table 22 Input level adjust setting in register CON3  
DATA  
Gl  
(dB)  
D3  
L3  
D2  
L2  
D1  
L1  
D0  
L0  
HEX  
4.0  
3.5  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0F  
0E  
0D  
0C  
0B  
0A  
09  
08  
07  
06  
05  
04  
03  
02  
01  
00  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
1997 Nov 04  
30  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 23 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2  
DATA  
FUNCTION  
D4  
D3  
D2  
D1  
D0  
AX4  
AX3  
AX2  
AX1  
AX0  
Gain increase  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Nominal gain  
Gain decrease  
Table 24 STS bit setting in register ALI2 (pilot threshold stereo on)  
FUNCTION  
STon(rms) 35 mV  
DATA D7  
1
0
STon(rms) 30 mV  
1997 Nov 04  
31  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Table 25 Timing current setting in register ALI3  
Table 27 ADJ bit setting in register ALI3  
DATA  
FUNCTION  
DATA D7  
IS RANGE  
Stereo decoder operation mode  
0
1
D2  
TC2  
D1  
TC1  
D0  
TC0  
Auto adjustment of channel separation  
+30%  
+20%  
+10%  
Nominal  
10%  
20%  
30%  
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
Table 26 AVL attack time setting in register ALI3  
DATA  
Ratt  
()  
D6  
AT1  
D5  
AT2  
420  
730  
0
1
0
1
0
0
1
1
1200  
2100  
MHA312  
300  
7
V
V
CAV  
(V)  
o(rms)  
(mV)  
(1)  
(2)  
6
250  
5
4
3
2
1
200  
160  
(3)  
100  
10  
2  
1  
10  
1
10  
V
(V)  
I(rms)  
(1) VCAV  
AVL measured at pin EOL/EOR.  
Y1 axis output level in AVL operation with typically 200 mV.  
(2) Vo max(rms)  
(3) Vo min(rms)  
Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to 15 dB.  
Fig.4 Automatic volume level control diagram.  
1997 Nov 04  
32  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
MHA311  
0
(1)  
phase  
(degree)  
(2)  
100  
(3)  
200  
300  
400  
2
3
4
5
10  
10  
10  
10  
10  
f (Hz)  
(1) see Table 28.  
(2) see Table 28.  
(3) see Table 28.  
Fig.5 Pseudo (phase in degrees) as a function of frequency (left output).  
Table 28 Explanation of curves in Fig.5  
CAPACITANCE AT PIN CPS1  
CAPACITANCE AT PIN CPS2  
(nF)  
CURVE  
EFFECT  
(nF)  
1
2
3
15  
15  
47  
68  
normal  
intensified  
5.6  
5.6  
more intensified  
1997 Nov 04  
33  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
MHA844  
25  
G
c
(dB)  
15  
16  
14  
9
4
5
5  
1  
6  
11  
16  
21  
26  
31  
36  
15  
25  
35  
2
3
4
10  
20  
10  
10  
10  
f (Hz)  
Fig.6 Volume control with loudness (including low roll-off frequency).  
MHA843  
21  
18  
bass  
G
15  
12  
9
(dB)  
6
3
0
3  
6  
9  
12  
15  
2
3
4
10  
20  
10  
10  
10  
f (Hz)  
Fig.7 Bass control.  
34  
1997 Nov 04  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
MHA845  
15  
12  
treble  
G
(dB)  
9
6
3
0
3  
6  
9  
12  
15  
2
3
4
5
10  
200  
10  
10  
10  
f (Hz)  
Fig.8 Treble control.  
MHA842  
60  
handbook, halfpage  
noise  
(µV)  
40  
20  
0
80  
60  
40  
20  
0
20  
gain (dBA)  
Fig.9 Noise as function of gain in dBA (RMS value).  
35  
1997 Nov 04  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
gain volume = 16 dB (G  
)
v(max)  
LIL  
POWER  
STAGE  
TDA9855  
LIR  
G = 20 dB  
P
= 40 W at 4 Ω  
(max)  
V = 200 mV; AVL off  
or  
V = 100 to 1250 mV; AVL on  
V
= 1.26 V for P  
O
I
(max)  
4 dB margin for power peaks  
MHA841  
I
All values given are in RMS value.  
Fig.10 Level diagram.  
1997 Nov 04  
36  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
APPLICATION HINTS  
Selection of input signals by using the zero-crossing mute mode (see Fig.11)  
A selection between the internal signal path and the external input LIL/LIR produces a modulation click depending on the  
difference of the signal values at the time of switching.  
At t1 the maximum possible difference between signals is 7 V (p-p) and gives a large click. Using the zero-crossing  
detector no modulation click is audible.  
For example: The selection is enabled at t1, the microcontroller sets the zero-crossing bit (TZCM = 1) and then the mute  
bit (GMU = 1) via the I2C-bus. The output signal follows the input A signal, until the next zero-crossing occurs and then  
activates mute.  
After a fixed delay time before t2, the microcontroller has to send the forced mute mode (TZCM = 0) and the return to the  
zero-crossing mode (TZCM = 1) to be sure that mute is enabled.  
The output signal remains muted until the next signal zero-crossing of input B occurs, and then follows that signal.  
The delay time t2 t1 is e.g. 40 ms. The zero-crossing function is working at the lowest frequency of 40 Hz.  
MED436  
V
4
(1)  
3
2
1
0
(2)  
(3)  
t
t
t
2
1
1  
2  
3  
4  
(1) Input A (internal signal).  
(2) Output.  
(3) Input B (external input signal).  
Fig.11 Zero-crossing function; only one channel shown.  
1997 Nov 04  
37  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Loudness filter calculation example  
Figure 12 shows the basic loudness circuit with an  
external low-pass filter application. R1 allows an  
attenuation range of 21 dB while the boost is determined  
by the gain stage V1. Both result in a loudness control  
range of +16 to 12 dB.  
handbook, halfpage  
C
KVL  
VIX  
R1  
33 kΩ  
Defining fref as the frequency where the level does not  
change while switching loudness on/off. The external  
resistor R3 for fref → ∞ can be calculated as:  
V
1
LOX  
C1  
R3  
R2  
Gv  
------  
1020  
R3 = R1  
. With G = 21 dB and R1 = 33 k,  
v
---------------------  
Gv  
------  
MHA838  
1 1020  
R3 = 3.2 kis generated.  
For the low-pass filter characteristic the value of the  
external capacitor C1 can be determined by setting a  
specific boost for a defined frequency and referring the  
gain to Gv at fref as indicated above.  
Fig.12 Basic loudness circuit.  
Gv  
------  
(R1 + R3) × 1020 R3  
1
=
-------------------------------------------------------------  
--------------------  
Gv  
j (ω C1)  
------  
1 1020  
handbook, halfpage  
For example: 3 dB boost at f = 1 kHz  
Gv = Gv(ref) + 3 dB = 18 dB; f = 1 kHz and C1 = 100 nF.  
220 nF  
VIX  
R1  
33 kΩ  
8.2 nF  
20 kΩ  
If a loudness characteristic with additional high frequency  
boost is desired, an additional high-pass section has to be  
included in the external filter circuit as indicated in the  
block diagram. A filter configuration that provides  
AC coupling avoids offset voltage problems.  
V
1
LOX  
150  
nF  
R2  
2.2 kΩ  
Figure 13 shows an example of the loudness circuit with  
bass and treble boost.  
MHA839  
Fig.13 Loudness circuit with bass and treble boost.  
1997 Nov 04  
38  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
V
P
+8.5 V to  
oscilloscope  
470  
µF  
V
4.7  
kΩ  
CC  
8.5 V  
28  
inputs  
12  
41  
6
outputs to  
oscilloscope  
TDA9855  
47  
25  
11  
30  
2 × 4.7 µF  
2 × 5 kΩ  
2 × 220 nF  
2 × 600 Ω  
100  
µF  
100  
µF  
MHA840  
Fig.14 Turn-on/off power supply circuit diagram.  
MED433  
10  
(V)  
8
(1)  
6
4
2
(2)  
0
0
1
2
3
4
5
t (s)  
(1) VCC  
(2) VO.  
.
Fig.15 Turn-on/off behaviour.  
39  
1997 Nov 04  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
INTERNAL PIN CONFIGURATIONS  
The pin numbers refer to the SDIP-version.  
handbook, halfpage  
4.25 V  
2
+
handbook, halfpage  
1
4.25 V  
+
3.64 kΩ  
+
7.79 kΩ  
2.4 kΩ  
4.25 V  
MHA846  
MHA847  
Fig.16 Pin 1: treble control capacitor, left;  
pin 52: treble control capacitor, right.  
Fig.17 Pin 2: bass control capacitor input, left;  
pin 51: bass control capacitor input, right.  
handbook, halfpage  
handbook, halfpage  
3
4.25 V  
4
4.25 V  
+
+
80 Ω  
80 Ω  
MHA849  
MHA848  
Fig.19 Pin 4: output subwoofer;  
pin 6: output, left channel;  
pin 14: output selector, left channel;  
pin 39: output selector, right channel;  
pin 47: output, right channel.  
Fig.18 Pin 3: bass control capacitor output, left;  
pin 50: bass control capacitor output, right.  
1997 Nov 04  
40  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
5
+
1.8 kΩ  
MHA850  
Fig.20 Pin 5: MAD (I2C-bus address switch).  
handbook, halfpage  
7
4.25 V  
+
1.33 kΩ  
MHA851  
Fig.21 Pin 7: input loudness, left; pin 46: input loudness, right.  
handbook, halfpage  
8
4.25 V  
+
10.58 kΩ  
4.8 kΩ  
MHA852  
Fig.22 Pin 8: input volume, left; pin 45: input volume, right.  
1997 Nov 04  
41  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
9
4.25 V  
+
handbook, halfpage  
10  
+
15  
kΩ  
6.8  
kΩ  
MHA854  
MHA853  
Fig.23 Pin 9: output effects, left;  
pin 44: output effects, right.  
Fig.24 Pin 10: automatic volume control capacitor.  
handbook, halfpage  
11  
handbook, halfpage  
12  
4.25 V  
+
+
3.4 kΩ  
3.4 kΩ  
20 kΩ  
20 kΩ  
MHA856  
MHA855  
Fig.26 Pin 12: line input, left;  
pin 41: line input, right.  
Fig.25 Pin 11: reference voltage 0.5VCC  
.
1997 Nov 04  
42  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
13  
4.25 V  
1
2
handbook, halfpage  
15 4.25 V  
+
+
5 kΩ  
3
8
1.75 kΩ  
MHA858  
MHA857  
Fig.27 Pin 13: input automatic volume control, left;  
pin 40: input automatic volume control, right.  
Fig.28 Pin 15: line output, left;  
pin 38: line output, right.  
handbook, halfpage  
18  
4.25 V  
handbook, halfpage  
16  
+
+
6 kΩ  
MHA859  
MHA860  
Fig.29 Pin 16: timing capacitor wideband for dbx;  
pin 17: timing capacitor spectral for dbx.  
Fig.30 Pin 18: capacitor wideband for dbx;  
pin 19: capacitor spectral for dbx.  
1997 Nov 04  
43  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
handbook, halfpage  
20  
21  
+
+
600 Ω  
MHA861  
MHA862  
Fig.31 Pin 20: variable emphasis out for dbx.  
Fig.32 Pin 21: variable emphasis in for dbx.  
handbook, halfpage  
23  
handbook, halfpage  
22 4.25 V  
+
+
10 kΩ  
MHA863  
MHA864  
Fig.33 Pin 22: capacitor noise reduction for dbx.  
Fig.34 Pin 23: capacitor mute for SAP.  
handbook, halfpage  
24  
4.25 V  
handbook, halfpage  
26 5 V  
1.8 kΩ  
+
20 kΩ  
20 kΩ  
MHA866  
MHA865  
Fig.35 Pin 24: capacitor DC decoupling for SAP.  
Fig.36 Pin 26: SDA (I2C-bus data input/output).  
1997 Nov 04  
44  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
apply 8.5 V to this pin  
28  
handbook, halfpage  
5 V  
27  
1.8 kΩ  
MHA867  
MHA868  
Fig.37 Pin 27: SCL (I2C-bus clock).  
Fig.38 Pin 28: supply voltage.  
handbook, halfpage  
29  
4.25 V  
handbook, halfpage  
30  
+
+
4.7  
kΩ  
300 Ω  
5 kΩ  
MHA870  
30 kΩ  
MHA869  
Fig.39 Pin 29: input composite signal.  
Fig.40 Pin 30: smoothing capacitor for supply.  
handbook, halfpage  
32  
4.25 V  
+
handbook, halfpage  
31 4.25 V  
+
3.5  
kΩ  
3.5  
kΩ  
3.5 kΩ  
MHA871  
MHA872  
Fig.41 Pin 31: capacitor for pilot detector.  
Fig.42 Pin 32: capacitor for pilot detector.  
1997 Nov 04  
45  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
handbook, halfpage  
34  
handbook, halfpage  
33 4.25 V  
+
+
10 kΩ  
10 kΩ  
MHA873  
MHA874  
Fig.43 Pin 33: capacitor for phase detector.  
Fig.44 Pin 34: capacitor for filter adjust.  
handbook, halfpage  
35  
+
handbook, halfpage  
36 4.25 V  
+
3 kΩ  
10 kΩ  
10 kΩ  
MHA876  
MHA875  
Fig.46 Pin 36: capacitor DC decoupling mono;  
pin 37: capacitor DC decoupling stereo/SAP.  
Fig.45 Pin 35: ceramic resonator.  
handbook, halfpage  
49  
4.25 V  
handbook, halfpage  
43  
4.25 V  
1
+
+
2
3
8
15 kΩ  
10 kΩ  
10 kΩ  
MHA877  
MHA878  
Fig.47 Pin 43: capacitor 1 pseudo function;  
pin 42: capacitor 2 pseudo function.  
Fig.48 Pin 49: capacitor subwoofer.  
1997 Nov 04  
46  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
PACKAGE OUTLINES  
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)  
SOT247-1  
D
M
E
A
2
A
L
A
1
c
e
(e )  
1
w M  
Z
b
1
M
H
b
52  
27  
pin 1 index  
E
1
26  
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
A
A
2
max.  
(1)  
(1)  
Z
1
w
UNIT  
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.  
max.  
1.3  
0.8  
0.53  
0.40  
0.32  
0.23  
47.9  
47.1  
14.0  
13.7  
3.2  
2.8  
15.80  
15.24  
17.15  
15.90  
mm  
5.08  
0.51  
4.0  
1.778  
15.24  
0.18  
1.73  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
90-01-22  
95-03-11  
SOT247-1  
1997 Nov 04  
47  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
PLCC68: plastic leaded chip carrier; 68 leads  
SOT188-2  
e
e
E
D
y
X
A
60  
44  
Z
E
43  
61  
b
p
b
1
w
M
68  
1
H
E
E
pin 1 index  
A
e
A
1
A
4
(A )  
3
k
L
1
p
9
k
27  
β
detail X  
10  
26  
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm  
scale  
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)  
(1)  
(1)  
A
min.  
A
max.  
k
1
max.  
Z
Z
E
(1)  
(1)  
1
4
D
UNIT  
mm  
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.  
4.57  
4.19  
0.81 24.33 24.33  
0.66 24.13 24.13  
23.62 23.62 25.27 25.27 1.22  
22.61 22.61 25.02 25.02 1.07  
1.44  
1.02  
0.53  
0.33  
0.51  
0.51 0.25 3.30  
0.020 0.01 0.13  
1.27  
0.05  
0.18 0.18 0.10 2.16 2.16  
o
45  
0.180  
0.165  
0.032 0.958 0.958  
0.026 0.950 0.950  
0.930 0.930 0.995 0.995 0.048  
0.890 0.890 0.985 0.985 0.042  
0.057  
0.040  
0.021  
0.013  
inches  
0.020  
0.007 0.007 0.004 0.085 0.085  
Note  
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
92-11-17  
95-03-11  
SOT188-2  
112E10  
MO-047AC  
1997 Nov 04  
48  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
SOLDERING  
Introduction  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
situations reflow soldering is often used.  
Several techniques exist for reflowing; for example,  
thermal conduction by heated belt. Dwell times vary  
between 50 and 300 seconds depending on heating  
method. Typical reflow temperatures range from  
215 to 250 °C.  
Preheating is necessary to dry the paste and evaporate  
the binding agent. Preheating duration: 45 minutes at  
45 °C.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011).  
WAVE SOLDERING  
SDIP  
Wave soldering techniques can be used for all PLCC  
packages if the following conditions are observed:  
SOLDERING BY DIPPING OR BY WAVE  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joint for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
A double-wave (a turbulent wave with high upward  
pressure followed by a smooth laminar wave) soldering  
technique should be used.  
The longitudinal axis of the package footprint must be  
parallel to the solder flow.  
The device may be mounted up to the seating plane, but  
the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg max). If the  
printed-circuit board has been pre-heated, forced cooling  
may be necessary immediately after soldering to keep the  
temperature within the permissible limit.  
The package footprint must incorporate solder thieves at  
the downstream corners.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
REPAIRING SOLDERED JOINTS  
Maximum permissible solder temperature is 260 °C, and  
maximum duration of package immersion in solder is  
10 seconds, if cooled to less than 150 °C within  
Apply a low voltage soldering iron (less than 24 V) to the  
lead(s) of the package, below the seating plane or not  
more than 2 mm above it. If the temperature of the  
soldering iron bit is less than 300 °C it may remain in  
contact for up to 10 seconds. If the bit temperature is  
between 300 and 400 °C, contact may be up to 5 seconds.  
6 seconds. Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
PLCC  
REPAIRING SOLDERED JOINTS  
REFLOW SOLDERING  
Fix the component by first soldering two diagonally-  
opposite end leads. Use only a low voltage soldering iron  
(less than 24 V) applied to the flat part of the lead. Contact  
time must be limited to 10 seconds at up to 300 °C. When  
using a dedicated tool, all other leads can be soldered in  
one operation within 2 to 5 seconds between  
270 and 320 °C.  
Reflow soldering techniques are suitable for all PLCC  
packages.  
The choice of heating method may be influenced by larger  
PLCC packages (44 leads, or more). If infrared or vapour  
phase heating is used and the large packages are not  
absolutely dry (less than 0.1% moisture content by  
weight), vaporization of the small amount of moisture in  
them can cause cracking of the plastic body. For more  
information, refer to the Drypack chapter in our “Quality  
Reference Handbook” (order code 9398 510 63011).  
1997 Nov 04  
49  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
1997 Nov 04  
50  
Philips Semiconductors  
Product specification  
I2C-bus controlled BTSC stereo/SAP  
decoder and audio processor  
TDA9855  
NOTES  
1997 Nov 04  
51  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,  
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,  
Fax. +43 160 101 1210  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Belgium: see The Netherlands  
Brazil: see South America  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 689 211, Fax. +359 2 689 102  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,  
Tel. +65 350 2538, Fax. +65 251 6500  
Colombia: see South America  
Czech Republic: see Austria  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,  
Tel. +45 32 88 2636, Fax. +45 31 57 0044  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,  
Tel. +27 11 470 5911, Fax. +27 11 470 5494  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615800, Fax. +358 9 61580920  
South America: Rua do Rocio 220, 5th floor, Suite 51,  
04552-903 São Paulo, SÃO PAULO - SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 829 1849  
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 3 301 6312, Fax. +34 3 301 4107  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 632 2000, Fax. +46 8 632 2745  
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,  
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2686, Fax. +41 1 481 7730  
Hungary: see Austria  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,  
Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Indonesia: see Singapore  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,  
Tel. +90 212 279 2770, Fax. +90 212 282 6707  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,  
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,  
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +1 800 234 7381  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
Uruguay: see South America  
Vietnam: see Singapore  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. +381 11 625 344, Fax.+381 11 635 777  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381  
Middle East: see Italy  
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,  
Internet: http://www.semiconductors.philips.com  
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
© Philips Electronics N.V. 1997  
SCA55  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
547047/1200/03/pp52  
Date of release: 1997 Nov 04  
Document order number: 9397 750 02446  

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