TDA9952HN [NXP]
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras; 10位， 3.0V， 25 Msps的模拟 - 数字为CCD相机接口
| 型号： | TDA9952HN |
| 厂家： | 
NXP |
| 描述： | 10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras |
| 文件： | 总28页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA9952
10-bit, 3.0 V, 25 Msps
analog-to-digital interface for
CCD cameras
Preliminary specification
2002 Aug 21
Supersedes data of 2001 Jul 04
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
FEATURES
GENERAL DESCRIPTION
• Sample rate = 25 Msps;10-bit resolution
The TDA9952 is a 10-bit analog-to-digital interface for
CCD cameras. The device consists of a Correlated Double
Sampling (CDS) circuit, a digitally Programmable Gain
Amplifier (PGA), a black level clamp and a 10-bit
Analog-to-Digital Converter (ADC).
• Single 3.0 V supply operation (2.2 to 3.6 V operation for
the digital outputs)
• Low power consumption: only 115 mW at 2.7 V
• Power consumption in standby mode: 4.5 mW
(typical value)
An internal CDS input buffer is incorporated in order to
avoid using an external buffer that would consume more
power and therefore optimizing the application for low
noise, low power working.
• Programmable gain amplifier:
gain range = 36 dB in 0.1 dB steps
• Correlated double sampling
The PGA gain, the ADC clamp level and other settings are
controlled via a 3-wire serial digital interface.
• Internal input buffer for the correlated double sampling
• Fully programmable via a 3-wire serial interface
• 8-bit DAC included for external analog settings
• TTL-compatible inputs and CMOS-compatible outputs.
An additional DAC is provided for system controls.
The TDA9952 operates from a single 3 V power supply
(2.7 V minimum) and dissipates 135 mW (typical value).
APPLICATIONS
• Video camcorders
• Digital still cameras
• PC-cameras.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA9952HL
LQFP48
plastic low profile quad flat package; 48 leads;
SOT313-2
body 7 × 7 × 1.4 mm
TDA9952HN
HVQFN48
plastic, heatsink very thin quad flat package; no leads;
SOT619-1
48 terminals; body 7 × 7 × 0.85 mm
2002 Aug 21
2
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
QUICK REFERENCE DATA
SYMBOL
VCCA
PARAMETER
CONDITIONS
MIN.
2.7
TYP. MAX. UNIT
analog supply voltage
digital supply voltage
3.0
3.0
2.5
43
3.6
3.6
3.6
−
V
VCCD
VCCO
ICCA
2.7
2.2
−
V
digital outputs supply voltage
analog supply current
V
all clamps active
mA
mA
mA
ICCD
ICCO
digital supply current
fpix = 25 MHz
−
2.0
0.5
−
digital outputs supply current
fpix = 25 MHz; CL = 10 pF;
−
−
input ramp response time is 800 µs
ADCres
ADC resolution
−
10
−
−
−
−
−
1
2
−
−
bits
Vi(CDS)(p-p)
maximum CDS input voltage
(peak-to-peak value)
VCC = 2.85 V
650
800
25
−
mV
VCC ≥ 3.0 V
−
mV
fpix(max)
fpix(min)
maximum pixel rate
minimum pixel rate
−
MHz
MHz
MHz
dB
OCCD(max) = ±100 mV
OCCD(max) = ±200 mV
−
−
−
DRPGA
Ntot(rms)
PGA dynamic range
−
36
0.4
total noise from CDS input to
ADC output (RMS value)
PGA code = 00; see Fig.8
−
LSB
Ein(rms)
Ptot
equivalent input noise voltage PGA code = 383
(RMS value)
−
145
−
µV
total power consumption
VCCA = VCCD = 3 V; VCCO = 2.5 V
CCA = VCCD = 2.7 V; VCCO = 2.2 V
standby mode
−
−
−
135
115
4.5
−
−
−
mW
mW
mW
V
2002 Aug 21
3
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BLK
CLK
OE
V
V
SHP
SHD
AGND1
2
AGND6 CLPOB CLPDM
CCA1
1
CCA6
41
45
46
40
44
48
43
47
39
22
21
DGND1
V
CCD1
CDS CLOCK GENERATOR
37
38
OGND2
V
CCO2
8
9
CPCDS1
CPCDS2
TDA9952
CLAMP
36
35
34
33
32
31
30
29
28
27
D9
D8
7
3
4
V
input buffer
CCA2
D7
D6
D5
D4
D3
D2
D1
D0
AGND2
PGA
CORRELATED
DOUBLE
SAMPLING
IN
BLACK
LEVEL
SHIFT
DATA
FLIP-
FLOP
OUTPUT
BUFFER
SHIFT
BLANKING
25,
26
10-bit ADC
n.c.
CLAMP
V
14
5
ref
V
CCA3
9-BIT
6-BIT
REGISTER
REGISTER
AGND3
24
23
OFD DAC
OGND1
11
V
CCO1
OFDOUT
SERIAL
INTERFACE
8-BIT
REGISTER
INIT-ON-
POWER
10
REGULATOR
DCLPC
13
16
18
17
20
42
12
6
15
19
FCE629
V
V
SCLK
VSYNC
TEST
SEN
SDATA
STDBY
AGND5
AGND4
CCA4
CCA5
Fig.1 Block diagram.
ahdnbok,uflapegwidt
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
PINNING
SYMBOL
VCCA1
PIN
DESCRIPTION
1
analog supply voltage1
analog ground 1
AGND1
AGND2
IN
2
3
analog ground 2
4
input signal from CCD
analog ground 3
AGND3
AGND4
VCCA2
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
AGND5
VCCA3
VCCA4
VCCA5
SDATA
SCLK
SEN
5
6
analog ground 4
7
analog supply voltage 2
clamp storage capacitor pin 1
clamp storage capacitor pin 2
regulator decoupling pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
analog output of the additional 8-bit control DAC
test mode input pin (should be connected to AGND5)
analog ground 5
analog supply voltage 3
analog supply voltage 4
analog supply voltage 5
serial data input for serial interface control
serial clock input for serial interface
strobe pin for serial interface
vertical sync pulse input
digital supply voltage 1
VSYNC
VCCD1
DGND1
VCCO1
OGND1
n.c.
digital ground 1
digital output supply voltage 1
digital output ground 1
not connected
n.c.
not connected
D0
ADC digital output 0 (LSB)
ADC digital output 1
D1
D2
ADC digital output 2
D3
ADC digital output 3
D4
ADC digital output 4
D5
ADC digital output 5
D6
ADC digital output 6
D7
ADC digital output 7
D8
ADC digital output 8
D9
ADC digital output 9 (MSB)
digital output ground 2
OGND2
VCCO2
OE
digital output supply voltage 2
output enable control input (LOW: outputs active; HIGH: outputs in high-impedance)
analog ground 6
AGND6
2002 Aug 21
5
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SYMBOL
VCCA6
PIN
DESCRIPTION
41
42
43
44
45
46
47
48
analog supply voltage 6
STDBY
BLK
standby mode control input (LOW: TDA9952 active; HIGH: TDA9952 standby)
blanking control input
CLPOB
SHP
clamp pulse input at optical black
preset sample-and-hold pulse input
data sample-and-hold pulse input
data clock input
SHD
CLK
CLPDM
clamp pulse input at dummy pixel
V
1
2
3
4
5
6
7
8
9
36 D9
35 D8
34 D7
33 D6
32 D5
31 D4
30 D3
29 D2
28 D1
27 D0
26 n.c.
25 n.c.
CCA1
AGND1
AGND2
IN
AGND3
AGND4
TDA9952HL
V
CCA2
CPCDS1
CPCDS2
DCLPC 10
OFDOUT 11
TEST 12
FCE483
Note: the HVQFN package pin configuration is identical.
Fig.2 Pin configuration.
6
2002 Aug 21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
note 1
MIN.
−0.3
MAX.
+4.5
UNIT
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
digital outputs supply voltage
supply voltage difference
between VCCA and VCCD
between VCCA and VCCO
between VCCD and VCCO
input voltage
note 1
note 1
−0.3
−0.3
+4.5
+4.5
−0.5
−0.5
−0.5
−0.3
−
+0.5
+1.2
+1.2
+6.5
±10
V
V
V
V
Vi
referenced to AGND
Io
data output current
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
ambient temperature
junction temperature
−55
−20
−
+150
+75
150
Note
1. All supplies are connected together.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to ambient in free air
76
K/W
2002 Aug 21
7
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 25 MHz; Tamb = −20 to +75 °C; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
analog supply voltage
digital supply voltage
2.7
2.7
2.2
3.0
3.0
2.5
3.6
V
V
V
3.6
3.6
digital outputs supply
voltage
ICCA
ICCD
ICCO
analog supply current
digital supply current
all clamps active
−
−
−
43
−
−
−
mA
mA
mA
2.0
0.5
digital outputs supply
current
CL = 10 pF on all data
outputs; input ramp of
800 µs duration
Ptot
total power consumption
VCCA = VCCD = 3 V;
VCCO = 2.5 V
−
−
−
135
115
4.5
−
−
−
mW
mW
mW
VCCA = VCCD = 2.7 V;
VCCO = 2.2 V
standby mode
Digital inputs
PINS SHP, SHD AND CLK (REFERENCED TO DGND)
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
−
0.8
5.5
+3
2
V
2.0
−3
−
V
0 ≤ Vi ≤ 5.5 V
µA
pF
Ci
input capacitance
PINS CLPDM, CLPOB, SEN, SCLK, SDATA STBY, OE, BLK AND VSYNC
VIL
VIH
Ii
LOW-level input voltage
HIGH-level input voltage
input current
0
−
−
−
0.8
5.5
+2
V
2.0
−2
V
0 ≤ Vi ≤ 5.5 V
µA
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width in PGA code = 383 for
15
−
−
−
pixels
mS
number of pixels
maximum 6 LSB error for a
CPCDS capacitance
of 1 µF; clamp code = 32
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
−
15
2002 Aug 21
8
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum CDS input
voltage (peak-to-peak
value)
VCC = 2.85 V
CC ≥ 3.0 V
650
800
−
−
−
mV
V
−
mV
Vreset(max)
maximum CDS input reset
pulse
−
−
1.5
V
Ii(IN)
input current into pin IN
input capacitance
at floating gate level
−
−
2
−
3
−
−
µA
pF
ns
Ci
−
tCDS(min)
CDS control pulses
minimum active time
Vi(CDS)(p-p) = 800 mV;
black-to-white transition in
1 pixel with 98.5% Vi
recovery
11
th(IN;SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
Figs 3 and 4
3
3
−
−
−
−
ns
ns
th(IN;SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
Figs 3 and 4
Programmable Gain Amplifier (PGA)
DRPGA
PGA dynamic range
PGA gain step
−
36
−
dB
dB
∆GPGA
0.08
0.10
0.12
ADC
DNL
differential non linearity
ADC resolution
ramp input
−
−
±0.5
±0.9
LSB
bits
ADCres
10
−
Total chain characteristics (CDS + PGA + ADC)
fpix(max)
fpix(min)
maximum pixel rate
minimum pixel rate
25
−
−
−
−
−
−
MHz
MHz
MHz
mV
OCCD(max) = ±100 mV
OCCD(max) = ±200 mV
1
−
2
OCCD(max)
maximum offset voltage
between CCD floating
level and CCD dark pixel
level
−200
+200
tCLKH
CLK pulse width HIGH
CLK pulse width LOW
15
15
−
−
−
−
−
ns
ns
ns
tCLKL
−
td(SHD;CLK)
time delay between
SHD and CLK
Figs 3 and 4
Figs 3 and 4
10
tsu(BLK;SHD)
Vi(IN)
set-up time of BLK
compared to SHD
5
−
−
ns
video input voltage for
ADC full-scale output
PGA code = 00
PGA code = 383
−
−
800
−
−
mV
mV
12.7
2002 Aug 21
9
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Ntot(rms)
total noise from CDS input Fig.8; note 1
to ADC output
PGA code = 00
−
−
−
−
0.4
0.6
145
170
−
LSB
(RMS value)
PGA code = 96
PGA code = 383
PGA code = 96
−
−
−
LSB
µV
Ein(rms)
equivalent input noise
voltage (RMS value)
µV
Digital-to-Analog Converter (OFD DAC)
VOFDOUT(p-p) output voltage
(peak-to-peak value)
RL = 1 MΩ
Fig.5
−
−
−
−
1.0
−
−
V
VOFDOUT(0)
DC output voltage for
code 0
VAGND
V
VOFDOUT(255) DC output voltage for
code 255
Fig.5
VAGND + 1.0 −
V
TCDAC
DAC output temperature
coefficient
250
−
ppm/K
ZOFDOUT
IOFDOUT
DAC output impedance
DAC output current drive
−
−
2000
−
Ω
static
−
100
µA
Digital outputs fpix = 25 MHz; CL = 10 pF; see Figs 3 and 4
VOH
VOL
IOZ
HIGH-level output voltage IOH = −1 mA
V
CCO − 0.5
−
−
−
VCCO
0.5
V
LOW-level output voltage IOL = 1 mA
0
V
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
+20
µA
th(o)
td(o)
output hold time
output delay time
5
−
−
ns
ns
ns
ns
pF
VCCO = 3.6 V; VCCD = 3.6 V −
10
12
13
−
13
15
16
20
V
V
CCO = 2.5 V; VCCD = 3.0 V −
CCO = 2.2 V; VCCD = 2.7 V −
CL
output load capacitance
−
Serial interface
fSCLK(max)
maximum clock frequency
of serial interface
10
−
−
MHz
Note
1. Noise figure includes the internal input buffer circuit.
2002 Aug 21
10
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IN
N + 1
N + 2
N + 3
N + 4
N + 5
N
t
CDS(min)
2.0 V
SHP
SHD
0.8 V
t
h(IN;SHP)
t
CDS(min)
2.0 V
2.0 V
0.8 V
0.8 V
t
h(IN;SHD)
t
CLKH
2.0 V
2.0 V
0.8 V
CLK
0.8 V
t
d(SHD;CLK)
ADC CLAMP
CODE
50%
N
N − 4
N − 3
N − 2
N − 1
DATA
t
h(o)
t
d(o)
2.0 V
BLK
MGU673
t
su(BLK;SHD)
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at falling edge.
Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP.
ahdnbok,uflapegwidt
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
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IN
N + 1
N + 2
N + 3
N + 4
N + 5
N
2.0 V
SHP
SHD
0.8 V
t
t
CDS(min)
2.0 V
h(IN;SHP)
2.0 V
0.8 V
0.8 V
t
t
CDS(min)
h(IN;SHD)
2.0 V
2.0 V
0.8 V
CLK
DATA
BLK
0.8 V
t
t
CLKL
d(SHD;CLK)
ADC CLAMP
CODE
N − 4
N − 3
N − 2
N − 1
50%
N
t
h(o)
t
d(o)
0.8 V
MGU672
t
su(BLK;SHD)
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at rising edge.
Recommended placement for CLK falling edge is between the rising edge of SHD and the falling edge of SHP.
ahdnbok,uflapegwidt
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
handbook, halfpage
1.0
FCE486
OFDOUT DAC
voltage
output
(V)
0
0
255
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
CLPOB
CLPDM
WINDOW
WINDOW
D[9:0]
(digital outputs)
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
CLPDM
(active HIGH)
BLK
(active HIGH)
BLK window
FCE487
Fig.6 Line frequency timing diagram.
13
2002 Aug 21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
MGU671
42
handbook, halfpage
TOTAL
37.9
gain
36
30
24
18
12
6
(dB)
1.9
0
0
64 128 192 256 320 384 448 511
PGA input code
PGAcode
---------------------------
383
Gain(dB) = 1.9 + 36 ×
[dB]
Full-scale at the ADC input is reached at Vi(CDS)(p-p) = 800 mV; PGA code 0.
Fig.7 Total gain from CDS input to ADC input as a function of PGA control code.
FCE489
14
tot(rms)
handbook, halfpage
N
(LSB)
12
10
8
6
4
2
0
0
64
128
192
256
320
383
PGA code
Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 25 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account because there is no input.
Fig.8 Typical total noise performance as a function of PGA gain.
2002 Aug 21
14
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SERIAL INTERFACE
SDATA
SHIFT REGISTER
SD5 SD6
SD0 SD1 SD2
LSB
SD3
SD4
SD7
A1
A2
A3
SD8 SD9 SD10 SD11 A0
MSB
SCLK
SEN
12
LATCH
SELECTION
8
9
6
10
CONTROL PULSE
POLARITY
PGA GAIN
LATCHES
ADC CLAMP
LATCHES
OFDOUT DAC
LATCHES
LATCHES
CONDITIONING
VSYNC
VSYNC
LOAD
FLIP-FLOP
8-bit DAC
FLIP-FLOP
PGA control
FLIP-FLOP
control pulses
polarity settings
ADC clamp
control
FCE490
First logical layer (DFF) is clocked by first falling SCLK edge after rising SEN edge.
Second logical layer is clocked by LOAD signal; this signal depends on VSYNC signal.
If vertical sync signal is not available, VSYNC should be connected to SEN.
Fig.9 Serial interface block diagram.
2002 Aug 21
15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
t
su2
t
hd4
MSB
LSB
SDATA
SCLK
SEN
A3
A2
A1
A0
SD10
SD11 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
t
t
su1
su3
hd5
t
t
VSYNC
hd6
FCE491
tsu1 = tsu2 = tsu3 = 10 ns (minimum); thd4 = thd5 = thd6 = 10 ns (minimum).
Fig.10 Loading sequence of control input data via the serial interface.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
Table 1 Serial interface programming
ADDRESS BITS
DATA BITS SD11 TO SD0
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
PGA gain control (SD8 to SD0)
DAC OFDOUT output control (SD7 to SD0)
ADC clamp reference control (SD5 to SD0); from code 0 to 63
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings;
SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see
Tables 3 and 4
other addresses
test modes (not to be used in normal applications)
Table 2 Polarity settings
PIN
DATA BIT
ACTIVE EDGE OR LEVEL
SHP and SHD
CLK
SD4
SD5
SD0
SD1
SD3
SD8
1 = HIGH; 0 = LOW
1 = rising; 0 = falling
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
1 = HIGH; 0 = LOW
0 = rising; 1 = falling
CLPDM
CLPOB
BLK
VSYNC
Table 3 Standby control using pin STDBY or serial interface
DATA BIT SD7
PIN STDBY
I
CCA + ICCD (typical)
1
HIGH
LOW
HIGH
LOW
1.5 mA
45 mA
45 mA
1.5 mA
0
Table 4 Output enable selection using output enable pin OE or serial interface)
DATA BIT SD6
PIN OE
ADC DIGITAL OUTPUTS D9 TO D0
1
LOW
HIGH
LOW
HIGH
active binary
high-impedance
high-impedance
active binary
0
When power supplies increase from zero, an init-on-power block initializes the circuit as follows:
• PGA gain code is set to 000
• Clamp code is set to 00
• All polarity settings are set to logic 1
• Input OFD is set to logic 0.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
APPLICATION INFORMATION
V
V
CCD
CCD
V
V
CCO
CCA
100 nF
100 nF
(2) (2)
(1)(2)
CCD
1 µF
48 47 46 45 44 43 42 41 40 39 38 37
V
CCA1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c
n.c
V
CCA
1
2
3
4
5
6
36
35
34
33
32
31
30
29
28
27
26
25
AGND1
AGND2
IN
100 nF
AGND3
AGND4
V
TDA9952
V
CCA2
CCA
7
CPCDS1
100 nF
1 µF
8
CPCDS2
DCPLC
9
1 µF
10
11
12
1 µF OFDOUT
TEST
13 14 15 16 17 18 19 20 21 22 23 24
100 nF
CCA
100 nF
CCO
100 nF
(3)
serial
interface
V
V
V
FCE757
CCD
(1) As an internal input buffer is incorporated, depending on the CCD output impedance, an external input buffer may not be necessary and
consequently power savings can be made.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN; SHP) and th(IN; SHD) (see Chapter “Characteristics”).
(3) Pins SEN and VSYNC should be connected together when the vertical sync signal is not available.
Fig.11 Application diagram.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
(1)
CCD
10-bit
data bus
DIGITAL
SIGNAL
TDA9952
PROCESSOR
MGU674
clamp
signals
clock
signals
PULSE
PATTERN
GENERATOR
HORIZONTAL
AND VERTICAL
DRIVER
(1) The external input buffer can be omitted for CCDs with low output impedance; for CCDs with high output impedance, a small current (around 1 mA)
is needed.
Fig.12 Typical imaging application.
Power and grounding recommendations
In a two-ground system, in order to minimize the noise
through the package and die parasitics, the following
recommendation must be implemented:
Care should be taken to minimize the noise when
designing a printed-circuit board for applications such as
PC cameras, surveillance cameras, camcorders and
digital still cameras.
• The ground pin associated with the digital outputs must
be connected to the digital ground plane and special
care should be taken to avoid feedthrough in the analog
ground plane. The analog and digital ground planes
must be connected together with an inductor as closely
as possible to the IC in order for them to have the same
DC voltage.
For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be taken into account, particularly with respect to
power and ground connections.
• The digital output pins and their associated lines should
be shielded by the digital ground plane which can then
be used as a return path for digital signals.
The connections between the CCD interface and the CDS
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
performance. If it is not possible to do this on the board
then the analog supply pins must be decoupled effectively
from the digital supply pins. The decoupling capacitors
must be placed as close as possible to the IC package.
2002 Aug 21
19
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
PACKAGE OUTLINES
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
2002 Aug 21
20
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
HVQFN48: plastic, heatsink very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1
index area
A
4
A
E
detail X
C
e
1
y
y
1/2 e
e
v M
b
C
C
C
A B
1
w M
13
24
L
25
12
e
e
2
E
h
1/2 e
pin 1 index
1
36
48
37
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
max.
A
4
max.
(1)
(1)
UNIT
mm
b
E
h
e
e
e
y
D
D
E
L
v
w
y
1
1
2
h
0.35 7.05 5.25 7.05 5.25
0.18 6.95 4.95 6.95 4.95
0.50
0.30
0.80
0.05
0.1
1.00
0.5
5.5
5.5
0.2
0.1
Note
1. Plastic or metal protrusions of 0.076 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
01-06-07
01-08-08
SOT619-1
MO-220
2002 Aug 21
21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Aug 21
22
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Aug 21
23
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Aug 21
24
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
NOTES
2002 Aug 21
25
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
NOTES
2002 Aug 21
26
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital
interface for CCD cameras
TDA9952
NOTES
2002 Aug 21
27
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp28
Date of release: 2002 Aug 21
Document order number: 9397 750 09672
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