UAA3535HL [NXP]
Low power GSM/DCS/PCS multi-band transceiver; 低功耗GSM / DCS / PCS的多频段收发器
| 型号： | UAA3535HL |
| 厂家： | 
NXP |
| 描述： | Low power GSM/DCS/PCS multi-band transceiver |
| 文件： | 总24页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UAA3535HL
Low power GSM/DCS/PCS
multi-band transceiver
Objective specification
2000 Feb 17
File under Integrated Circuits, IC17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
FEATURES
The second section is the IF section, which further
amplifies the chosen channel and performs gain control to
adjust the output level to the desired value. The IF gain
can be varied over more than 64 dB gain range.
• Multi-band application for GSM, DCS and PCS cellular
phone systems
• Low noise and wide dynamic range low IF receiver
The transmitter also consists of two sections. The first is a
high precision I/Q modulator which converts the baseband
modulation up to the transmit IF. The second is a
modulation loop architecture which converts the signal
to RF.
• More than 35 dB on-chip image rejection in receive
mode
• More than 64 dB gain control range in receive mode
• Integrated channel filter
• Integrated TX low-pass filter
The Local Oscillator (LO) signals are provided by an
on-chip Voltage Controlled Oscillator (VCO) for operation
of the IF section and are provided externally for operation
of the RF section. The frequencies of the RF and IF VCOs
are set by internal PLL circuits, which are programmable
via a 3-wire serial bus. Comparison frequencies are
200 kHz (100 kHz step programmability) and 13 MHz for
the RF and IF PLL respectively, and are derived from a
13 MHz reference signal which has to be supplied
externally. The quadrature-phase RF LO signals required
for I/Q mixers in reception are generated internally.
The quadrature LO signals required for operation of the
I/Q modulator are generated inside the IF VCO.
• High precision I/Q modulator
• Multi-band TX modulation loop architecture including
offset mixer and phase-frequency detector
• Dual PLL with on-chip fully integrated IF VCO
• Fully differential design minimizing crosstalk and
spurious signals
• Functional down to 2.4 V and up to 3.6 V
• 3-wire serial bus interface
• LQFP48 package.
The circuit can be powered-up into one of three different
modes: RX, TX or SYN mode, depending on the logic
state of pins RXON, TXON and SYNON, respectively. It is
also possible to set the IC in one of these modes by
software, using the 3-wire bus serial programming.
In RX (TX) mode, all sections required for receive
(transmit) are turned on. The SYN mode is used to
power-up the synthesizers prior to the RX or TX mode.
In the SYN mode, some internal LO buffers are also
powered-up in such a way that VCO pulling is minimized
when switching on the receiver or the transmitter.
Additional band selection is done using the 3-wire bus
serial programming, allowing the required enabling of the
Low Noise Amplifiers (LNAs) and charge pumps current
programming.
APPLICATIONS
• GSM 900 MHz, DCS 1800 MHz and PCS 1900 MHz
hand-held transceivers.
GENERAL DESCRIPTION
The UAA3535HL is intended for Global Systems for
Mobile communication (GSM), Digital Cellular
communication Systems (DCS) and Personal
Communication Services (PCS). The circuit integrates the
receiver and most of the transmitter section of hand-held
transceivers for these applications.
The receiver consists of two sections. The first section is
the RF receiver front-end, which amplifies the GSM, DCS
or PCS aerial signal, then converts the chosen channel
down to a low Intermediate Frequency (IF) of 100 kHz,
and also provides more than 35 dB image suppression.
Some selectivity is provided at this stage by an on-chip
low-pass filter and channel selectivity is provided by a high
performance integrated band-pass filter.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UAA3535HL
2000 Feb 17
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
2
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
BLOCK DIAGRAM
38
RFGND1
7
39
IA
GSMIA
GSMIB
40
8
×
IB
36
IFCIA
35
41
RFGND2
IFCIB
34
QUAD
37
IFCQA
V
CC(RF)
33
IFCQB
9
42
QA
10
DCSPCSIA
43
×
DCSPCSIB
29
QB
16
RFLOGND
1 : 1/2
32
DATA
V
3-WIRE BUS
17
CC(RFLO)
CLK
30
31
CONTROL REGISTER
18
E
RFLOIA
RFLOIB
MAIN
DIVIDER
11
RXON
12
POWER
ENABLE
PHASE-FREQUENCY
DETECTOR AND
CHARGE PUMP
TXON
25
24
RFCPO
SYNON
22
REFERENCE
DIVIDER
23
26
44
REFIN
1 : 1/2
RFCPGND
3
5
V
TXIFA
TSTO
CC(RFCP)
RFGND3
PHASE-FREQUENCY
14
V
CC2(IF)
DETECTOR AND
CHARGE PUMP
45
2
15
TXRFI
IFGND2
×
V
20
CC(TXCP)
TXCPO
IFCPO
PHASE-FREQUENCY
DETECTOR AND
CHARGE PUMP
21
1
IFCPGND
19
×
V
1 : 6/7
CC(IFCP)
4
IFGND1
48
46
13
TXCPGND
RFGND4
IFTUNE
1 : 1/2
6
UAA3535HL
V
CC1(IF)
91 MHz GSM/DCS
78 MHz PCS
28
47
SYNGND
EXTRES
×
27
V
CC(SYN)
FCA074
Fig.1 Block diagram.
3
2000 Feb 17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
PINNING
SYMBOL PIN
DESCRIPTION
SYMBOL PIN
DESCRIPTION
VCC(RFCP)
VCC(SYN)
SYNGND
RFLOGND
RFLOIA
RFLOIB
VCC(RFLO)
IFCQB
26 RF charge pump supply voltage
27 synthesizers supply voltage
28 synthesizers ground
29 RF LO ground
TXCPO
1
transmit modulation loop GSM
charge pump output
VCC(TXCP)
2
transmit modulation loop charge
pump supply voltage
30 RF LO input A
TXIFA
IFGND1
TSTO
VCC1(IF)
IA
3
4
5
6
7
8
9
transmit IF test pin
31 RF LO input B
IF ground 1
32 RF LO supply voltage
33 RX IF Q test pin B
34 RX IF Q test pin A
35 RX IF I test pin B
test mode output
IF supply voltage 1
IFCQA
I path A baseband input/output
I path B baseband input/output
Q path A baseband input/output
IFCIB
IB
IFCIA
36 RX IF I test pin A
QA
VCC(RF)
37 RF front-end and transmit
modulation loop supply voltage
QB
10 Q path B baseband input/output
11 RX mode control input
12 TX mode control input
13 transmit IF VCO tune input
14 IF supply voltage 2
RXON
TXON
IFTUNE
VCC2(IF)
IFGND2
DATA
CLK
RFGND1
38 RF front-end and transmit
modulation loop ground 1
GSMIA
GSMIB
RFGND2
39 receiver GSM RF input A
40 receiver GSM RF input B
15 IF ground 2
41 RF front-end and transmit
modulation loop ground 2
16 3-wire bus data input
17 3-wire bus clock input
DCSPCSIA 42 receiver DCS/PCS RF input A
DCSPCSIB 43 receiver DCS/PCS RF input B
E
18 3-wire bus enable control input
(active LOW)
RFGND3
44 RF front-end and transmit
modulation loop ground 3
VCC(IFCP)
19 transmit IF charge pump supply
voltage
TXRFI
45 input from RF transmit VCOs
IFCPO
20 transmit IF charge pump output
21 transmit IF charge pump ground
22 synthesizers reference input
23 RF charge pump ground
24 RF charge pump output
RFGND4
46 RF front-end and transmit
modulation loop ground 4
IFCPGND
REFIN
EXTRES
47 reference resistor for transmit
modulation loop
RFCPGND
RFCPO
SYNON
TXCPGND
48 transmit modulation loop charge
pump ground
25 SYN mode control input
2000 Feb 17
4
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
1
2
36 IFCIA
35
TXCPO
V
IFCIB
34 IFCQA
CC(TXCP)
TXIFA
3
4
33
32
31
IFGND1
TSTO
IFCQB
V
5
CC(RFLO)
V
6
RFLOIB
CC1(IF)
UAA3535HL
30 RFLOIA
IA
IB
7
29 RFLOGND
28 SYNGND
8
QA
9
V
V
QB
27
26
10
11
12
CC(SYN)
RXON
TXON
CC(RFCP)
25 SYNON
FCA068
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
RF receiver
Channel filter and AGC
The front-end IF I and Q outputs are first applied to an
amplifier circuit with provision for three 8 dB gain step
adjustment possibilities and then to an integrated
band-pass channel filter. The filter is a fifth-order
band-pass filter centred around 100 with 220 kHz
bandwidth. After filtering the IF I and Q signals are further
amplified with provision for eleven 4 dB gain steps and
DC offset compensation.
The receiver front-end converts the aerial RF signal from
EGSM (Extended GSM; 925 to 960 MHz), DCS
(1805 to 1880 MHz) or PCS (1930 to 1990 MHz) bands
down to an IF signal of 100 kHz. The first stages are
symmetrical LNAs that are matched to 50 Ω using external
baluns. The LNAs are followed by an I/Q down-mixer.
The I/Q down-mixer consists of two mixers in parallel but
driven by quadrature out of phase LO signals.
The In-phase (I) and Quadrature- phase (Q) IF signals are
then low-pass filtered to provide protection from high
frequency offset interferers. The IF I and Q signals are
then fed into the channel filter.
I/Q modulator
I and Q baseband signals are applied to the I/Q modulator
where the modulation spectrum is shifted up to the
transmit IF frequency. For low harmonic distortion, low
carrier leakage and high image rejection, the phase error
must be kept as small as possible. The IF output of the
modulator is fed to an integrated low-pass filter where
unwanted spurious signals are suppressed, prior to being
fed to the phase detector.
2000 Feb 17
5
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
Transmit modulation loop
The ‘main’ path consists of a programmable divider chain
that divides the RF and IF LO signals down to frequencies
of 200 kHz (100 kHz step programmability) and 13 MHz
respectively. Their phase is then compared in a digital
Phase-Frequency Detector (PFD) with that of a reference
signal derived from an external 13 or 26 MHz clock signal.
The phase error information is fed back to the VCO via the
charge pump circuit that ‘sinks’ into or ‘sources’ current
from the loop filter capacitor, thereby changing the VCO
frequency so that the loop becomes ‘phase locked’.
The analog transmit modulation loop consists of an
on-chip offset mixer, a phase-frequency detector, an
off-chip loop filter and a transmit VCO. The analog PLL
copies the modulation to the off-chip transmit VCO and
acts as a tracking filter. A PLL of at least third-order is
required to meet noise requirements at 20 MHz offset from
the carrier. The PLL bandwidth must be greater than
600 kHz in order to keep a low dynamic phase error and to
minimize the acquisition time.
Operating modes
RF and IF LO sections
BASIC OPERATING MODES
The RF LO input covering the 1788 to 2002 MHz
bandwidth is connected to an external RF VCO module.
The RF LO section includes the LO buffering for the
RF PLL, a divider-by-2 or 1 for GSM and DCS/PCS
respectively which drives a quadrature generation network
for use in the RX I/Q down-mixer or the transmit
modulation loop offset mixer. The IF LO section consists of
a fully integrated IF VCO which internally provides the
I/Q modulator with the necessary quadrature signals.
The circuit can be powered-up into different operating
modes depending on the voltage level applied at pins
RXON, TXON and SYNON (hardware control). This
defines the three main modes; RX, TX and SYN. Table 1
describes the different operating modes as defined by
hardware control.
The operation mode status depends on the control bits
SYNON, RXON and TXON (see Table 1).
Dual PLL
When the receiver is on, it is possible to switch-off the low
noise amplifier to perform DC offset compensation in the
receiver (see Section “LNA power control”).
A high performance dual PLL is included on-chip which
enables the frequencies of the RF VCO to be synthesized
off-chip and that of the IF VCO on-chip. Very low close-in
phase noise is achieved which allows the PLL loop
bandwidth to be widened to achieve a shorter settling time.
The charge pump circuit has very low leakage current, in
the nA range, so that the spurious signals are hardly
detectable.
When in TX mode, it is possible to enable the
IF synthesizer and VCO independently from the rest of the
TX section via bit TXIFON via the control bus.
Table 1 Basic operating mode control
CONTROL PIN LEVEL
MODE
POWER STATUS
SYNON
HIGH
HIGH
HIGH
LOW
RXON
LOW
HIGH
LOW
LOW
TXON
LOW
LOW
HIGH
LOW
SYNTHESIZER
RECEIVER
TRANSMITTER
SYN
RX
on
on
on
off
off
on
off
off
off
off
on
off
TX
Idle
2000 Feb 17
6
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
IF SYNTHESIZER AND VCO CONTROL
SIDEBAND SELECTION CONTROL
The IF synthesizer is only necessary in transmit mode.
The TX IF VCO and synthesizer section can be
powered-up with the control bit TXIFON; see Table 2.
If TXIFON is not used, the IF VCO and synthesizer section
will be enabled with the signal TXON.
The receiver includes an image rejection front-end which
allows the use of a RF LO 100 kHz below the RF input
frequency (infradyne) or 100 kHz above the RF input
frequency (supradyne). Between these two states the
proper image should be selected for rejection.
The selection of these 2 modes is accomplished by the
control bit SBD; see Table 5.
Table 2 IF synthesizer and VCO power control
IF SYNTHESIZER AND
Table 5 Sideband selection control
BIT TXIFON
VCO MODE
BIT SBD
SIDEBAND MODE
0
1
off
on
0
1
supradyne
infradyne
LNA POWER CONTROL
TX CHARGE PUMP CURRENT CONTROL
When the receiver is on, it is possible to switch-off the low
noise amplifier separately. Separate control of the low
noise amplifier is accomplished by the control bit LNA; see
Table 3.
The transmit modulation loop includes a transmit charge
pump where sink and source currents are determined by
an external resistor. When determined, this nominal
current can be divided-by-1 or 2 to cope with different
transmit VCO gains. The selection of these 2 modes is
accomplished by the control bit TXI; see Table 6.
Table 3 LNA power control
BIT LNA
LNA MODE
0
1
off
on
Table 6 TX charge pump current control
BIT TXI
TX CHARGE PUMP CURRENT MODE
0
1
nominal current
BAND SELECTION CONTROL
nominal current divided-by-2
The receiver includes two RF front-end and RF LO
sections; one for GSM where the RF LO is divided-by-2
and fed to the 925 to 960 MHz front-end, and the other
one for DCS and/or PCS where the RF LO is not divided
and fed to the 1805 to 1990 MHz front-end. The selection
of these 2 modes is accomplished by the control bit BND;
see Table 4.
REFERENCE DIVIDER CONTROL
The reference divider can be programmed to divide the
external reference frequency by 65 or 130. The selection
of these 2 modes is accomplished by the control bit
REFDIV; see Table 7.
Table 4 Band selection control
Table 7 Reference divider control
BIT BND
BAND MODE
BIT REFDIV
REFERENCE DIVIDER MODE
divide-by-65
divide-by-130
0
1
GSM
DCS and/or PCS
0
1
2000 Feb 17
7
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
IF DIVIDER CONTROL
Programming
The IF divider can be programmed to divide the integrated
IF VCO frequency by 1 or 2. The selection of these
2 modes is accomplished by the control bit IFDIV;
see Table 8.
SERIAL PROGRAMMING BUS
A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable).
The data sent to the device is loaded in bursts framed
by E. Programming clock edges are ignored until E goes
active LOW. The programmed information is loaded into
the addressed latch when E returns inactive HIGH. This is
allowed when CLK is in either state without causing any
consequences to the register data. Only the last 17 bits
serially clocked into the device are retained within the
programming register. Additional leading bits are ignored,
and no check is made on the number of clock pulses.
The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during power-down of both
synthesizers.
Table 8 IF divider control
BIT IFDIV
IF DIVIDER MODE
IF = fVCO
IF = fVCO divided by 2
0
1
TXIF FILTER CONTROL
The transmit section integrates two switchable low-pass
filters, one for a 45.5 MHz IF and the other one for
91 MHz IF. The selection of these 2 modes is
accomplished by the control bit FILT; see Table 9.
DATA FORMAT
Table 9 TXIF filter control
Data is entered with the most significant bit first.
BIT FILT
TXIF FILTER MODE
IF 45.5 MHz
IF 91 MHz
The leading bits make up the data field, while the trailing
4 bits are an address field. The address bits are decoded
on the rising edge of E. This produces an internal load
pulse to store the data in the addressed latch. To ensure
that data is correctly loaded on first power-up, E should be
held LOW and only taken High after having programmed
an appropriate register. To avoid erroneous divider ratios,
the pulse is inhibited during the period when data is read
by the frequency dividers. This condition is guaranteed by
respecting a minimum E pulse width after data transfer.
0
1
IF SYNTHESIZER DIVIDER CONTROL
The IF synthesizer divider can be programmed to divide
the semi-integrated IF VCO frequency by 6 or 7.
The selection of these 2 modes is accomplished by the
control bit IFO; see Table 10.
The allocation of the register bits is given in Table 11.
Table 10 IF synthesizer divider control
IF SYNTHESIZER
DIVIDER MODE
REGISTER PRESET CONDITIONS
BIT IFO
The UAA3535HL programming registers have a preset
state. The preset values can be found in Table 12.
Conditions for guaranteed preset values at power-on are
as follows:
0
1
divide-by-6
divide-by-7
• DATA, CLOCK, E, SYNON, RXON and TXON must be
at 0 V
• Preset value is guaranteed 2 ms after VCC(SYN) rises
to 90% of 2.6 V
• E should stay at 0 V up to the end of the first
programming word.
2000 Feb 17
8
Table 11 Register bit allocation; notes 1 and 2 and 3
REGISTER ALLOCATION
DATA FIELD
ADDRESS
FIELD
BIT
16
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
LAST 4 BITS
X
X
RF
14
RF
13
RF
12
RF
11
RF
10
RF
9
RF
8
RF
7
RF
6
RF
5
RF
4
RF
3
RF
2
RF
1
RF
0
0
0
1
1
X
X
X
X
X
X
X
0
X
0
0
0
0
0
LNA
G5
1
G4
1
G3
G2
G1
G0
0
0
0
0
1
0
0
1
FILT REF
DIV
IFO
IF
DIV
TXI
SBD BND
TXIF SYN
ON
RX
ON
TX
ON
ON
for test purpose only; bit usage to be defined; this is a forbidden address
0
0
0
0
Notes
1. The 15-bit RF divider is programmable through the 15 bits RF0 to RF14, in steps of 100 kHz.
2. X = don’t care.
3. The 6-bit AGC attenuator is programmable through the 6 bits G0 to G5 in 17 steps of 4 dB (see Table 13).
Table 12 Preset values; note 1
REGISTER ALLOCATION
ADDRESS
FIELD
DATA FIELD
BIT
16
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
LAST 4 BITS
X
X
X
X
X
X
1
X
X
0
X
0
0
X
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
for test purpose only; bit usage to be defined; this is a forbidden address
Note
1. X = don’t care.
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
Table 13 AGC gain look-up table; note 1
G5(2)
G4(2)
G3
G2
G1
G0
ATTENUATION (dB)(3)
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
Notes
1. Codes not included in the table are forbidden.
2. Steps at the input of the band-pass filter.
3. The figure represents the total attenuation in the receive path, with respect to the maximum gain.
2000 Feb 17
10
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
LIMITING VALUES
SYMBOL
VCC
VCC(TXCP)
VCC(RFCP)
Pmax
DESCRIPTION
MIN.
−0.3
MAX.
UNIT
supply voltage
+3.6
V
;
supply voltage for RX and TX charge pumps
−0.3
+4.25
V
maximum power dissipation
ambient temperature
−
1
W
Tamb
−30
−40
+70
+150
°C
°C
Tstg
storage temperature
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
65
UNIT
Rth(j-c)
thermal resistance from junction to case
K/W
DC CHARACTERISTICS
VCC = VCC(TXCP) = VCC(RFCP) = 2.6 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
ICC
PARAMETER
supply current
CONDITIONS
MIN.
TYP.
10
MAX.
50
UNIT
normal mode; total power-down;
note 1
−
−
µA
preset mode; total power-down;
note 2
100
200
µA
RX and SYN mode
TX, TXIF and SYN mode
SYN mode
−
−
−
−
51.5
54
17
29
−
60
66
20
37
3.3
mA
mA
mA
mA
V
TXIF and SYN mode
VCC(RF)
RF front-end and transmit
modulation loop supply
voltage
2.4
ICC(RF)
RF front-end and transmit
modulation loop supply
current
RX mode; one LNA and
quadrature mixer active
−
17
−
mA
RX mode; one LNA active
−
−
6
6
−
−
mA
mA
TX mode; transmit modulation
loop active without charge pump
VCC1(IF)
ICC1(IF)
IF supply voltage 1
IF supply current 1
2.4
−
3.3
V
RX mode; I/Q low IF band-pass
filter active
−
7
−
mA
TX mode; I/Q modulator active
−
9
−
4
9
−
mA
V
VCC2(IF)
ICC2(IF)
IF supply voltage 2
IF supply current 2
2.4
−
3.3
−
RX mode; I/Q AGC active
mA
mA
TXIF mode; TX IF VCO active
−
−
2000 Feb 17
11
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
2.4
TYP.
MAX.
3.3
UNIT
VCC(RFLO)
ICC(RFLO)
RF LO supply voltage
RF LO supply current
−
V
RX and SYN mode; RF LO buffer
and divider section active
−
10
−
mA
TX and SYN mode; RF LO buffer
and divider section active
−
10
−
mA
SYN mode; RF LO buffer active
−
6
−
mA
V
VCC(SYN)
ICC(SYN)
synthesizers supply voltage
synthesizers supply current
2.4
−
−
3.3
−
SYN mode; RF synthesizer
active
9.5
mA
TXIF mode; IF synthesizer active
−
0.5
−
mA
V
VCC(IFCP)
ICC(IFCP)
VCC(TXCP)
ICC(TXCP)
transmit IF charge pump
supply voltage
2.4
−
3.3
transmit IF charge pump
supply current
TXIF mode; IF LO charge pump
active; in lock
−
1.5
−
−
mA
V
transmit modulation loop
charge pump supply voltage
2.4
−
4.25
−
transmit modulation loop
charge pump supply current
TX mode; TX RF charge pump
active; in lock; external
resistance is 1800 Ω
1.0
mA
VCC(RFCP)
ICC(RFCP)
RF charge pump supply
voltage
2.4
−
4.25
V
RF charge pump supply
current
SYN mode; RF LO charge pump
active; in lock
−
4.5
−
mA
Baseband section: pins IA, IB, QA and QB
VI(CM)
common mode input-output
voltage I
1.15
1.15
1.25
1.25
1.35
1.35
V
V
V
IA + VIB
VI =
-----------------------
2
VQ(CM)
common mode input-output
voltage Q
V
QA + VQB
V Q
=
---------------------------
2
Logic input levels: pins DATA, CLK, E, TXON, RXON and SYNON
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
0.9
−
−
−
V
V
−
0.3
Notes
1. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are HIGH impedance; pins DATA, CLK and E are
HIGH impedance.
2. VCC(TXCP) = VCC(RFCP) = 4.2 V; pins TXON, RXON and SYNON are LOW; pins DATA, CLK and E are HIGH.
2000 Feb 17
12
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
AC CHARACTERISTICS
VCC = VCC(CP) = 2.6 V; Tamb = −30 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RF receiver section; measured in a 50 Ω impedance system, including external input baluns and matching
networks to 50 Ω
PINS: GSMIA AND GSMIB
fi(RF)
Ri(dif)
Ci(dif)
F
RF input frequency
925
−
−
960
−
MHz
Ω
differential input resistance
parallel RC input model
75
1.5
3.5
differential input capacitance parallel RC input model
−
−
pF
noise figure
for Ri; maximum AGC;
notes 1 and 2
−
4
dB
αoff
LNA off-state attenuation
bit LNA = 0; note 1
−
45
−
−
−
−
dB
Poff
LNA off-state power handling bit LNA = 0; notes 1 and 3 3
dBm
dBm
DES3i
input referred 3 dB
desensitization
∆f = 3 MHz; Tamb = 25 °C; −25
note 1
−
PINS: DCSPCSIA AND DCSPCSIB
fi(RF)
Ri(dif)
Ci(dif)
F
RF input frequency
1805
−
1990
−
MHz
Ω
differential input resistance
parallel RC input model
−
120
1.0
4
differential input capacitance parallel RC input model
−
−
−
pF
noise figure
for Ri; maximum AGC;
notes 1 and 2
4.5
dB
αoff
LNA off-state attenuation
bit LNA = 0; note 1
−
45
−
−
−
−
dB
Poff
LNA off-state power handling bit LNA = 0; notes 1 and 3 6
dBm
dBm
DES3i
input referred 3 dB
desensitization
∆f = 3 MHz; Tamb = 25 °C; −28
note 1
−
PINS: GSMIA, GSMIB, DCSPCSIA AND DCSPCSIB
s11
input reflection coefficient
note 2
−
−15
−
−10
−57
−47
−45
−
dB
SPURP(RFin) power level of spurious
signals at RF input
900 to 1000 MHz band
1800 to 2000 MHz band
out of preceding bands
−
dBm
dBm
dBm
dBm
−
−
−
−
CP1
IP3i
1 dB input compression point minimum AGC;
−25
−
Tamb = 25 °C; note 1
input referred third-order
intercept
maximum AGC;
Tamb = 25 °C; note 1
−18
−
−
−
−
−
2
dBm
dBm
dBm
dB
IP2i
input referred second-order
intercept
maximum AGC; note 4
−
30
−
DES3i
IR
input referred 3 dB
desensitization
∆f = 3 MHz; Tamb = 25 °C; −23
note 1
image rejection
fIF = 200 kHz;
35
38
−
Tamb = 25 °C; note 1
∆Gv(RF)
gain mismatch GSM and
DCS paths
note 5
−
dB
2000 Feb 17
13
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PINS IA, IB, QA AND QB (RX MODE)
Gv(min) minimum voltage conversion gain set to minimum;
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
19
25
31
97
dB
gain notes 1 and 5
maximum voltage conversion gain set to maximum;
gain notes 1 and 5
Gv(max)
89
93
dB
Gv(step)
∆Gv(I/Q)
∆Φ
voltage conversion gain step note 5
gain mismatch I and Q paths note 5
−
−
−
4
−
−
−
dB
0.5
5
dB
quadrature-phase error
I and Q paths
peak error
deg
LEAGC
gain control linearity
over full gain range; note 2 −2
over any 20 dB gain range −0.5
−
−
−
+2
dB
dB
V
+0.5
Vo(peak)
Io(peak)
maximum output voltage per 3% T.H.D.; RL = 100 kΩ
pin
0.75
−
per pin
maximum output current per
pin
25
50
−
µA
Voffset
output offset voltage
under static conditions
−300
−
+300
8
mV
HP−3dB
−3 dB high-pass corner
4
6
kHz
frequency
BIF(−3dB)
∆td(g)
−3 dB IF filter bandwidth
100 kHz centre frequency 220
−
250
2
kHz
µs
group delay variation
30 kHz < fo < 170 kHz
fo = 100 kHz ± 200 kHz
fo = 100 kHz ± 400 kHz
fo = 100 kHz ± 600 kHz
−
1.5
31
64
82
α5(IF)
IF filter attenuation
(fifth-order)
17
54
73
−
dB
dB
dB
−
−
Transmit IF section (initial conditions: Vmod(peak) = 0.5 V; fmod = 67.7 kHz; unless otherwise specified)
PINS IA, IB, QA AND QB (TX MODE)
fmod
modulation frequency
3 dB low-pass cut-off
frequency
1
−
−
MHz
Vmod(peak)
Ri(D)
modulation level
single-ended; peak value
single-ended
−
−
0.5
25
0.55
V
dynamic input resistance
−
kΩ
IF LO oscillator (measured and guaranteed on demonstration board at Tamb = 25 °C)
fIFLO
range of possible operation
VCO gain
with programming
Vtune from 0.6 V to
78
−
91
MHz
KVCO
−
30
−
MHz/V
VCC − 0.6 V
Vtune
tuning voltage
referenced to VCC(IFCP)
pushing
0.4
−
−
V
CC − 0.4
V
∆fVCC
frequency variation with
−
1
MHz/V
respect to the supply voltage
∆fTRON
frequency variation
pulling
−5
−
+5
kHz
Transmit modulation loop section
OFFSET MIXER; PIN TXRFI
fRF
RF input frequency
880
−
1910
MHz
2000 Feb 17
14
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PARAMETER
input resistance
CONDITIONS
single-ended
single-ended
MIN.
TYP.
50
MAX.
UNIT
Ri
Ci
Pi
−
−
−
Ω
input capacitance
input power
−
−
pF
−23
−
−20
−10
10
−17
−
dBm
dB
s11
F
input reflection coefficient
noise figure
Tamb = 25 °C
−
−
dB
CP1
1 dB input compression point Tamb = 25 °C
−
−20
−50
−
−
dBm
dBm
dBm
SPURP(RFin) power level of spurious
signals at RF input
LO leakage
other
−
−45
−45
−
PHASE DETECTOR; PIN TXCPO
ICP(max)
charge pump maximum sink GSM mode; external
1
2
1
4
2
mA
mA
or source current
resistance of 1800 Ω 1%
for minimum output
current; TXI = 0; note 6
DCS and PCS mode;
external resistance of
1800 Ω 1% for minimum
output current; TXI = 1;
note 6
0.5
KΦ
phase-frequency detector
gain
for ICP = 1 mA
−
−
0.16
−
mA/rad
%
∆KΦ
phase-frequency detector
gain variation
over output voltage range
−
10
Vo
Ro
output voltage
0.4
−
V
CC(CP) − 0.4
V
output resistance
−
10
−
kΩ
VCC(PHD)
Vo
=
----------------------
2
Ro(pd)
output resistance power
down
TX mode disabled
−
1
−
kΩ
LOo
local oscillator feedthrough
third-order products level
note 7
−
−
−40
−55
−32
−50
dBc
dBc
IM3o
offset +3 × 67.7 kHz or
−3 × 67.7 kHz; note 7
IMo
image level
f
IFLO − 67.7 kHz; note 7
−
−
−45
−37
dBc
ΦNOISE
phase noise output power
density
∆f = 400 kHz;
Tamb = 25 °C; note 7
−
−117
dBc/Hz
∆f = 1.8 MHz;
−
−
−117
dBc/Hz
Tamb = 25 °C; note 7
∆f = 20 MHz; Tamb = 25 °C −
−
−
−136
−50
dBc/Hz
dBc
SPURL(4fm)
SPURL(8fm)
level of spurious signals at
4 × fmod
fmod = 67.7 kHz;
notes 7 and 8
−
level of spurious signals at
fmod = 67.7 kHz; note 7
−
−
−55
dBc
8 × fmod
RF LO buffer
RF SOURCE CONNECTED AT PIN RFLOIA AND RFLOIB
fi(RF)
RF input frequency
1788
−
2002
MHz
2000 Feb 17
15
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
Ri(dif)
PARAMETER
CONDITIONS
MIN.
TYP.
50
MAX.
UNIT
differential input resistance
parallel RC input model
−
−
−
−
Ω
Ci(dif)
s11
differential input capacitance parallel RC input model
input reflection coefficient
0.2
−15
−5
−
pF
−10
−2
dB
PLO
power available from the
LO source
−8
dBm
RF and IF synthesizers
REFERENCE INPUT; PIN REFIN
fref
reference frequency
REFDIV = 0
REFDIV = 1
−
−
13
26
−
−
MHz
MHz
mV
−
Vi(rms)
Ri
input voltage level
(RMS value)
60
220
input resistance
fref = 13 MHz
−
10
−
kΩ
RF SYNTHESIZER; PIN RFCPO
fRFLO
synthesizer frequency
1700
−
2100
MHz
kHz
dBc
fcomp(RF)
fcomp(leak)
comparison frequency
−
−
200
−50
−
−
200 kHz comparison
frequency leakage
with recommended loop
filter
fstep(RF)
frequency step
programmability
fcomp(RF) = 200 kHz
−
100
−
kHz
Φnoise
close-in phase noise
∆f = 2 kHz
−
−
−80
−76
−70
dBc/Hz
dBc
SPURP(RF)
power level of spurious
signals
f > 400 kHz
−
ICP(nom)
KΦ
nominal charge pump output sink or source
current
1.7
−
2.0
0.32
−
2.3
−
mA
phase-frequency detector
gain
ICP = 2 mA
mA/rad
%
∆KΦ
phase-frequency detector
gain variation
over VCP range
−
10
+5
IL(CP)
VCP
Ro
charge pump leakage current in off state
−5
−
−
1
nA
V
charge pump output voltage ICP within specified range 0.4
VCC − 0.4
output resistance
SYN mode disabled;
power-down
−
−
kΩ
2000 Feb 17
16
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF SYNTHESIZER; PINS IFTUNE AND IFCPO
fIFLO
synthesizer frequency
comparison frequency
close-in phase noise
70
−
100
MHz
fcomp(IF)
Φnoise
−
−
−
13
−
−
MHz
∆f = 400 kHz
−117
−70
dBc/Hz
dBc
SPURP(IF)
power level of spurious
signals
−
ICP
charge pump output current sink or source
0.85
1.0
1.15
mA
KΦ
phase-frequency detector
gain
for ICP = 1 mA
−
0.16
−
mA/rad
∆KΦ
phase-frequency detector
gain variation
over VCP range
−
−
10
+5
%
IL
charge pump leakage current off state
charge pump output voltage
−5
0.4
−
−
−
1
nA
V
VCP
Ro
VCC − 0.4
output resistance
TXIFON and TXON mode
−
kΩ
disabled; power-down
DIVIDERS RATIOS
D/DRF(main)
RF main divider ratio
ratio between RFLOI
frequency and fcomp(RF)
8940
6
−
−
10010
7
D/DIF(main)
IF main divider ratio
ratio between IF VCO
frequency and fcomp(IF)
D/DRF(REFDIV) RF reference divider ratio
D/DIF(REFDIV) IF reference divider ratio
REFDIV = 0
REFDIV = 1
REFDIV = 0
REFDIV = 1
−
−
−
−
65
130
1
−
−
−
−
2
General
tON
turn-on time
90% of the final current
−
−
200
µs
Notes
1. Measured and guaranteed only on OM 5178 demonstration board.
2. This value includes printed-circuit board and balun losses.
3. The power level of the spurious signals in this measurement is less than specified under SPURP(RFin)
4. IP2i related to an IM2 measurement in low gain mode.
.
5. Voltage gain defined as the differential baseband RMS output voltage (either at pins IA and IB or pins QA and QB
measured in standard load) divided by the RMS input voltage at the RF baluns.
6. This range is obtained through variation of the external reference resistor.
7. Measured at external transmit VCO output.
8. This is based on an adjustment in such a way, that a difference of 36 dBc is obtained in the level of the wanted signal
at the frequency fIF + fmod and the level of the signal at the frequency 3fIF − fmod, measured at the input of the
phase-frequency comparator for IF frequencies of 45.5 and 91 MHz.
2000 Feb 17
17
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SERIAL TIMING CHARACTERISTICS
Initial parameter values: VCC = 2.6 V ±5%; Tamb = −30 to +70 °C; unless otherwise specified; see Fig.3.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock: pin CLK
tr
rise time
−
−
10
20
ns
tf
fall time
10
20
ns
ns
Tcy
clock cycle time
200
−
−
Enable programming: pin E
tsu(E) delay to rising clock edge
th(E) delay from last falling clock edge
tW(E)
tsu(E)
200
100
4000
200
−
−
−
−
−
−
−
−
ns
ns
ns
ns
minimum inactive pulse width
enable set-up time to next clock edge
Register serial input data: pin DATA
tsu(D)
th(D)
input data to clock set-up time
input data to clock hold time
50
50
−
−
−
−
ns
ns
t
t
t t
END SU;E
t
t
f
r
SU;DAT
HD;DAT
T
cy
CLK
DATA
MSB
LSB
ADDRESS
E
t
MGD565
t
START
W(min)
Fig.3 Timing diagram 3-wire serial bus.
2000 Feb 17
18
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38
39
40
RFGND1
BALUN
7
8
IA
IB
DCSRX
PCSRX
GSMRX
×
36
35
34
33
IFCIA
IFCIB
IFCQA
41
37
RFGND2
QUAD
V
CC(RF)
IFCQB
9
42
43
QA
QB
BALUN
10
×
29
RFLOGND
16
17
18
1 : 1/2
DATA
CLK
E
32
30
31
V
CC(RFLO)
3-WIRE BUS
CONTROL REGISTER
MAIN
DIVIDER
BALUN
11
12
25
GSM/DCS/PCS
RXON
TXON
POWER
ENABLE
PHASE-FREQUENCY
DETECTOR AND
CHARGE PUMP
24
SYNON
13 MHz
VTCXO
22
REFIN
REFERENCE
DIVIDER
23
26
44
1 : 1/2
RFCPGND
3
5
V
TXIFA
TSTO
CC(RFCP)
RFGND3
PHASE-FREQUENCY
14
15
V
CC2(IF)
DETECTOR AND
CHARGE PUMP
45
2
IFGND2
×
V
20
21
CC(TXCP)
IFCPO
PHASE-FREQUENCY
DETECTOR AND
CHARGE PUMP
1
IFCPGND
GSMTX
DCSTX
PCSTX
19
4
×
V
1 : 6/7
CC(IFCP)
IFGND1
IFTUNE
48
46
13
TXCPGND
1 : 1/2
6
28
27
UAA3535HL
RFGND4
EXTRES
V
CC1(IF)
91 MHz GSM/DCS
78 MHz PCS
47
SYNGND
×
V
CC(SYN)
FCA075
Fig.4 Application diagram.
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
2000 Feb 17
20
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
SOLDERING
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
2000 Feb 17
21
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 17
22
Philips Semiconductors
Objective specification
Low power GSM/DCS/PCS multi-band transceiver
UAA3535HL
NOTES
2000 Feb 17
23
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp24
Date of release: 2000 Feb 17
Document order number: 9397 750 06172
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