MSM63184B-XXXGS-K [OKI]
Microcontroller, 4-Bit, MROM, 2MHz, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, PLASTIC, QFP-128;
| 型号： | MSM63184B-XXXGS-K |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Microcontroller, 4-Bit, MROM, 2MHz, CMOS, PQFP128, 14 X 20 MM, 0.50 MM PITCH, PLASTIC, QFP-128 驱动器 微控制器 CD |
| 文件： | 总30页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2E0059-19-81
This version: Aug. 1999
¡ Semiconductor
MSM63184A
4-Bit Microcontroller with Built-in 640-Dot Matrix LCD Drivers, Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63184A is an enhanced version of the MSM63184B in which supply currents have been
improved.
The MSM63184A is a CMOS 4-bit microcontroller with built-in 640-dot matrix LCD drivers and
operates at 0.9 V (min.). The MSM63184A is suitable for applications such as games, toys,
watches, etc. which are provided with an LCD display.
The MSM63184A is an M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki's original CPU core nX-4/250.
The MSM63P180 is the one-time-programmable ROM version of MSM63188A, having one-time
PROM (OTP) as internal program memory.
The MSM63P180 is used to evaluate the software development.
FEATURES
• Rich instruction set
439 instructions
Transfer,rotate,increment/decrement,arithmeticoperations,comparison,logicoperations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
8K words
Basic instruction length is 16 bits/1 word
• Data memory space
640 nibbles
• External data memory space
Expandable beyond 64 Kbytes by using I/O port.
1/29
¡ Semiconductor
MSM63184A
• Stack level
Call stack level
Register stack level
: 8 levels
: 16 levels
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Canbeinterfacedwithexternalperipheralsthatuseadifferentpowersupplythanthisdevice
uses.
Number of ports:
Input port
Output port
Input-output port
: 2 ports ¥ 4 bits
: 4 ports ¥ 4 bits
: 5 ports ¥ 4 bits
• Buzzer function
Buzzer output
: 0.946 to 5.461 kHz (adjustable in 15 steps)
: Intermittent sound 1, 2; simple sound; continu-
ous sound
Buzzer output modes
• LCD driver
Number of segments
1/1 to 1/16 duty
: 640 Max. (40 SEG ¥ 16 COM)
1/4 or 1/5 bias (regulator built-in)
Selectable as all-on mode/all-off mode/power down mode/normal display mode
Adjustable contrast
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/29
¡ Semiconductor
MSM63184A
• Timers and counter
Watchdog timer ¥ 1
Overflows in 2 sec.
100 Hz timer ¥ 1
Measurable in steps of 1/100 sec.
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Shift register
Shift clock
: 1x or 1/2x system clock; external clock
Data length
: 8 bits
• Interrupt sources
External interrupt
Internal interrupt
: 3
: 7 (watchdog timer interrupt is a nonmask-
able interrupt)
• Operating voltage
When backup used
: 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
When backup not used
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name: MSM63184A-xxxGS-K)
Chip
: (Product name: MSM63184A-xxx)
xxx indicates a code number.
Differences Between the MSM63184B and the MSM63184A
The MSM63184A has the following improved characteristics.
• Supply currents (I
, I
, I
) in DC characteristics
DD1 DD2 DD3
• The V
voltage during a halt of high-speed clock oscillation
DDL
3/29
¡ Semiconductor
MSM63184A
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
to the circuits corresponding to the signal names inside
interface).
indicates that the power is supplied
from V
(power supply for
DDI
nX-4/250
H
X
L
CBR
EBR
RA
PC
TIMING
CON-
ROM
8KW
TROL
Y
A
G
C
Z
SP
BUS
CON-
TROL
D0-7*
ALU
EXTMEM
RSP
MIE
A0-15*
RD*
WR*
INSTRUCTION
DECODER
STACK
CAL: 8-level
REG: 16-level
IR
RAM
640N
INT
1
SIN*
SFT
SOUT*
SCLK*
INT184
BD
BDB
INT
4
RESET
RST
BUZZER
TBC
BLD
INT
1
TST1
TST2
P0.0-P0.3
P1.0-P1.3
TST
INPUT
PORT
XT0
XT1
INT
1
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
OSC0
100HzTC
WDT
OSC
OSC1
TBCCLK*
HSCLK*
OUTPUT
PORT
INT
1
V
DDH
P8.0-P8.3
P9.0-P9.3
PA.0-PA.3
PD.0-PD.3
PE.0-PE.3
V
DD
BACKUP
CB1
CB2
I/O
PORT
V
DD1
DD2
DD3
DD4
DD5
C1
INT
2
V
V
V
V
BIAS
LCD
&
DSPR
COM1-16
SEG0-39
LCLK*
FRAME*
C2
V
DDI
V
DDL
V
SS
4/29
¡ Semiconductor
MSM63184A
PIN CONFIGURATION (TOP VIEW)
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
P6.0
P6.1
P6.2
P6.3
P1.0
P1.1
P1.2
P1.3
PA.0
PA.1
PA.2
PA.3
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
PE.0
PE.1
PE.2
PE.3
PD.0
PD.1
PD.2
PD.3
P0.0
P0.1
P0.2
P0.3
P4.0
P4.1
P4.2
P4.3
P5.0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/29
¡ Semiconductor
MSM63184A
PAD CONFIGURATION
Pad Layout
P7.3 98
P7.2 99
60 P5.1
59 P5.2
58 P5.3
57 TST1
56 TST2
55 XT0
54 XT1
53 RESET
52 OSC0
51 OSC1
50 VDDL
49 VDD
48 CB2
47 CB1
46 VDDH
45 C2
P7.1 100
P7.0 101
BD 102
BDB 103
VDDI 104
COM1 105
COM2 106
COM3 107
COM4 108
COM5 109
COM6 110
COM7 111
COM8 112
COM9 113
COM10 114
COM11 115
COM12 116
COM13 117
COM14 118
COM15 119
COM16 120
SEG39 121
SEG38 122
SEG37 123
44 C1
43 VDD5
42 VDD4
41 VDD3
40 VDD2
39 VDD1
38 VSS
Y
X
Chip Size
: 5.35 mm ¥ 4.66 mm
: 350 mm (typ.)
: Chip center
: 100 mm ¥ 100 mm
: 110 mm ¥ 110 mm
: 140 mm
Chip Thickness
Coordinate Origin
Pad Hole Size
Pad Size
Minimum Pad Pitch
Note: The chip substrate voltage is V .
SS
6/29
¡ Semiconductor
MSM63184A
Pad Coordinates
Pad
Name
Pad
Name
Pad
Name
Pad No.
X (µm) Y (µm) Pad No.
X (µm) Y (µm) Pad No.
X (µm) Y (µm)
1
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
–2520 –2135
–2380 –2135
–2240 –2135
–2100 –2135
–1960 –2135
–1820 –2135
–1680 –2135
–1540 –2135
–1400 –2135
–1260 –2135
–1120 –2135
–980 –2135
–840 –2135
–700 –2135
–560 –2135
–420 –2135
–280 –2135
–140 –2135
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
VDD4
VDD5
C1
2530 –1065
83
84
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
P1.3
P1.2
P1.1
P1.0
P6.3
P6.2
P6.1
P6.0
P7.3
P7.2
P7.1
P7.0
BD
–560
–700
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
1607
1467
1327
1187
1029
889
2
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2530
2520
2380
2240
2100
1960
1820
1680
1540
1400
1260
1120
980
–915
–765
–615
–465
–315
–165
–15
3
85
–840
4
C2
86
–980
5
VDDH
CB1
87
–1120
–1260
–1400
–1540
–1680
–1820
–1960
–2100
–2240
–2380
–2520
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
–2530
6
88
7
CB2
89
8
VDD
90
9
VDDL
OSC1
OSC0
RESET
XT1
135
91
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
285
92
435
93
585
94
735
95
XT0
885
96
TST2
TST1
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P0.3
P0.2
P0.1
P0.0
PD.3
PD.2
PD.1
PD.0
PE.3
PE.2
PE.1
PE.0
P8.3
P8.2
P8.1
P8.0
P9.3
1030
1170
1328
1468
1608
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
2135
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
0
–2135
140 –2135
280 –2135
420 –2135
560 –2135
700 –2135
840 –2135
980 –2135
1120 –2135
1260 –2135
1400 –2135
1540 –2135
1680 –2135
1820 –2135
1960 –2135
2100 –2135
2240 –2135
2380 –2135
2520 –2135
2530 –1665
2530 –1515
2530 –1365
2530 –1215
BDB
VDDI
749
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
609
469
329
189
49
–91
SEG8
–231
–371
–511
–651
–791
–931
SEG7
SEG6
SEG5
840
COM10 –2530
COM11 –2530
COM12 –2530
SEG4
700
SEG3
560
SEG2
420
COM13 –2530 –1071
COM14 –2530 –1211
SEG1
280
SEG0
140
COM15
COM16
SEG39
SEG38
SEG37
–1351
–1491
–1631
–1771
–1970
–2530
–2530
–2530
–2530
–2530
VSS
0
VDD1
–140
–280
–420
VDD2
VDD3
7/29
¡ Semiconductor
MSM63184A
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63184A are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
Fortype, "—"denotesapowersupplypin, "I"aninputpin, "O"anoutputpin, and"I/O"aninput-
output pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
Pin
52
40
41
42
43
44
45
46
47
Type
—
Description
VDD
VSS
Positive power supply
Negative power supply
—
VDD1
VDD2
VDD3
VDD4
VDD5
Power supply pins for LCD bias (internally generated).
Capacitors (0.1 mF) should be connected between these pins and
—
VSS.
C1
Power
—
—
Capacitor connection pins for LCD bias generation.
C2
A capacitor (0.1 mF) should be connected between C1 and C2.
Positive power supply pin for external interface
Supply
VDDI
VDDL
VDDH
110
53
—
—
—
(power supply for input, output, and input-output ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and VSS
.
Voltage multiplier pin for power supply backup (internally generated)
48
A capacitor (1.0 mF) should be connected between this pin and VSS
Pins to connect a capacitor for voltage multiplier.
.
CB1
CB2
49
50
—
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
Low-speed clock oscillation pins.
XT0
58
57
55
54
60
59
I
O
I
A 32.768 kHz crystal should be connected between XT0 and XT1,
XT1
Oscillation
and CG (5 to 25 pF) should be connected between XT0 and VSS
High-speed clock oscillation pins.
.
OSC0
A ceramic resonator and capacitors (CL0, CL1) or external
oscillation resistor (ROS) should be connected to these pins.
Input pins for testing.
OSC1
O
I
TST1
A pull-down resistor is internally connected to these pins.
The user cannot use these pins.
Test
TST2
I
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
Reset
RESET
56
I
A pull-down resistor is internally connected to this pin.
Buzzer output pin (non-inverted output)
Buzzer output pin (inverted output)
BD
108
109
O
O
Buzzer
BDB
8/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
P4.0/A0
Pin
73
Type
Description
4-bit input ports.
72
Pull-up resistor input, pull-down resistor input, or
high-impedance input is selectable for each bit.
I
71
70
97
96
I
95
94
69
4-bit output ports.
P4.1/A1
68
P-channel open drain output, N-channel open drain output,
O
O
O
O
CMOS output, or high-impedance output is selectable for each
bit.
P4.2/A2
67
P4.3/A3
66
Port
P5.0/A4
65
P5.1/A5
63
P5.2/A6
62
P5.3/A7
61
P6.0/A8
101
100
99
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
98
107
106
105
104
9/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Type
Description
Pin
85
84
83
82
89
88
87
86
93
92
91
90
77
76
75
74
81
80
79
78
4-bit input-output ports.
P8.0/RD
P8.1/WR
P8.2
In input mode, pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for each bit.
In output mode, P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance output is
selectable for each bit.
I/O
P8.3/INT4
P9.0/D0
P9.1/D1
I/O
I/O
I/O
I/O
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
Port
PA.2/D6
PA.3/D7
PD.0/FRAME
PD.1/LCLK
PD.2/TBCCLK
PD.3/HSCLK
PE.0/SIN
PE.1/SOUT
PE.2/SCLK
PE.3/INT2
10/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG0
Pin
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
38
Type
Description
LCD common signal output pins
O
LCD segment signal output pins
SEG1
37
SEG2
36
SEG3
35
LCD
SEG4
34
SEG5
33
SEG6
32
SEG7
31
SEG8
30
SEG9
29
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
28
27
26
O
25
24
23
22
21
20
19
18
17
16
15
14
11/29
¡ Semiconductor
MSM63184A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
Pin
13
12
11
10
9
Type
Description
LCD segment signal output pins
8
7
LCD
6
O
5
4
3
2
1
128
127
12/29
¡ Semiconductor
MSM63184A
Table 2 shows the secondary functions of each pin of the MSM63184A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin
Type
Description
External 2 interrupt input pins.
PE.3/INT2
78
I
The change of input signal level causes an interrupt to occur.
External 4 interrupt input pins.
P8.3/INT4
82
I
The change of input signal level causes an interrupt to occur.
External 5 interrupt input pins.
P0.0/INT5
P0.1/INT5
P0.2/INT5
P0.3/INT5
P1.0/INT5
P1.1/INT5
P1.2/INT5
P1.3/INT5
73
72
71
70
97
96
95
94
The change of input signal level causes an interrupt to occur.
The Port 0 Interrupt Enable register (P0IE) and Port 1 Interrupt
Enable register (P1IE) enable or disable an interrupt for each bit.
External
Interrupt
I
LCD
PD.0/FRAME
PD.1/LCLK
77
76
O
O
Frame output pin for LCD driver expansion
Clock output pin for LCD driver expansion
External
Expansion
Oscillation
Output
PD.2/TBCCLK
PD.3/HSCLK
PE.0/SIN
75
74
81
80
O
O
I
Low-speed oscillation clock output pin
High-speed oscillation clock output pin
Shift register receive data input pin
PE.1/SOUT
O
Shift register transmit data output pin
Shift
Shift register clock input-output pin.
Register
PE.2/SCLK
79
O
Clock output when this device is used as a master processor.
Clock input when this device is used as a slave processor.
13/29
¡ Semiconductor
MSM63184A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Symbol
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
PA.3/D7
P8.0/RD
P8.1/WR
Pin
69
Type
Description
Address output bus for external memory
68
67
66
65
63
62
61
O
101
100
99
98
External
Memory
107
106
105
104
89
Data bus for external memory
88
87
86
I/O
93
92
91
90
85
O
O
Read signal output pin for external memory (negative logic)
Write signal output pin for external memory (negative logic)
84
14/29
¡ Semiconductor
MSM63184A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Power Supply Voltage 7
Power Supply Voltage 8
Power Supply Voltage 9
Input Voltage 1
Symbol
VDD1
VDD2
VDD3
VDD4
VDD5
VDD
Condition
Ta = 25°C
Rating
Unit
V
–0.3 to +1.6
–0.3 to +2.9
–0.3 to +4.2
–0.3 to +5.5
–0.3 to +6.8
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +6.0
Ta = 25°C
V
Ta = 25°C
V
Ta = 25°C
V
Ta = 25°C
V
Ta = 25°C
V
VDDI
Ta = 25°C
V
VDDH
VDDL
VIN1
Ta = 25°C
V
Ta = 25°C
V
VDD Input, Ta = 25°C
VDDI Input, Ta = 25°C
VDD1 Output, Ta = 25°C
VDD2 Output, Ta = 25°C
VDD3 Output, Ta = 25°C
VDD4 Output, Ta = 25°C
VDD5 Output, Ta = 25°C
VDD Output, Ta = 25°C
VDDI Output, Ta = 25°C
VDDH Output, Ta = 25°C
—
–0.3 to VDD + 0.3
–0.3 to VDDI + 0.3
–0.3 to VDD1 + 0.3
–0.3 to VDD2 + 0.3
–0.3 to VDD3 + 0.3
–0.3 to VDD4 + 0.3
–0.3 to VDD5 + 0.3
–0.3 to VDD + 0.3
–0.3 to VDDI + 0.3
–0.3 to VDDH + 0.3
–55 to +150
V
V
V
V
V
V
V
V
V
V
°C
Input Voltage 2
VIN2
Output Voltage 1
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
TSTG
Output Voltage 2
Output Voltage 3
Output Voltage 4
Output Voltage 5
Output Voltage 6
Output Voltage 7
Output Voltage 8
Storage Temperature
15/29
¡ Semiconductor
MSM63184A
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Parameter
Symbol
Top
Condition
Range
–20 to +70
0.9 to 2.7
0.9 to 5.5
30 to 35
Unit
°C
Operating Temperature
—
VDD
—
V
Operating Voltage
VDDI
fXT
V
—
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
kHz
—
VDD = 1.2 to 2.7 V
VDD = 1.5 to 2.7 V
VDD = 1.2 to 2.7 V
VDD = 1.5 to 2.7 V
300k to 500k
200k to 1M
100 to 300
50 to 300
fCM
Hz
External RC Oscillator Resistance
ROS
kW
• When backup is not used
(VSS = 0 V)
Parameter
Symbol
Top
Condition
—
Range
–20 to +70
1.8 to 5.5
1.8 to 5.5
30 to 35
Unit
°C
Operating Temperature
VDD
—
V
Operating Voltage
VDDI
fXT
V
—
Crystal Oscillation Frequency
kHz
—
VDD = 1.8 to 5.5 V
VDD = 2.2 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 1.8 to 5.5 V
VDD = 2.2 to 5.5 V
VDD = 2.7 to 5.5 V
300k to 500k
300k to 1M
200k to 2M
100 to 300
50 to 300
30 to 300
Ceramic Oscillation Frequency
External RC Oscillator Resistance
fCM
Hz
ROS
kW
16/29
¡ Semiconductor
MSM63184A
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Mea-
suring
Circuit
Parameter
Symbol
Condition
Min.
Typ.
Max. Unit
1/5 bias, 1/4 bias
(Ta = 25°C)
—
VDD2 Voltage
VDD2
1.7
—
1.8
–4
1.9
—
V
VDD2 Voltage Temperature Deviation DVDD2
mV/°C
V
VDD1 Voltage
VDD1
1/5 bias, 1/4 bias
1/5 bias
Typ.– 0.2 1/2 ¥ VDD2 Typ.+ 0.2
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
VDD3 Voltage
VDD3
1/4 bias (connect
V
Typ.– 0.2 VDD2 Typ.+ 0.2
VDD3 and VDD2
1/5 bias
)
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
Typ.– 0.3 3/2 ¥ VDD2 Typ.+ 0.3
Typ.– 0.5 5/2 ¥ VDD2 Typ.+ 0.5
Typ.– 0.4 2 ¥ VDD2 Typ.+ 0.4
VDD4 Voltage
VDD5 Voltage
VDD4
V
V
1/4 bias
1/5 bias
VDD5
1/4 bias
High-speed clock oscillation
stopped
2.8
2.0
—
—
3.0
2.7
V
V
VDDH Voltage
VDD = 1.5 V
VDDH
(Backup used)
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
1
High-speed clock
oscillation stopped
0.8
1.2
1.0
1.3
—
—
1.8
5.5
—
V
V
V
VDDL Voltage
VDDL
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
Oscillation start time:
within 5 seconds
Crystal Oscillation Start Voltage
Crystal Oscillation Hold Voltage
VSTA
Backup
0.9
1.7
0.1
5
—
—
—
—
25
—
—
5.0
25
30
V
V
VHOLD
Backup not used
Crystal Oscillation Stop Detect Time
External Crystal Oscillator Capacitance
Internal Crystal Oscillator Capacitance
TSTOP
CG
—
—
—
ms
pF
pF
CD
20
CSA2.00MG (Murata
MFG.-make) used
External Ceramic Oscillator
Capacitance
CL0, 1
—
30
—
pF
VDD = 3.0 V
Internal RC Oscillator Capacitance
POR Voltage
COS
—
8
12
—
—
—
—
16
0.4
0.7
1.5
3.0
pF
V
VDD = 1.5 V
VDD = 3.0 V
VDD = 1.5 V
VDD = 3.0 V
0.0
0.0
1.2
2.0
VPOR1
V
V
Non-POR Voltage
VPOR2
V
Notes: 1. "T
" indicates that if the crystal oscillator stops over the value of T
, the system
STOP
STOP
reset occurs.
2. "POR" denotes Power On Reset.
3. "V " indicates that POR occurs when V falls from V to V
POR1
and again rises
DD
DD
POR1
up to V
.
DD
4. "V
" indicates that POR does not occur when V falls from V
to V
and
POR2
DD
DD
POR2
again rises up to V
.
DD
17/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
• When backup is used
(VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
Mea-
Parameter Symbol
Condition
CPU is in HALT state.
(High-speed clock oscillation
stopped)
Min. Typ. Max. Unit
suring
Circuit
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
5.3
5.3
6.5
8.0
Supply Current 1 IDD1
mA
mA
CPU is in HALT state.
LCD is in Power Down mode.
(High-speed clock oscillation
stopped)
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
4.2
4.2
5.0
6.5
Supply Current 2 IDD2
1
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
Supply Current 3 IDD3
Supply Current 4 IDD4
Supply Current 5 IDD5
—
—
—
15
20
mA
mA
mA
CPU is in operation at high-speed oscillation
(RC oscillation, f = approx. 720 kHz, ROS = 51 kW)
600
700
800
900
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
• When backup is not used
(VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, Ta = –20 to +70°C unless otherwise specified)
Mea-
suring
Circuit
Parameter Symbol
Condition
CPU is in HALT state.
(High-speed clock oscillation
stopped)
Min. Typ. Max. Unit
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
2.4
2.4
2.9
3.4
Supply Current 1 IDD1
mA
CPU is in HALT state.
LCD is in Power Down mode.
(High-speed clock oscillation
stopped)
Ta = –20 to +50°C
Ta = –20 to +70°C
—
—
1.8
1.8
2.2
2.8
Supply Current 2 IDD2
Supply Current 3 IDD3
mA
mA
CPU is in operation at low-speed oscillation.
(High-speed clock oscillation stopped)
1
—
7.2
9.0
f = approx. 800 kHz,
450
350
600
450
—
—
CPU is in operation at
high-speed oscillation
ROS = 51 kW
Supply Current 4 IDD4
Supply Current 5 IDD5
mA
f = approx. 500 kHz,
(RC oscillation)
ROS = 100 kW
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
—
850 1000 mA
18/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
Mea-
Parameter
Symbol
Condition
Unit
Min. Typ. Max.
suring
Circuit
Output Current 1
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
VDDI = 1.5 V
–2.0 –1.2 –0.2 mA
–5.0 –3.0 –1.0 mA
–8.0 –4.0 –1.5 mA
IOH1
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
VDDI = 5.0 V
V
DDI = 1.5 V
0.2
1.0
1.5
1.2
3.0
4.0
2.0
5.0
8.0
mA
mA
mA
(PD.0 to PD.3)
(PE.0 to PE.3)
IOL1
VOL1 = 0.5 V
VDDI = 3.0 V
VDDI = 5.0 V
Output Current 2
(BD, BDB)
V
DD = 1.5 V
VOH2 = VDD – 0.7 V VDD = 3.0 V
–2.5 –1.3 –0.4 mA
–6.0 –4.0 –2.0 mA
IOH2
VDD = VDDH = 5.0 V –9.0 –5.5 –3.0 mA
V
DD = 1.5 V
0.4
2.0
3.0
—
4
1.3
4.0
5.5
—
—
—
—
—
—
—
—
—
—
2.5
6.0
9.0
–4
—
–4
—
–4
—
–4
—
–4
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOL2
IOH3
VOL2 = 0.7 V
VDD = 3.0 V
VDD = VDDH = 5.0 V
Output Current 3
(SEG0 to SEG39)
(COM1 to COM16)
VOH3 = VDD5 – 0.2 V (VDD5 level)
IOHM3 VOHM3 = VDD4 + 0.2 V (VDD4 level)
IOHM3S VOHM3S = VDD4 – 0.2 V (VDD4 level)
IOMH3 VOMH3 = VDD3 + 0.2 V (VDD3 level)
IOMH3S VOMH3S = VDD3 – 0.2 V (VDD3 level)
IOML3 VOML3 = VDD2 + 0.2 V (VDD2 level)
IOML3S VOML3S = VDD2 – 0.2 V (VDD2 level)
IOLM3 VOLM3 = VDD1 + 0.2 V (VDD1 level)
IOLM3S VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
4
—
4
2
—
4
—
4
IOL3
VOL3 = VSS + 0.2 V (VSS level)
Output Current 4
(OSC1)
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V –2.5 –1.5 –0.75 mA
IOH4R
(RC oscillation)
VOL4R = 0.5 V
(RC oscillation)
VDD = VDDH = 5.0 V –3.5 –2.0 –1.0 mA
VDD = VDDH = 3.0 V 0.75
VDD = VDDH = 5.0 V 1.0
1.5
2.0
2.5
3.5
mA
mA
IOL4R
IOH4C
IOL4C
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V –300 –180 –60 mA
(ceramic oscillation)
VOL4C = 0.5 V
VDD = VDDH = 5.0 V –450 –280 –100 mA
VDD = VDDH = 3.0 V
60
120
200
300 mA
450 mA
(ceramic oscillation)
VDD = VDDH = 5.0 V 100
Output Leakage
(P4.0 to P4.3)
(P5.0 to P5.3)
(P6.0 to P6.3)
IOOH
VOH = VDDI
—
—
—
0.3
—
mA
mA
IOOL
VOL = VSS
–0.3
(PE.0 to PE.3)
19/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
Mea-
Parameter
Symbol
Condition
Unit
suring
Circuit
Min. Typ. Max.
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
VDDI = 1.5 V
2
10
90
30
mA
VIH1 = VDDI
IIH1
VDDI = 3.0 V
VDDI = 5.0 V
VDDI = 1.5 V
VDDI = 3.0 V
VDDI = 5.0 V
30
180 mA
600 mA
(when pulled down)
70
250
–10
–30
–2
–30 mA
–600 –250 –70 mA
mA
VIL1 = VSS
IIL1
–180 –90
(when pulled up)
(PE.0 to PE.3)
IIH1Z
IIL1Z
VIH1 = VDDI (in a high impedance state)
VIL1 = VSS (in a high impedance state)
0.0
—
—
1.0
0.0
mA
mA
–1.0
Input Current 2
(OSC0)
VIL2 = VSS
V
DD = VDDH = 3.0 V –200 –110 –30 mA
IIL2
(when pulled up)
VDD = VDDH = 5.0 V –600 –350 –150 mA
IIH2R
IIL2R
VIH2R = VDDH (RC oscillation)
VIL2R = VSS (RC oscillation)
0.0
–1.0
0.1
—
—
1.0
0.0
1.0
3.0
mA
mA
mA
mA
3
VIH2C = VDDH
V
DD = VDDH = 3.0 V
0.5
1.5
IIH2C
IIL2C
(ceramic oscillation)
VIL2C = VSS
VDD = VDDH = 5.0 V 0.75
V
DD = VDDH = 3.0 V –1.0 –0.5 –0.1 mA
(ceramic oscillation)
VDD = VDDH = 5.0 V –3.0 –1.5 –0.75 mA
Input Current 3
(RESET)
VDD = 1.5 V
VDD = 3.0 V
10
150
0.5
–1.0
50
50
350
1.0
—
80
mA
IIH3
IIL3
IIH4
IIL4
VIH3 = VDD
VIL3 = VSS
VIH4 = VDD
VIL4 = VSS
600 mA
VDD = VDDH = 5.0 V
2.0
0.0
mA
mA
Input Current 4
(TST1, TST2)
VDD = 1.5 V
VDD = 3.0 V
150
1.0
2.5
—
300 mA
0.5
1.5
4.0
0.0
mA
mA
mA
VDD = VDDH = 5.0 V 1.25
–1.0
20/29
¡ Semiconductor
MSM63184A
DC Characteristics (continued)
(VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V,
VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = –20 to +70°C unless otherwise specified)
Mea-
Parameter
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
Symbol
Condition
Unit
suring
Circuit
Min. Typ. Max.
VDDI = 1.5 V
VDDI = 3.0 V
1.2
2.4
4.0
0.0
0.0
0.0
2.4
4.0
0.0
0.0
1.35
2.4
4.0
0.0
0.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
3.0
5.0
0.3
0.6
1.0
3.0
5.0
0.6
1.0
1.5
3.0
5.0
0.15
0.6
1.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIH1
VDDI = 5.0 V
VDDI = 1.5 V
VIL1
VDDI = 3.0 V
(PE.0 to PE.3)
VDDI = 5.0 V
Input Voltage 2
(OSC0)
VDD = VDDH = 3.0 V
VDD = VDDH = 5.0 V
VDD = VDDH = 3.0 V
VDD = VDDH = 5.0 V
VIH2
VIL2
Input Voltage 3
(RESET, TST1, TST2)
VDD = 1.5 V
VIH3
VDD = 3.0 V
VDD = VDDH = 5.0 V
VDD = 1.5 V
4
VIL3
VDD = 3.0 V
VDD = VDDH = 5.0 V
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
VDDI = 1.5 V
VDDI = 3.0 V
0.05
0.2
0.1
0.5
1.0
0.3
1.0
1.5
V
V
V
DVT1
V
DDI = 5.0 V
0.25
(PE.0 to PE.3)
Hysteresis Width 2
VDD = 1.5 V
VDD = 3.0 V
0.05
0.2
0.1
0.5
1.0
0.3
1.0
1.5
V
V
V
(RESET, TST1, TST2)
DVT2
VDD = VDDH = 5.0 V
0.25
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(P9.0 to P9.3)
CIN
—
—
—
5
pF
1
(PD.0 to PD.3)
(PE.0 to PE.3)
21/29
¡ Semiconductor
MSM63184A
Measuring circuit 1
CB1
CG
Cb12
XT0
XT1
CB2
C1
32.768 kHz
Crystal
C12
C2
q
*1
OSC0
w
OSC1
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
A
Ca
Cb
Cc
Cd
Ce
Ch
Cl
V
V
V
V
V
V
V
Ca, Cb, Cc, Cd, Ce, Cl, C12 : 0.1 mF
*1 RC Oscillator
ROS
Cb12, Ch
: 1 mF
q
CG
: 15 pF
: 30 pF
: 30 pF
CL0
CL1
w
Ceramic Resonator
: CSA2.00MG (2 MHz)
CSB1000J (1 MHz)
(Murata MFG.-make)
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
*3
VIH
A
*2
INPUT
OUTPUT
VIL
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
22/29
¡ Semiconductor
MSM63184A
Measuring circuit 3
*4
A
INPUT
OUTPUT
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
Measuring circuit 4
VIH
Waveform
Monitoring
*4
INPUT
OUTPUT
VIL
VSS VDD VDDI VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
23/29
¡ Semiconductor
MSM63184A
AC Characteristics (Serial Interface, Shift Register)
(V =0.9 to 5.5V, V
=1.8to5.5V, V =0V, V =5.0V, Ta=–20to+70°Cunlessotherwise
DDI
DD
DDH
SS
specified)
Min.
Typ.
Max.
Parameter
Symbol
Condition
Unit
SCLK Input Fall Time
SCLK Input Rise Time
tf
tr
—
—
—
—
—
—
1.0
1.0
ms
ms
SCLK Input "L" Level
Pulse Width
tCWL
—
0.8
0.8
—
—
—
—
ms
ms
SCLK Input "H" Level
Pulse Width
tCWH
tCYC
—
SCLK Input Cycle Time
VDDI = 5 V to VDD
1.8
—
—
—
—
ms
ms
tCYC1(O) CPU in operation state at 32 kHz
30.5
SCLK Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
—
0.5
—
ms
VDD = VDDH = 2.7 V to 5.5 V
SOUT Output Delay Time
SIN Input Setup Time
SIN Input Hold Time
tDDR
tDS
Cl = 10 pF
—
0.5
0.8
—
—
—
0.4
—
—
ms
ms
ms
—
—
tDH
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
SCLK (PE.2)
5 V (VDDI
)
0 V (VSS
)
tr
tf
tCWH
tCWL
tDDR
tDDR
5 V (VDDI
)
SOUT (PE.1)
SIN (PE.0)
0 V (VSS
)
tDS
tDH
tDS
5 V (VDDI
)
0 V (VSS
)
24/29
¡ Semiconductor
MSM63184A
AC Characteristics (External Memory Interface)
(V =0.9 to 5.5V, V
=1.8to5.5V, V =0V, V =5.0V, Ta=–20to+70°Cunlessotherwise
DDI
DD
DDH
SS
specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Read Cycle Time
Symbol
tRC
Condition
Min.
—
Typ.
61.0
—
Max.
—
Unit
ms
—
—
—
—
RD Output Delay Time
Output Valid Time
tOE
—
5.0
ms
tOHA
tDO
—
—
5.0
ms
External Memory Output Delay Time
—
—
5.0
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
Read Cycle Time
Symbol
tRC
Condition
Min.
1.0
—
Typ.
—
Max.
—
Unit
ms
—
—
—
—
RD Output Delay Time
Output Valid Time
tOE
—
100
100
150
ns
tOHA
tDO
—
—
ns
External Memory Output Delay Time
—
—
ns
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S2 S1
S1
S2
S1
S2
System clock
tRC
Address output Port setup value
5 V (VDDI
)
P7 - P4
(A15 - A0)
Port setup value
Port setup value
0 V (VSS
)
5 V (VDDI
)
P8.0
(RD)
0 V (VSS
)
tOE
tOHA
5 V (VDDI
)
PA, P9
(D7 - D0)
Input data
tDO
Port setup value
0 V (VSS
)
25/29
¡ Semiconductor
MSM63184A
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Write Cycle Time
Symbol
Condition
Min.
—
Typ.
61.0
30.5
15.3
15.3
45.8
15.3
Max.
—
Unit
ms
tWC
tAS
tW
—
—
—
—
—
—
Address Setup Time
Write Time
—
—
ms
—
—
ms
Write Recovery Time
Data Setup Time
Data Hold Time
tWR
tDS
tDH
—
—
ms
—
—
ms
—
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
Write Cycle Time
Symbol
tWC
Condition
Min.
1.0
0.4
0.2
0.2
0.7
0.2
Typ.
—
Max.
—
Unit
ms
—
—
—
—
—
—
Address Setup Time
Write Time
tAS
—
—
ms
tW
—
—
ms
Write Recovery Time
Data Setup Time
Data Hold Time
tWR
—
—
ms
tDS
—
—
ms
tDH
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1 S2 S1 S2 S1
S2
System clock
tWC
Address output Port setup value
5 V (VDDI
)
P7 - P4
(A15 - A0)
Port setup value
Port setup value
0 V (VSS
)
PA, P9
(D7 - D0)
5 V (VDDI
)
Output data
Port setup value
0 V (VSS
)
tDS
tDH
5 V (VDDI
)
P8.1
(WR)
0 V (VSS
)
tAS
tW tWR
26/29
¡ Semiconductor
MSM63184A
APPLICATION CIRCUITS
•RC oscillation is selected as high-speed
oscillation.
•Ports are powered from external memory
power source.
LCD
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12,
Ch, and CG, are for reference only.
Crystal
32.768 kHz
COM1-16
SEG0-39
XT0
OSC0
OSC1
ROS
CG
5 to
25 pF
1.5 V
XT1
VDDH
Ch
1.0 mF
VDD
P8.3
P8.2
Cv 0.1 mF
CB1
PE.3
PE.2
PE.1
PE.0
PD.3
PD.2
PD.1
PD.0
Cb12
Cl
1.0 mF
0.1 mF
CB2
VDDL
Ce
Cd
Cc
Cb
Ca
0.1 mF
0.1 mF
0.1 mF
0.1 mF
0.1 mF
VDD5
VDD4
VDD3
VDD2
SW Matrix
(8 ¥ 8)
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
MSM63184A
VDD1
C1
C12
0.1 mF
C2
Push SW
RESET
TST1
TST2
BD
Open
VDDI
Buzzer
VDD
BDB
VSS
A15-0
P4-7
External
Memory
(64K ¥ 8 bits)
5.0 V
P9, PA
P8.0
P8.1
D7-0
RD
WR
VSS
Note:
V
DDI
is the power supply pin for the input, output, and input-output ports.
Be sure to connect the V
pin either to the positive power supply pin (V ) of this
DD
DDI
device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
27/29
¡ Semiconductor
MSM63184A
APPLICATION CIRCUITS (continued)
•Ceramic oscillation is selected as high-speed
oscillation.
•Ports, external memory, and IC share their
power supply.
LCD
•Cv is an IC power supply bypass capacitor.
•Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG,
CL0, and CL1 are for reference only.
Crystal
32.768 kHz
CL0 30 pF
COM1-16
SEG0-39
XT0
OSC0
OSC1
Ceramic
Resonator
CG
(Example: 1 MHz)
5 to 25 pF
XT1
VDD
CL1
VDDH
30 pF
5.0 V
VDD
P8.3
P8.2
CB1
CB2
VDDL
Open
0.1 mF
PE.3
PE.2
PE.1
PE.0
PD.3
PD.2
PD.1
PD.0
Cv
Cl
Ce
Cd
Cc
Cb
Ca
0.1 mF
0.1 mF
VDD5
VDD4
VDD3
SW Matrix
(8 ¥ 8)
0.1 mF
0.1 mF
0.1 mF
0.1 mF
P1.3
P1.2
P1.1
P1.0
P0.3
P0.2
P0.1
P0.0
MSM63184A
VDD2
VDD1
C1
C12
0.1 mF
C2
Push SW
RESET
TST1
TST2
BD
Open
VDDI
VDD
Buzzer
VDD
A15-0
P4-7
BDB
VSS
External
P9, PA
P8.0
P8.1
D7-0
RD
WR
Memory
(64K ¥ 8 bits)
VSS
Note:
V
DDI
is the power supply pin for the input, output, and input-output ports.
Be sure to connect the V
pin either to the positive power supply pin (V ) of this
DD
DDI
device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
28/29
¡ Semiconductor
MSM63184A
PACKAGE DIMENSIONS
(Unit : mm)
QFP128-P-1420-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.19 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
29/29
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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