MSM7603 [OKI]
Echo Canceler; 回波消除器
| 型号： | MSM7603 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | Echo Canceler |
| 文件： | 总20页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2U0064-18-82
This version: Aug. 1998
¡ Semiconductor
MSM7603/7603B
Echo Canceler
GENERAL DESCRIPTION
The MSM7603/7603B is an improved version of the MSM7602 with basically the same
configuration, and offers twice the cancelable echo delay time of the MSM7602.
The MSM7603B I/O interface allows switching between m-law PCM and A-law PCM.
The MSM7603/7603B is a low-power CMOS IC device for canceling echo (in an acoustic system
or telephone line) generated in a speech path.
Echo is canceled, in digital signal processing, by estimating the echo path and generating a
pseudo echo signal.
Whenusedasanacousticechocanceler,thedevicecancanceltheacousticecho,betweentheloud
speakerandthemicrophone,whichoccurduringhandsfreecommunicationsuchasonacellular
phone or a conference system phone.
When used as a line echo canceler, the device can cancel the line echo which returns due to
impedance mismatching in a hybrid.
In addition, a quality conversation is made possible by controlling the level and by preventing
howling through a howling detector, double talk detector, attenuation function and a gain
control function, and by controlling the low level noise by means of a center clipping function.
Theuseofasinglechipcodec,suchastheMSM7704(3V)andMSM7533(5V),allowsaneconomic
and efficient echo canceler to be configured.
FEATURES
• Can handle both acoustic and telephone line echoes.
• Switchable between m-law PCM and A-law PCM interfaces. (MSM7603B)
• Cancelable echo delay time:
MSM7603B-003 .............. 55 ms (max.)
• Echo attenuation
• Clock frequency
: 30 dB (typ.)
: 19.2 MHz
17.5 MHz to 20 MHz (when internal sync signal not used)
• Power supply voltage : 2.7 V to 5.5 V
• Package:
28-pin plastic SSOP (SSOP28-P-485-0.65-K) (Product name : MSM7603-003GS-K)
(Product name : MSM7603B-003GS-K)
1/20
¡ Semiconductor
MSM7603/7603B
BLOCK DIAGRAM
MSM7603/7603B
Non–linear/
Linear
Linear/
Non–linear
RIN
S/P
ATT
Gain
P/S
ROUT
Howling
Detector
Double Talk
Detector
Power
Calculator
Adaptive
FIR Filter
(AFF)
–
+
+
Linear/
Non–linear
Center
Clip
Non–linear/
Linear
SOUT
P/S
ATT
S/P
SIN
RST
VDD
VSS
PWDWN
Clock Generator
PLL
Mode Selector
I/O Controller
CLKIN
SCKO SYNCO
NLP HCL ADP ATT GC HD m/A
SCK SYNC
*
For MSM7603B only
2/20
¡ Semiconductor
MSM7603/7603B
PIN CONFIGURATION (TOP VIEW)
NLP 1
HCL 2
ADP 3
SYNC 4
SCK 5
28 VDD
27 SOUT
26 ROUT
25 SIN
24 RIN
VDD
VSS
6
7
23 VSS
22 NC
RST 8
PWDWN 9
HD 10
21 NC[TEST]*
20 VDD
19 ATT
V
DD[m/A]* 11
18 SCKO
17 GC
CLKIN 12
V
DD(PLL) 13
16 SYNCO
15 VSS
V
SS(PLL) 14
NC : No connect pin
28-Pin Plastic SSOP
*
Pins shown in brackets apply to MSM7603B.
3/20
¡ Semiconductor
MSM7603/7603B
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
This is the control pin for the center clipping function to force
the SOUT output to a minimum value when the SOUT signal is
below –57 dBm0. Effective for reducing low-level noise.
"H": Center clip ON
1
NLP
I
"L": Center clip OFF
2
3
HCL
ADP
I
I
This is the through mode control pin.
When this pin is in the through mode the RIN and SIN data are
output to ROUT and SOUT. At the same time, the coefficient of
the adaptive FIR filter is cleared.
"H": Through mode
"L": Normal mode (echo canceler operates)
This is the AFF coefficient control pin which stops updating the
adaptive FIR filter (AFF) coefficient and sets it to a fixed value,
when the pin is configured to be the coefficient fix mode.
Used when holding the AFF coefficient which has been once
converged.
"H": Coefficient fix mode
"L": Normal mode (coefficient update)
This is the input pin for the sync signal for transmit/receive
serial data. This pin uses the external SYNC or SYNCO.
Inputs the PCM codec transmit/receive sync signal (8 kHz).
This is the clock input pin for transmit/receive serial data. It
uses the external SCK or the SCKO.
4
5
SYNC
SCK
I
I
Input the PCM codec transmit/receive clock (64 to 2048 kHz).
4/20
¡ Semiconductor
MSM7603/7603B
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
This is the input pin for the reset signal.
"L": Reset mode
8
RST
I
"H": Normal operation mode
Due to initialization, input signals are disabled for 100 ms after reset
(after RST is returned from "L" to "H").
Input the basic clock during the reset.
Output pins during the reset are in the following sates :
High impedance: SOUT, ROUT
Not affected: SYNCO, SCKO
This is the power-down mode control pin for power down operation
"L": Power-down mode
9
PWDWN
I
"H": Normal operation mode
During power-down mode, all input pins are disabled and output
pins are in the following states :
High impedance : SOUT, ROUT
"L": SYNCO, SCKO
Reset after the power-down mode is released.
10
11
HD
I
I
This pin controls the howling detect function that detects and
cancels a howling generated during hands-free talking for
acoustic system.
This function is used to cancel acoustic echoes.
"L": Howling detector ON
"H": Howling detector OFF
Used for MSM7603B only.
(m/A)
CLKIN
This is the input pin for m-law PCM/A-law PCM interface select
signal.
"L": A-law PCM interface
"H": m-law PCM interface
For MSM7603, apply VDD
.
This is the input pin for external input for the basic clock.
Input the basic clock (17.5 to 20 MHz).
12
13
I
I
When the internal sync signal (SYNCO, SCKO) is used, input the
basic clock of 19.2 MHz.
This is the power supply pin for the PLL circuit used for the basic
clock.
V
DD (PLL)
Insert a 0.1 mF capacitor with excellent high frequency
characteristics between VDD (PLL) and VSS (PLL).
This is the ground pin for the PLL circuit used for the basic clock.
This is the output pin for the 8 kHz sync signal for the PCM codec.
Connect to the SYNC pin andthe PCMcodec transmit/receivesync
pin.
14
16
VSS (PLL)
SYNCO
I
O
Leave open if using an external SYNC.
5/20
¡ Semiconductor
MSM7603/7603B
PIN DESCRIPTIONS (Continued)
Pin
Symbol
Type
Description
17
GC
I
This is the pin for the input signal by which the gain controller
for the RIN input is controlled. The pin also controls RIN input
level and prevents howling.
The gain controller adjusts the RIN input level when it is –20
dBm0 or above. RIN input levels from –20 to –11.5 dBm0 will be
suppressed to –20 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above –11.5 dBm0 will always be attenuated by
8.5 dB.
"H": Gain control ON
"L": Gain control OFF
"H" is recommended for performing echo cancellation.
18
19
SCKO
ATT
O
This is the output pin for the transmit clock signal (256 kHz) for
the PCM codec.
Connect to the SCK pinandthePCM codectransmit/receiveclock
pin.
Leave open when using an external SCK.
This is the control pin for the ATT function which prevents howling
by attenuators (ATT) for the RIN input and SOUT output.
If there is input only to RIN, then the ATT for the SOUT output is
activated.
I
If there is no input to SIN or there is input to both SIN and RIN,
then the ATT for the RIN input is activated.
Either the ATT for the RIN output or the ATT for the SOUT is
always activated in all cases, and the attenuation of ATT is 6 dB.
"H": ATT OFF
"L": ATT ON
"L" is recommended for performing echo cancellation.
21
24
(TEST)
RIN
O
I
This pin is for MSM7603B only and not used. Should be left open.
In MSM7603 it is an NC pin.
This is the receive serial data input pin.
Input the PCM signal synchronized to SYNC and SCK.
Data is read at the falling edge of SCK.
25
26
27
SIN
I
This is the transmit serial data input pin.
Input the PCM signal synchronized to SYNC and SCK.
Data is read at the falling edge of SCK.
This is the output pin for receive serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in high impedance state during the absence of data output.
ROUT
SOUT
O
O
This is the output pin for transmit serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in high impedance state during the absence of data output.
6/20
¡ Semiconductor
MSM7603/7603B
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Input Voltage
Symbol
VDD
Condition
Ta = 25˚C
—
Rating
Unit
V
–0.3 to + 7
–0.3 to VDD + 0.3
1
VIN
V
Power Dissipation
Storage Temperature
PD
W
TSTG
–55 to +150
˚C
RECOMMENDED OPERATING CONDITIONS
(VDD = 2.7 V to 3.6 V)
Parameter
Power Supply Voltage
Power Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Operating Temperature
Symbol
VDD
VSS
VIH
Condition
Min.
2.7
—
Typ.
3.3
0
Max.
3.6
Unit
V
—
—
—
—
—
—
V
2.0
0
—
VDD
0.5
V
VIL
—
V
Ta
–40
+25
+85
˚C
(VDD = 4.5 V to 5.5 V)
Parameter
Power Supply Voltage
Power Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Operating Temperature
Symbol
VDD
VSS
VIH
Condition
Min.
4.5
—
Typ.
5
Max.
5.5
Unit
V
—
—
—
—
—
0
—
V
2.4
0
—
—
+25
VDD
0.8
V
VIL
V
Ta
–40
+85
˚C
7/20
¡ Semiconductor
MSM7603/7603B
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 V to 3.6 V, Ta = –40˚C to +85˚C)
Symbol
VOH
Parameter
Condition
IOH = 40 mA
IOL = 1.6 mA
Min.
2.2
0
Typ.
—
Max.
VDD
0.4
1
Unit
V
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
—
V
VOL
—
0.1
mA
mA
mA
IIH VIH = VDD
VIL = VSS
–1
–0.1
0.1
—
IIL
High Level Output Leakage Current
VOH = VDD
—
1
IOZH
Low Level Output Leakage Current
IOZL
IDDO
IDDS
VOL = VSS
–1
—
—
–0.1
30
—
50
1
mA
mA
mA
Power Supply Current
(Operating)
—
Power Supply Current
(Standby)
PWDWN = "L"
0.5
Input Capacitance
Output Load Capacitance
CI
—
—
—
—
15
20
pF
pF
—
—
CLOAD
(VDD = 4.5 V to 5.5 V, Ta = –40˚C to +85˚C)
Parameter
Symbol
VOH
VOL
IIH
Condition
IOH = 40 mA
Min.
4.2
0
Typ.
—
Max.
VDD
0.4
10
Unit
V
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Output Leakage Current
IOL = 1.6 mA
VIH = VDD
VIL = VSS
—
V
—
0.1
mA
mA
mA
IIL
–10
—
–0.1
0.1
—
IOZH
VOH = VDD
10
VOL = VSS
–10
—
–0.1
40
—
70
1
mA
mA
mA
IOZL
IDDO
IDDS
Low Level Output Leakage Current
Power Supply Current
(Operating)
—
Power Supply Current
(Standby)
—
0.5
PWDWN = "L"
CI
Input Capacitance
Output Load Capacitance
—
—
—
—
—
15
20
pF
pF
CLOAD
—
8/20
¡ Semiconductor
MSM7603/7603B
Echo Canceler Characteristics (Refer to Characteristics Diagram)
Parameter
Symbol
Condition
RIN = –10 dBm0
Min.
Typ.
Max.
Unit
(5 kHz band white noise)
E. R. L. (echo return loss)
= 6 dB
LRES
Echo Attenuation
—
30
—
dB
TD = 50 ms
ATT, GC, NLP: OFF
RIN = –10 dBm0
(5 kHz band white noise)
E. R. L. = 6 dB
TD
Cancelable Echo Delay Time
—
—
55
ms
ATT, GC, NLP: OFF
9/20
¡ Semiconductor
MSM7603/7603B
AC Characteristics
(Ta = –40˚C to +85˚C)
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
Parameter
Symbol
Unit
Min.
Typ.
19.2
—
Max.
Min.
—
Typ.
19.2
—
Max.
—
Clock Frequency
—
17.5
—
—
20.0
—
fC
MHz
When Internal Sync Signal is not used
Clock Cycle Time
17.5
—
20.0
—
52.08
—
52.08
—
tMCK
tDMC
tMCH
ns
ns
ns
When Internal Sync Signal is not used
Clock Duty Ratio
50.0
40
57.14
60
50.0
40
57.14
60
—
—
Clock "H" Level Pulse Width
20.8
20.8
—
—
31.3
31.3
20.8
20.8
—
—
31.3
31.3
f = 19.2 MHz
c
Clock "L" Level Pulse Width
tMCL
ns
f = 19.2 MHz
c
Clock Rise Time
tr
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
1
—
—
5
5
—
—
—
—
—
—
—
—
—
64
0.488
40
123
45
45
tSCK
45
45
—
—
—
1
—
—
5
5
ns
ns
Clock Fall Time
tf
Sync Clock Output Time
Internal Sync Clock Frequency
Internal Sync Clock Output Cycle Time
Internal Sync Clock Duty Ratio
Internal Sync Signal Output Delay Time
Internal Sync Signal Period
tDCM
fCO
—
40
—
40
ns
256
3.9
50
—
256
3.9
50
—
kHz
ms
%
tCO
—
—
tDCO
tDCC
tCYO
—
—
—
5
—
5
ns
125
tCO
—
—
125
tCO
—
—
ms
ms
kHz
ms
%
Internal Sync Signal Output Width tWSO
fSCK
—
—
Transmit/Receive Sync Clock Frequency
Transmit/Receive Sync Clock Cycle Time tSCK
2048
15.6
60
2048
15.6
60
—
—
Transmit/Receive Sync Clock Duty Ratio
Transmit/Receive Sync Signal Period
tDSC
tCYC
tXS
50
50
125
—
—
125
—
—
ms
ns
—
—
Sync Timing
tSX
—
tCYC-tSCK
—
—
tCYC-tSCK
—
ns
Sync Signal Width
tWSY
tDS
—
—
ms
ns
Receive Signal Setup Time
Receive Signal Hold Time
Receive Data Input Time
—
—
—
—
tDH
—
—
—
—
ns
tID
7tSCK
—
—
7tSCK
—
—
ms
ns
tSD
90
90
Serial Output Delay Time
tXD
—
90
—
90
ns
Reset Signal Input Width
Reset Start Time
tWR
tDRS
tDRE
tDIT
tDPS
tDPE
—
—
—
—
ms
ns
5
—
—
5
—
—
Reset End Time
—
100
—
—
10
20
20
0
—
52
—
100
—
—
10
20
20
0
—
52
ns
Processing Operation Start Time
Power Down Start Time
Power Down End Time
—
—
—
—
ms
ns
—
111
15
—
111
15
—
—
ns
Reset Pulse Width Immediately after Power Down tWPR
—
—
—
—
ns
Control Pin Setup Time (RST)
Control Pin Hold Time (RST)
Control Pin Setup Time
tDSR
tDHR
tDTS
tDTH
—
—
—
—
ns
—
—
—
—
ns
—
—
—
—
ns
Control Pin Hold Time
160
—
—
160
—
—
ns
10/20
¡ Semiconductor
MSM7603/7603B
TIMING DIAGRAM
Clock Timing
tr
tf
fC, tMCK, tDMC
tMCH
tMCL
CLKIN
tDCM
tDCM
SCKO
fCO, tCO
SCKO
tDCO
tDCC
tDCC
tCYO
SYNCO
tWSO
Serial Input Timing
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tDH
tDS
SIN
RIN
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
tID
11/20
¡ Semiconductor
MSM7603/7603B
Serial Output Timing
fSCK, tSCK
tDSC
SCK
tSX
tXS
tCYC
SYNC
tWSY
tXD
tSD
tXD
SOUT
ROUT
High-Z
High-Z
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
Operation Timing After Reset
tWR
*Reset timing can be asynchronous.
tDIT
RST
tDRS
tDRE
Reset
Internal operaion
Initialization
Processing Start
* INT is invalid during the shaded interval.
Power Down Timing
PWDWN
tDPS
tDPE
Power Down
Internal Operation
Processing Start
tWPR
RST
Invalid
12/20
¡ Semiconductor
MSM7603/7603B
Control Pin Load-in Timing
tWR
RST
tDHR
tDSR
NLP, HCL, HD,
ATT, ADP, GC
SCK
tCYC
SYNC
SIN
RIN
MSB
7
LSB
0
MSB
7
6
5
4
3
2
1
tID
tDTH
tDTS
NLP, HCL, HD,
ATT, ADP, GC
13/20
¡ Semiconductor
MSM7603/7603B
HOW TO USE THE MSM7603/7603B
The MSM7603/7603B cancels, based on the RIN signal, the echo which returns to SIN.
Connect the base signal to the R side and the echo-generated signal to the S side.
Connection Methods According to Echoes
Example 1:
Canceling acoustic echo (to handle acoustic echo from line input)
MSM7603
MSM7603B
ROUT
SIN
RIN
Line input
AFF
H
Acoustic echo
CODEC
CODEC
–
SOUT
+
+
Example 2:
Canceling line echo (to handle line echo from microphone input)
MSM7603
MSM7603B
Microphone input
RIN
ROUT
SIN
AFF
H
CODEC
CODEC
–
SOUT
+
+
Lin echo
Example 3: Canceling of both acoustic and line echo
(to handle both acoustic echo from line input and line echo from microphone input)
MSM7603
MSM7603
MSM7603B
MSM7603B
Line input
H
ROUT
SIN
RIN
SOUT
RIN
SIN
+
+
–
AFF
Acoustic echo
CODEC
CODEC
AFF
–
+
SOUT
ROUT
+
Line echo
Microphone input
For acoustic echo
For line echo
14/20
¡ Semiconductor
MSM7603/7603B
ECHO CANCELER CHARACTERISTICS DIAGRAM
(for m-law and A-law, and for reference only)
E. R. L. vs. echo attenuation
RIN input level vs. echo attenuation
40
30
20
10
0
40
30
20
10
0
40 30 20 10
E. R. L. [dB]
0
–10
–50 –40 –30 –20 –10
RIN input level [dBm0]
0
Measurement Conditions :
Measurement Conditions :
RIN input = –10 dBm0 5 kHz band white noise
Echo delay time TD = 50 ms
ATT, GC, NLP = OFF
RIN input: 5 kHz band white noise
Echo delay time TD = 50 ms
E.R.L. = 6 dB
Power supply voltage 5 V
ATT, GC, NLP = OFF
Power supply voltage 5 V
Echo delay time vs. echo attenuation
30
20
10
0
Measurement Conditions :
RIN input = –10 dBm
5 kHz band white noise
E.R.L. = 6 dB
ATT, GC, NLP = OFF
Power supply voltage 5 V
0
10
20
30
40
50
Echo delay time [ms]
Note:
Above characteristics are for the MSM7533 (V 5 V, m-law CODEC interface). For the
DD
MSM7704 (V 3 V, m-law interface) the characteristics are basically the same except
DD
for input and output levels. Refer to the PCM CODEC data sheet.
MSM7533 (for both transmit and receive)
0 dBm0 = 0.85 Vrms = 0.8 dBm (600 W)
MSM7704 (for transmit side)
0 dBm0 = 0.35 Vrms = –6.9 dBm (600 W)
(for receive side)
0 dBm0 = 0.5 Vrms = –3.8 dBm (600 W)
15/20
¡ Semiconductor
MSM7603/7603B
Measurement System Block Diagram
White noise generator
TD
L. P. F. RIN
5 kHz
RIN
ROUT
Delay
MSM7603
Echo delay time
MSM7603B
SOUT SIN
Level meter
SOUT
ATT
E. R. L.
(Echo Return Loss)
Power supply voltage 5 V
2ch CODEC
MSM7533
16/20
¡ Semiconductor
MSM7603/7603B
APPLICATION CIRCUIT
Bidirectional Connection Example
2ch CODEC
MSM7533VGS-K
Microphone input
C1
R1
R5
C5
21
22
4
24
23
2
AIN1
GSX1
AOUT1
AIN2
GSX2
AOUT2
Line input
R2
R6
Line output
R3
R7
DV
DV
Speaker output
13
12
14
10
16
19
5
14
11
DOUT1 DOUT2
DIN1
XSYNC
RSYNC
BCLK
A / m
DIN2
8
1
VDD
SGC
AV
+
C10 C11
18 C9
9
PDN
CHP
AG
DG
(AG)
6
DV
DV
DV
DV
For cancelation of
acoustic echo
MSM7603/7603B
DV
R4
DV
For cancelation of line echo
MSM7603/7603B
R9 R10
R8
25
27
24
27
24
25
26
SIN
ROUT
SOUT
RIN
SOUT
RIN
SIN
ROUT
26
DV
4
5
1
2
3
1
2
3
4
5
SYNC
SCK
NLP
NLP
HCL
ADP
ATT
GC
HD
SYNC
SCK
HCL
ADP
ATT
GC
HD
16
18
16
18
19
17
10
11
21
13
14
7
19
17
10
11
21
13
14
7
SYNCO
SCKO
SYNCO
SCKO
9
8
12
9
8
12
PWDWN
RST
PWDWN
PWDWN
RST
CLKIN
(m / A)
(TEST)
(m / A)
(TEST)
RST
CLK
C4
DV C8
CLKIN
VDD(P)
VSS(P)
VSS
V
DD(P)
SS(P)
V
DV
DV
6
20
28
6
20
28
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
15
23
15
23
VSS
VSS
+
C2
C3
C6
C7
+
R1=20 kW
R2=20 kW
R3=2.2 kW
R4=10 kW
R9=10 kW
C1=1 mF
R5=20 kW
R6=20 kW
R7=2.2 kW
R8=10 kW
R10=10 kW
C5=1 mF
C2=10 mF
C3=0.1 mF
C4=0.1 mF
C6=10 mF
C7=0.1 mF
C8=0.1 mF
C9=0.1 mF
C10=10 mF
C11=0.1 mF
Use the MSM7704-01GS-VK as a PCM CODEC when VDD 3 V is used.
The MSM7533 is pin compatible with the MSM7704.
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¡ Semiconductor
MSM7603/7603B
NOTES ON USE
1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be
amplified, the echo cannot be eliminated.
Refer to the characteristics diagram for E. R. L. vs. echo attenuation quantity.
2. Set the level of the analog input so that the PCM codec does not overflow.
3. The recommended input level is –10 to –20 dBm0. Refer to the characteristics
diagram for the RIN input level vs. echo attenuation quantity.
4. Applying the tone signal to this echo canceler for long duration may decrease echo
attenuation.
When used with the HD pin "L" (howling detector ON), this echo canceler may
operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher
level than the signal being input to RIN is input to the SIN pin.
A signal should therefore be input either to the RIN pin or to the SIN pin. If,
however, thetonesignalisinputtotheSINpinwhileasignalisinputtotheRINpin,
the ADP, HD, or HCL pin must be set to "H".
5. For changes in the echo path (retransmit, circuit switching during transmission,
and so on), convergence may be difficult.
Perform a reset to make it converge.
Ifthestateoftheechopathchangesafterareset, convergencemayagainbedifficult.
In cases such as a change in the echo path, perform a reset each time.
6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock
simultaneously with power ON.
If the device is put into power down mode immediately after power ON, be sure
to input 10 or more clocks of the basic clock before setting to the power down mode.
7. After power ON, be sure to reset the device.
8. Afterthepowerdownmodeisreleased(whenPWDWNpinischangedtoa"1"from
a "0"), be sure to reset the device.
9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less
than 30 dB.
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¡ Semiconductor
MSM7603/7603B
EXPLANATION OF TERMS
Attenuating Function :
Echo Attenuation :
This function prevents howling and controls the noise level with
the attenuator for the RIN input and SOUT output. Refer to the
explanation of pins (ATT pin).
If there is talking (input only to RIN) in the path of a rising echo
arises, the echo attenuation refers to the difference in the echo
return loss (canceled amount) when the echo canceler is not used
and when it is used.
Echo attenuation = (SOUT level during through mode operation)
– (SOUT level during echo canceler operation) [dB]
This is the time from when the signal is output from ROUT until it
returns to SIN as an echo.
When using a hands-free phone, for example, the signal output
from the speaker echoes and is input again to the microphone. The
return signal is referred to as acoustic echo.
Echo Delay Time :
Acoustic Echo :
Telephone Line Echo :
Gain Control Function :
This is a signal which is delayed midway in a telephone line and
returns as an echo, due to reasons such as a hybrid impedance
mismatch.
This function prevents howling and controls the sound level by
with a gain controller for the RIN input. Refer to the explanation
of pins (GC pin).
Center Clipping Function : This function forces the SOUT output to a minimum value when
thesignalisbelow–57dBm0. Refertotheexplanationofpins(NLP
pin).
Double talk refers to a state in which the SIN and RIN signals are
input simultaneously. In a double talk state, a signal other than the
echo signal which is to be canceled can be input to the SIN input,
resulting in malfunction.
Double Talk Detection :
Thedoubletalkdetectorpreventssuchmalfunctionofthecanceler.
Thisistheoscillatingstatecausedbytheacousticcouplingbetween
the loud speaker and the microphone during hands-free talking.
Howling not only interferes with talking, but can also cause
malfunction of the echo canceler.
Howling Detection :
The howling detector prevents such malfunction and howling.
When the signal output from ROUT returns to SIN as an echo, ERL
refers to how much loss there is in the signal level during ROUT.
ERL = (ROUT level) – (SIN level of the ROUT signal which returns
as an echo) [dB]
Echo Return Loss (ERL) :
If ERL is positive (ROUT > SIN), acts as an attenuator.
If ERL is negative (ROUT < SIN), acts as an amplifier.
Personal Handyphone System
PHS :
19/20
¡ Semiconductor
PACKAGE DIMENSIONS
SSOP28-P-485-0.65-K
MSM7603/7603B
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
0.39 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
20/20
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