CAV24C64_16 [ONSEMI]
64-Kb I2C CMOS Serial EEPROM;
| 型号： | CAV24C64_16 |
| 厂家： | 
ONSEMI |
| 描述： | 64-Kb I2C CMOS Serial EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总11页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAV24C64
64-Kb I2C CMOS Serial
EEPROM
Description
The CAV24C64 is a 64−Kb CMOS Serial EEPROM device,
internally organized as 8192 words of 8 bits each.
www.onsemi.com
It features a 32−byte page write buffer and supports the Standard
2
(100 kHz) and Fast (400 kHz) I C protocol.
External address pins make it possible to address up to eight
CAV24C64 devices on the same bus.
Features
SOIC−8
W SUFFIX
CASE 751BD
WLCSP−4
C4C SUFFIX
CASE 567JY
TSSOP−8
Y SUFFIX
CASE 948AL
• Automotive Temperature Grade 1 (−40°C to +125°C)
2
• Supports Standard and Fast I C Protocol
• 2.5 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
PIN CONFIGURATIONS (Top Views)
• Hardware Write Protection for Entire Memory
• CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
1
V
A
A
A
CC
0
1
2
WP
SCL
SDA
V
SS
2
• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs
SOIC (W), TSSOP (Y)
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
1
V
V
SS
A1
B1
A2
B2
CC
SCL
SDA
• SOIC, TSSOP 8−lead, and WLCSP 4−Ball Packages
WLCSP (C4C)
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN FUNCTION
V
CC
Pin Name
Function
A , A , A
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
0
1
2
SCL
SDA
SCL
WP
CAV24C64
SDA
A , A , A
2
1
0
WP
V
CC
V
SS
Ground
V
SS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
February, 2016 − Rev. 2
CAV24C64/D
CAV24C64
DEVICE MARKINGS
(TSSOP−8)
(WLCSP−4)
(SOIC−8)
For the location of Pin 1,
please consult the corre-
sponding package drawing.
A
YM
C64F
AYMXXX
G
24C64F
AYMXXX
G
A
Y
M
= Specific Device Code
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
C64F
A
= Specific Device Code
= Assembly Location
Y
M
XXX
G
= Production Year (Last Digit)
= Production Month (1-9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
24C64F = Specific Device Code
A
= Assembly Location
Y
M
XXX
G
= Production Year (Last Digit)
= Production Month (1-9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
°C
Storage Temperature
–65 to +150
–0.5 to +6.5
Voltage on Any Pin with Respect to Ground (Note 1)
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A , A , A
0
1
2
2
and WP should not exceed V + 1 V for more than 20 ns, while voltage on the I C bus pins, SCL and SDA, should not exceed the absolute
CC
maximum ratings, irrespective of V
.
CC
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter
(Note 3)
Min
1,000,000
100
Units
Program/Erase Cycles
Years
N
Endurance
END
T
DR
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V = 5 V, 25°C.
CC
Table 3. D.C. OPERATING CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
Read Current
Test Conditions
Min
Max
Units
mA
mA
mA
mA
V
I
Read, f
Write, f
= 400 kHz
1
2
5
2
CCR
SCL
I
Write Current
= 400 kHz
CCW
SCL
I
SB
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
All I/O Pins at GND or V
T = −40°C to +125°C
A
CC
I
L
Pin at GND or V
CC
V
IL
−0.5
0.7 x V
0.7 x V
0.3 x V
CC
V
IH
A , A , A and WP
V + 0.5
CC
V
0
1
2
CC
CC
SCL and SDA
> 2.5 V, I = 3 mA
5.5
0.4
V
OL
Output Low Voltage
V
CC
V
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
CAV24C64
Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.)
CC
A
Symbol
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
Max
8
Units
pF
C
C
(Note 4)
V
= 0 V, T = 25°C
IN
IN
A
(Note 4)
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
= 0 V, T = 25°C
6
pF
IN
A
I
(Note 5)
< V , V = 5.5 V
130
120
80
2
mA
WP
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 2.5 V
IH
IH
CC
> V
I
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
< V , V = 5.5 V
50
35
25
2
mA
A
IH
CC
< V , V = 3.3 V
IH
CC
< V , V = 2.5 V
IH
IH
CC
> V
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pull−down reverts to a weak current source.
CC
Table 5. A.C. CHARACTERISTICS (V = 2.5 V to 5.5 V, T = −40°C to +125°C, unless otherwise specified.) (Note 6)
CC
A
Standard
Fast
Min
Max
Min
Max
Symbol
Parameter
Units
kHz
ms
F
SCL
Clock Frequency
100
400
t
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
4
4.7
4
0.6
1.3
0.6
0.6
0
HD:STA
t
ms
LOW
t
ms
HIGH
t
4.7
0
ms
SU:STA
HD:DAT
t
ms
t
Data In Setup Time
250
100
ns
SU:DAT
t
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
1000
300
300
300
ns
R
t (Note 6)
ns
F
t
4
0.6
1.3
ms
SU:STO
t
4.7
ms
BUF
t
AA
3.5
0.9
ms
t
100
100
ns
DH
T (Note 6)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
100
100
ns
i
t
0
0
ms
SU:WP
HD:WP
t
WP Hold Time
2.5
2.5
ms
t
Write Cycle Time
5
1
5
1
ms
ms
WR
t
(Notes 7, 8) Power−up to Ready Mode
PU
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t is the delay between the time V is stable and the device is ready to accept commands.
PU
CC
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x V to 0.8 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
≤ 50 ns
0.3 x V , 0.7 x V
CC
CC
0.5 x V
CC
Current Source: I = 3 mA; C = 100 pF
OL
L
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3
CAV24C64
I2C Bus Protocol
The 2-wire I C bus consists of two lines, SCL and SDA,
connected to the V supply via pull-up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
Power-On Reset (POR)
2
Each CAV24C64 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
CC
mode after V exceeds the POR trigger level and will
CC
power down into Reset mode when V drops below the
CC
POR trigger level. This bi-directional POR behavior
protects the device against ‘brown-out’ failure following a
temporary loss of power.
START/STOP Condition
Pin Description
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
Device Addressing
A , A and A : The Address inputs set the device address
0
1
2
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address. For
the CAV24C64, the first four bits of the Slave address are set
that must be matched by the corresponding Slave address
bits. The Address inputs are hard-wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally.
to 1010 (Ah); the next three bits, A , A and A , must match
2
1
0
the logic state of the similarly named input pins. The R/W
bit tells the Slave whether the Master intends to read (1) or
write (0) data (Figure 3).
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally.
Acknowledge
During the 9 clock cycle following every byte sent to the
th
Functional Description
The CAV24C64 supports the Inter-Integrated Circuit (I C)
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
2
Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAV24C64
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those roles.
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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4
CAV24C64
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
Figure 4. Acknowledge Timing
t
t
F
t
R
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
SU:DAT
SU:STO
HD:STA
SDA IN
t
BUF
t
AA
t
DH
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow-up with a new Read or
Write request, rather than wait for the maximum specified
Write time (t ) to elapse. Upon receiving a NoACK
WR
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
operation is in progress (t ), the SDA output is tri-stated
and the Slave does not acknowledge the Master (Figure 7).
WR
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
st
falling edge of SCL immediately preceding the 1 data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAV24C64 is shipped erased, i.e., all bytes are FFh.
written to memory in a single internal Write cycle (t ).
WR
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5
CAV24C64
S
T
A
R
T
BUS ACTIVITY:
MASTER
S
T
O
P
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
a
15
− a
a − a
d − d
7 0
8
7
0
S
P
* * *
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
*a − a are don’t care bits.
15
13
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
BUS
ACTIVITY: S
T
A
S
T
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
SLAVE
ADDRESS
ADDRESS
BYTE
ADDRESS
BYTE
MASTER
SLAVE
R
T
O
P
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
1
8
9
8
d
SCL
SDA
a
a
0
d
7
7
0
t
SU:WP
WP
t
HD:WP
Figure 9. WP Timing
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6
CAV24C64
READ OPERATIONS
Immediate Read
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
N
S
T
A
R
T
O
BUS ACTIVITY:
MASTER
S
A T
C O
K P
SLAVE
ADDRESS
S
P
A
DATA
C
SLAVE
8
BYTE
K
SCL
SDA
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
N
O
BUS ACTIVITY:
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
ADDRESS
BYTE
ADDRESS
BYTE
SLAVE
ADDRESS
SLAVE
ADDRESS
MASTER
S
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SLAVE
DATA
BYTE
Figure 11. Selective Read Sequence
N
O
A
C
K
BUS ACTIVITY:
MASTER
S
T
O
P
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
P
A
C
K
SLAVE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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7
CAV24C64
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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8
CAV24C64
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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9
CAV24C64
PACKAGE DIMENSIONS
WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A
D
B
E
PIN A1
REFERENCE
MILLIMETERS
2X
0.05
0.05
C
C
A3
DIE COAT
DIM
A
MIN
MAX
(OPTIONAL)
−−−
0.35
A2
A1 0.0415 0.0715
2X
TOP VIEW
A2
A3
b
0.255 REF
0.025 REF
0.15
0.16
D
E
e
0.76 BSC
0.76 BSC
0.40 BSC
DETAIL A
DETAIL A
A2
0.05
C
C
A
RECOMMENDED
0.05
SOLDERING FOOTPRINT*
A1
SEATING
PLANE
NOTE 3
C
SIDE VIEW
PACKAGE
A1
OUTLINE
e
4X
b
e
4X
0.40
PITCH
0.05
0.03
C
C
A B
0.16
B
A
0.40
PITCH
DIMENSIONS: MILLIMETERS
1
2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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10
CAV24C64
ORDERING INFORMATION
Specific
Device Marking
†
Device Order Number
Package Type
Lead Finish
Shipping
CAV24C64YE−GT3
C64F
TSSOP−8
NiPdAu
Tape & Reel,
3,000 Units / Reel
CAV24C64YE−G (Note 9)
CAV24C64WE−GT3
C64F
TSSOP−8
NiPdAu
NiPdAu
Tube, 100 Units / Tube
24C64F
SOIC−8, JEDEC
Tape & Reel,
3,000 Units / Reel
CAV24C64C4CTR (Note 9)
A
WLCSP4
SnAgCu
Tape & Reel,
5,000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. Please contact your nearest ON Semiconductor Sales office for availability.
2
ON Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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