CSPEMI204FCTAG [ONSEMI]
带 ESD 保护的 EMI 滤波器;
| 型号： | CSPEMI204FCTAG |
| 厂家： | 
ONSEMI |
| 描述： | 带 ESD 保护的 EMI 滤波器 |
| 文件： | 总7页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSPEMI204
EMI Filter with ESD
Protection
Product Description
The CSPEMI204 is an L−R−C EMI filter array with ESD protection
that integrates two Pi−filters (C−L−R−C) to suppress EMI/RFI Noise.
CSPEMI204 includes ESD protection diodes on all input/output pins,
and provides a very high level of protection for sensitive electronic
components against possible electrostatic discharge (ESD). The ESD
diodes connected to the filter ports safely dissipate ESD strikes of
30 kV, which is beyond the maximum requirement of the
IEC61000−4−2 international standard.
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WLCSP5
FC SUFFIX
CASE 567MA
Features
• Two Channels of EMI Filtering
BLOCK DIAGRAM
•
•
30 kV ESD Protection (IEC 61000−4−2, Contact Discharge)
30 kV ESD Protection (IEC 61000−4−2, Air Discharge)
Filter#2
Filter#1
A3
A1
C3
C1
• Greater than 45 dB of Attenuation at 900 MHz
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
GND B1
GND B1
• Mobile Phones
MARKING DIAGRAM
MAXIMUM RATINGS (T = 25°C)
A
Rating
Symbol
Value
Unit
ATM
ESD Discharge IEC61000−4−2
Contact Discharge
Air Discharge
V
pp
kV
30
30
AT = Specific Device Code
M
= Date Code
RMS Current per Line
I
350
mA
°C
°C
°C
Line
Operating Temperature Range
Storage Temperature Range
T
J
−40 to +125
−55 to +150
260
ORDERING INFORMATION
T
stg
†
Device
Package
Shipping
Lead Solder Temperature
(10 second duration)
T
L
CSPEMI204FCTAG
WLCSP5
(Pb−Free)
5000 / Tape &
Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
August, 2015 − Rev. 0
CSPEMI204/D
CSPEMI204
PACKAGE/PINOUT DIAGRAMS
Table 1. PIN DESCRIPTIONS
Pin
A1
C1
A3
C3
B2
Name
Filter #1
Filter #1
Filter #2
Filter #2
GND
Description
Filter #1 Input/Output
Top View
(Bumps Down View)
Bottom View
(Bumps Up View)
Orientation
Marking
Filter #1 Input/Output
Filter #2 Input/Output
Filter #2 Input/Output
Device Ground
B
A
C
+
+
1
A1
A3
C1
C3
B2
AT
2
3
WLCSP5 Package
Table 2. ELECTRICAL OPERATING CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
V
RWM
Working Voltage
3.0
V
BR
Breakdown Voltage
I = 1 mA; (Note 4)
T
6.0
V
I
Channel Leakage Current
V
IN
= 3.0 V, GND = 0 V
400
3.0
nA
W
LEAK
R
Channel Resistance
CH
(Pins A1 – A3, C1 – C3)
C
Line Capacitance
V
= 0 V, f = 1 MHz
185
250
2.0
315
pF
t
R
f
Cut off Frequency
450 W Source and
MHz
3dB
10 kW Load Termination
f
Cut off Frequency
50 W Termination
25
MHz
dB
3dB
F
atten
Stop Band Attenuation
@ 700 MHz
@ 900 MHz
40
47
V
ESD
In system ESD Withstand Voltage
a) Contact discharge per IEC 61000 4 2 standard, Level 4
(External Pins)
(Notes 1 and 2)
kV
30
30
b) Contact discharge per IEC 61000 4 2 standard, Level 1
(Internal Pins)
V
CL
TLP Clamping Voltage
Forward I = 8 A
9.8
11.5
−9.7
−11.7
V
PP
Forward I = 16 A
PP
Forward I
=
8 A
PP
Forward I
=
16 A
PP
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Standard IEC61000−4−2 with C
= 150 pF, R
= 330, GND grounded.
Discharge
Discharge
2. These measurements performed with no external capacitor.
3. TVS devices are normally selected according to the working peak reverse voltage (V
or continuous peak operating voltage level.
), which should be equal to or greater than the DC
RWM
4. V is measured at pulse test current I .
BR
T
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2
CSPEMI204
PERFORMANCE INFORMATION
Typical Filter Performance
0
0
−10
−20
−30
−40
−10
−20
−30
−40
−50
−60
−70
−80
−50
−60
−90
−100
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 1. Typical Insertion Loss (50 W
Figure 3. Typical Insertion Loss (450 W Source
and 10 kW Load Termination)
Termination)
−80
−85
−90
−95
−100
−105
−110
−115
−120
20
200
2000
20000
FREQUENCY (Hz)
Figure 2. Typical THD+N at 1.8 Vpp
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3
CSPEMI204
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 4. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
CSPEMI204
−25
25
20
15
10
5
−20
−15
−10
−5
0
0
0
2
4
6
8
10
12
14
0
−2
−4
−6
−8
−10
−12
−14
V , VOLTAGE (V)
C
V , VOLTAGE (V)
C
Figure 6. Positive TLP I−V Curve (Preliminary)
Figure 7. Negative TLP I−V Curve (Preliminary)
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns. V is the equivalent voltage
IEC
0
p
r
1
2
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP5, 1.26x0.89
CASE 567MA
ISSUE O
SCALE 4:1
DATE 07 JUL 2015
NOTES:
E
A
B
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
PIN A1
REFERENCE
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
2X
0.10
0.10
C
MILLIMETERS
DIM
A
A1
A2
b
D
E
MIN
−−−
0.18
MAX
0.50
0.22
2X
C
TOP VIEW
SIDE VIEW
0.255 REF
0.235
0.295
1.26 BSC
A2
0.89 BSC
0.50 BSC
0.435 BSC
0.10
C
e
e1
A
GENERIC
MARKING DIAGRAM*
0.05
C
SEATING
PLANE
NOTE 3
C
A1
XXM
e/2
XX = Specific Device Code
e
5X
b
M
= Date Code
e1
0.10
0.05
C
C
A B
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
C
B
A
RECOMMENDED
1
2 3
SOLDERING FOOTPRINT*
BOTTOM VIEW
PACKAGE
OUTLINE
A1
5X
0.27
0.87
PITCH
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON00069G
WLCSP5, 1.26X0.89
PAGE 1 OF 1
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