EMG5DXV5T5G [ONSEMI]
Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network; 双偏置电阻晶体管NPN硅表面贴装晶体管与单片偏置电阻网络型号: | EMG5DXV5T5G |
厂家: | ONSEMI |
描述: | Dual Bias Resistor Transistors NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network |
文件: | 总7页 (文件大小:69K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EMG2DXV5T1,
EMG5DXV5T1
Preferred Devices
Dual Bias Resistor
Transistors
NPN Silicon Surface Mount Transistors
http://onsemi.com
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SOT−553 package which is designed for low power surface mount
applications.
NPN SILICON
BIAS RESISTOR
TRANSISTORS
(3)
(2)
(1)
R1
Features
R1
DT
R2
R2
• Simplifies Circuit Design
• Reduces Board Space
DT
r2
r1
• Reduces Component Count
• Moisture Sensitivity Level: 1
• Available in 8 mm, 7 inch Tape and Reel
• Lead−Free Solder Plating
• Pb−Free Packages are Available
(4)
(5)
SOT−553
CASE 463B
5
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
Value
50
Unit
Vdc
1
V
V
CBO
CEO
50
Vdc
I
100
mAdc
C
MARKING
DIAGRAM
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
5
Total Device Dissipation
P
230 (Note 1)
338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
mW
D
T = 25°C
XX M G
A
°C/W
°C/W
°C/W
°C
G
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
R
q
JA
540 (Note 1)
370 (Note 2)
1
xx = Device Code
xx= UF (EMG5)
UP (EMG2)
Thermal Resistance −
Junction-to-Lead
R
q
JL
264 (Note 1)
287 (Note 2)
M = Date Code
Junction and Storage
Temperature Range
T , T
−55 to +150
J
stg
G
= Pb−Free Package
(Note: Microdot may be in either location)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
ORDERING INFORMATION
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
October, 2005 − Rev. 0
EMG5DXV5/D
EMG2DXV5T1, EMG5DXV5T1
DEVICE MARKING AND RESISTOR VALUES
Device
Package
SOT−553
SOT−553
Marking R1 (K)
R2 (K)
47
EMG2DXV5T1
EMG5DXV5T1
UP
UF
47
10
47
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS (Q1 & Q2)
Collector-Base Cutoff Current (V = 50 V, I = 0)
I
I
−
−
−
−
100
500
nAdc
nAdc
mAdc
CB
E
CBO
CEO
Collector-Emitter Cutoff Current (V = 50 V, I = 0)
CE
B
Emitter-Base Cutoff Current (V = 6.0 V, I = 0)EMG2DXV5T1
I
EBO
−
−
−
−
0.1
0.2
EB
C
EMG5DXV5T1
Collector-Base Breakdown Voltage (I = 10 mA, I = 0)
V
V
50
50
−
−
−
−
Vdc
Vdc
C
E
(BR)CBO
(BR)CEO
Collector-Emitter Breakdown Voltage (Note 3)
(I = 2.0 mA, I = 0)
C
B
ON CHARACTERISTICS (Q1 & Q2) (Note 3)
DC Current Gain (V = 10 V, I = 5.0 mA)
EMG2DXV5T1
EMG5DXV5T1
h
FE
80
80
140
140
−
−
CE
C
Collector-Emitter Saturation Voltage (IC = 10 mA, I = 0.3 mA)
V
−
−
0.25
Vdc
Vdc
B
CE(sat)
Output Voltage (on)
V
OL
(V = 5.0 V, V = 3.5 V, R = 1.0 kW)
EMG2DXV5T1
EMG5DXV5T1
−
−
−
−
0.2
0.2
CC
B
L
(V = 5.0 V, V = 2.5 V, R = 1.0 kW)
CC
B
L
Output Voltage (off) (V = 5.0 V, V = 0.5 V, R = 1.0 kW)
V
4.9
−
−
Vdc
CC
B
L
OH
Input Resistor
EMG2DXV5T1
EMG5DXV5T1
R
1
32.9
7.0
47
10
61.1
13
kW
Resistor Ratio
EMG2DXV5T1
EMG5DXV5T1
R /R
1
0.8
0.17
1.0
0.21
1.2
0.25
2
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%
350
300
250
200
150
100
R
q
JA
= 370°C/W
50
0
−50
0
50
100
150
T , AMBIENT TEMPERATURE (°C)
A
Figure 1. Derating Curve
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2
EMG2DXV5T1, EMG5DXV5T1
TYPICAL ELECTRICAL CHARACTERISTICS — EMG2DXV5T1
10
1
1000
V
= 10 V
CE
I /I = 10
C B
T ꢀ=ꢀ75°C
A
25°C
−25°C
25°C
75°C
100
T ꢀ=ꢀ−25°C
A
0.1
0.01
10
0
20
40
50
1
10
100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 2. VCE(sat) versus IC
Figure 3. DC Current Gain
1
100
10
1
25°C
f = 1 MHz
I = 0 V
75°C
E
T ꢀ=ꢀ−25°C
A
0.8
T = 25°C
A
0.6
0.4
0.1
0.01
0.2
0
V
= 5 V
O
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
100
V
= 0.2 V
O
T ꢀ=ꢀ−25°C
A
25°C
75°C
10
1
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage versus Output Current
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3
EMG2DXV5T1, EMG5DXV5T1
TYPICAL ELECTRICAL CHARACTERISTICS − EMG5DXV5T1
1
300
T ꢀ=ꢀ−25°C
A
I /I = 10
C B
T ꢀ=ꢀ75°C
A
V
= 10
CE
250
200
150
100
25°C
75°C
25°C
0.1
−25°C
0.01
50
0
0.001
0
20
40
60
80
1
2
4
6
8
10 15 20 40 50 60 70 80 90 100
I , COLLECTOR CURRENT (mA)
C
I , COLLECTOR CURRENT (mA)
C
Figure 7. VCE(sat) versus IC
Figure 8. DC Current Gain
4
3.5
3
100
10
1
75°C
25°C
f = 1 MHz
l = 0 V
E
T = 25°C
A
2.5
T ꢀ=ꢀ−25°C
A
2
1.5
1
0.5
0
V
= 5 V
O
0
2
4
6
8
10 15 20 25 30 35 40 45 50
0
2
4
6
8
10
V , REVERSE BIAS VOLTAGE (VOLTS)
R
V , INPUT VOLTAGE (VOLTS)
in
Figure 9. Output Capacitance
Figure 10. Output Current versus Input Voltage
10
T ꢀ=ꢀ−25°C
A
V = 0.2 V
O
25°C
75°C
1
0.1
0
10
20
30
40
50
I , COLLECTOR CURRENT (mA)
C
Figure 11. Input Voltage versus Output Current
http://onsemi.com
4
EMG2DXV5T1, EMG5DXV5T1
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
ISOLATED
LOAD
FROM mP OR
OTHER LOGIC
Figure 12. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
+12 V
V
CC
OUT
IN
LOAD
Figure 13. Open Collector Inverter:
Inverts the Input Signal
Figure 14. Inexpensive, Unregulated Current Source
http://onsemi.com
5
EMG2DXV5T1, EMG5DXV5T1
DEVICE ORDERING INFORMATION
†
Device
EMG2DXV5T1
Package
Shipping
SOT−553
4000 / Tape & Reel
4000 / Tape & Reel
EMG2DXV5T1G
SOT−553
(Pb−Free)
EMG2DXV5T5
SOT−553
8000 / Tape & Reel
8000 / Tape & Reel
EMG2DXV5T5G
SOT−553
(Pb−Free)
EMG5DXV5T1
SOT−553
4000 / Tape & Reel
4000 / Tape & Reel
EMG5DXV5T1G
SOT−553
(Pb−Free)
EMG5DXV5T5
SOT−553
8000 / Tape & Reel
8000 / Tape & Reel
EMG5DXV5T5G
SOT−553
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
EMG2DXV5T1, EMG5DXV5T1
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
5−LEAD PACKAGE
CASE 463B−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
D
A
−X−
L
5
4
3
E
−Y−
MILLIMETERS
INCHES
NOM
0.022
0.009
0.005
H
E
DIM
A
b
c
D
E
MIN
0.50
0.17
0.08
1.50
1.10
NOM
0.55
0.22
0.13
1.60
MAX
MIN
MAX
0.024
0.011
0.007
0.067
0.051
1
2
0.60
0.27
0.18
1.70
1.30
0.020
0.007
0.003
0.059
0.043
b 5 PL
c
0.063
0.047
e
1.20
M
0.08 (0.003)
X Y
e
L
0.50 BSC
0.20
1.60
0.020 BSC
0.008
0.10
1.50
0.30
1.70
0.004
0.059
0.012
0.067
H
0.063
E
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.0
0.0394
1.35
0.0531
0.5
0.5
0.0197 0.0197
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
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EMG5DXV5/D
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