ESD7272LT1G [ONSEMI]
ESD 保护二极管，低电容，双沟道;
| 型号： | ESD7272LT1G |
| 厂家： | 
ONSEMI |
| 描述： | ESD 保护二极管，低电容，双沟道 二极管 |
| 文件： | 总8页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESD7272
ESD Protection Diodes, Low
Capacitance, Dual Channel
The ESD7272 is designed to protect various IOs and data lines from
ESD. The low capacitance and low ESD clamping voltage combined
with a high standoff voltage makes this device an ideal solution for
protecting various types of ICs without causing signal degradation.
The small, cost efficient SOT−23 package allows for easy PCB layout
and BOM reduction on multiple pin modules.
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MARKING
DIAGRAM
Features
• Low Capacitance: < 3.0 pF
• Protection for the Following IEC & ISO Standards:
♦ IEC 61000−4−2 (Level 4)
♦ ISO 10605
SOT−23
CASE 318
27L MG
G
1
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
27L
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONFIGURATIONS
AND SCHEMATICS
Pin 1
Pin 2
Typical Applications
• Sensor Lines
• PWM Inputs/Outputs
• General I/Os
• Automotive
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Symbol
Value
Unit
Pin 3
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 330 pF / 330 W Contact
ISO 10605 330 pF / 2 kW Contact
ISO 10605 150 pF / 2 kW Contact
ESD
15
15
12
25
30
kV
=
Operating Junction Temperature Range
Storage Temperature Range
T
−55 to +175
−55 to +175
260
°C
°C
°C
J(max)
T
stg
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
April, 2019 − Rev. 0
ESD7272/D
ESD7272
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Parameter
Symbol
Condition
Min
Typ
Max
24
Unit
V
Reverse Working Voltage
Breakdown Voltage
V
RWM
Any I/O to GND
I = 1 mA, Any I/O to GND
V
BR
27
29
6.0
0.2
38
36
V
T
Forward Voltage
V
F
I = 100 mA, GND to Any I/O
2.0
V
T
Reverse Leakage Current
Clamping Voltage
I
R
V
RWM
= 24 V, Any I/O to GND
1000
40
nA
V
V
C
V
C
V
C
I
PP
= 1 A, Any I/O to GND (8/20 ms pulse)
Clamping Voltage (Note 1)
IEC61000−4−2, 8kV Contact
See Figures 3 & 4
Clamping Voltage TLP
(Note 2)
I
PP
I
PP
I
PP
I
PP
= 8 A
38
41
−8.0
−10.5
V
V
V
V
= 16 A
= −8 A
= −16 A
Junction Capacitance
C
V
R
= 0 V, f = 1 MHz between Any I/O and GND
1.3
2.0
pF
J
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For text procedures see Application Note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z = 50 W, t = 100 ns, t = 4 ns, averaging window; t = 30 ns to t = 60 ns.
0
p
r
1
2
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.E−02
1.E−03
1.E−04
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
IO−GND
0.2
0
1.E−11
1.E−12
−6 −2
2
6
10 14 18 22 26
V (V)
30 34
0
5
10
15
20
25
V
Bias
(V)
Figure 1. IV Characteristics
Figure 2. CV Characteristics
160
150
140
130
120
110
100
90
10
0
−10
−20
−30
−40
−50
−60
80
−70
70
−80
60
−90
50
−100
−110
−120
−130
−140
−150
−160
40
30
20
10
0
−10
−20
0
20
40
60
80
100
120 140
−20
0
20
40
60
80
100
120 140
TIME (ns)
TIME (ns)
Figure 3. IEC61000−2−4 +8 kV Contact
Figure 4. IEC61000−2−4 −8 kV Contact
Clamping Voltage
Clamping Voltage
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2
ESD7272
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
First Peak
Current
(A)
100%
90%
Test Volt-
age (kV)
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
Device
Under
Test
Oscilloscope
ESD Gun
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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3
ESD7272
20
18
16
14
12
10
8
10
10
8
−20
−18
−16
−14
−12
−10
−8
8
6
6
4
4
6
−6
4
2
−4
2
2
−2
0
0
0
0
0
45
0
45
5
10
15
20
25
30
35
40
5
10
15
20
25
30
35
40
VOLTAGE (V)
VOLTAGE (V)
Figure 7. Positive TLP IV Curve
Figure 8. Negative TLP IV Curve
NOTE: TLP parameter: Z = 50 W, t = 100 ns, t = 300 ps, averaging window: t = 30 ns to t = 60 ns.
0
p
r
1
2
50 W Coax
Cable
Transmission Line Pulse (TLP) Measurement
L
Attenuator
S
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
÷
50 W Coax
Cable
I
M
V
M
10 MW
DUT
V
C
Oscilloscope
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD7272
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
ESD7272LT1G
SOT−23
(Pb−Free)
27L
3000 / Tape & Reel
SZESD7272LT1G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
SCALE 4:1
GENERIC
MARKING DIAGRAM*
XXXMG
G
1
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318
ISSUE AT
DATE 01 MAR 2023
STYLE 1 THRU 5:
CANCELLED
STYLE 6:
STYLE 7:
PIN 1. EMITTER
2. BASE
STYLE 8:
PIN 1. BASE
PIN 1. ANODE
2. EMITTER
3. COLLECTOR
2. NO CONNECTION
3. CATHODE
3. COLLECTOR
STYLE 9:
PIN 1. ANODE
2. ANODE
STYLE 10:
STYLE 11:
PIN 1. ANODE
2. CATHODE
STYLE 12:
STYLE 13:
PIN 1. SOURCE
2. DRAIN
STYLE 14:
PIN 1. CATHODE
2. GATE
PIN 1. DRAIN
2. SOURCE
3. GATE
PIN 1. CATHODE
2. CATHODE
3. ANODE
3. CATHODE
3. CATHODE−ANODE
3. GATE
3. ANODE
STYLE 15:
STYLE 16:
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
STYLE 18:
STYLE 19:
STYLE 20:
PIN 1. CATHODE
2. ANODE
PIN 1. GATE
2. CATHODE
3. ANODE
PIN 1. ANODE
2. CATHODE
3. CATHODE
PIN 1. NO CONNECTION PIN 1. CATHODE
2. CATHODE
3. ANODE
2. ANODE
3. CATHODE−ANODE
3. CATHODE
3. GATE
STYLE 21:
STYLE 22:
STYLE 23:
PIN 1. ANODE
2. ANODE
STYLE 24:
STYLE 25:
STYLE 26:
PIN 1. GATE
2. SOURCE
3. DRAIN
PIN 1. RETURN
2. OUTPUT
3. INPUT
PIN 1. GATE
2. DRAIN
PIN 1. ANODE
2. CATHODE
3. GATE
PIN 1. CATHODE
2. ANODE
3. SOURCE
3. NO CONNECTION
3. CATHODE
STYLE 27:
STYLE 28:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
PIN 1. ANODE
2. ANODE
3. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42226B
SOT−23 (TO−236)
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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