ESDR0502BT1G [ONSEMI]
Transient Voltage Suppressor ESD Protection Diodes with Ultra−Low Capacitance; 瞬态电压抑制器ESD保护二极管具有超低电容
| 型号： | ESDR0502BT1G |
| 厂家： | 
ONSEMI |
| 描述： | Transient Voltage Suppressor ESD Protection Diodes with Ultra−Low Capacitance |
| 文件： | 总4页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDR0502B
Transient Voltage Suppressor
ESD Protection Diodes with Ultra−Low
Capacitance
The ESDR0502B is designed to protect voltage sensitive
components from damage due to ESD in applications that require ultra
low capacitance to preserve signal integrity. Excellent clamping
capability, low leakage and fast response time are combined with an
ultra low diode capacitance of 0.5 pF to provide best in class
protection from IC damage due to ESD. The small SC−75 package is
ideal for designs where board space is at a premium. The ESDR0502B
can be used to protect two uni−directional lines or one bi−directional
line. When used to protect one bi−directional line, the effective
capacitance is 0.25 pF. Because of its low capacitance, it is well suited
for protecting high frequency signal lines such as USB2.0 high speed
and antenna line applications.
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1
PIN 1. CATHODE
3
2. CATHODE
3. ANODE
2
MARKING
DIAGRAM
Specification Features:
3
• Low Capacitance 0.5 pF Typical
• Low Clamping Voltage
SC−75
CASE 463
STYLE 4
AD M G
G
2
1
• Small Body Outline Dimensions:
0.063” x 0.063” (1.60 mm x 1.60 mm)
• Low Body Height: 0.031″ (0.8 mm)
• Stand−off Voltage: 5 V
1
AD
M
G
= Device Code
= Date Code*
= Pb−Free Package
• Low Leakage
• Response Time is Typically < 1.0 ns
• IEC61000−4−2 Level 4 ESD Protection
• This is a Pb−Free Device
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
ORDERING INFORMATION
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
†
Device
ESDR0502BT1G
Package
Shipping
SC−75
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Peak Surge Power
Symbol
Value
8.0
Unit
kV
Contact
(8 x 20 ms)
(8 x 20 ms)
P
I
20
W
pk
Peak Surge Current
2.0
A
DEVICE MARKING INFORMATION
pp
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
Total Power Dissipation on FR−5 Board
P
D
150
mW
(Note 1) @ T = 25°C
A
Storage Temperature Range
Junction Temperature Range
T
−55 to +150
−55 to +150
260
°C
°C
°C
stg
T
J
Lead Solder Temperature − Maximum
(10 Second Duration)
T
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010 − Rev. 0
ESDR0502B/D
ESDR0502B
ELECTRICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
A
I
Symbol
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
I
F
I
PP
V
C
PP
V
RWM
Working Peak Reverse Voltage
V
C
V
V
BR RWM
I
Maximum Reverse Leakage Current @ V
V
R
RWM
I
V
F
R
T
I
V
BR
Breakdown Voltage @ I
Test Current
T
I
T
I
F
Forward Current
I
PP
V
F
Forward Voltage @ I
F
P
Peak Power Dissipation
Capacitance @ V = 0 and f = 1.0 MHz
pk
Uni−Directional TVS
C
R
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted, V = 1.1 V Max. @ I = 10 mA for all types)
A
F
F
V
(V)
C (pF),
uni−directional
(Note 3)
C (pF),
bi−directional
(Note 4)
V (V)
C
BR
V
I
(mA)
@ I
@ I = 1 A
RWM
(V)
R
T
PP
@ V
(Note 2)
(Note 5)
I
T
V
C
RWM
Per
IEC61000−
4−2
Device
Max
Max
1.0
Min
mA
Typ
Max
Typ
Max
Max
(Note 6)
Marking
Device
ESDR0502B
AD
5.0
5.8
1.0
0.5
0.9
0.25
0.45
15
Figures 1
and 2
2. V is measured with a pulse test current I at an ambient temperature of 25°C.
BR
T
3. Uni−directional capacitance at f = 1 MHz, V = 0 V, T = 25°C (pin1 to pin 3; pin 2 to pin 3).
R
A
4. Bi−directional capacitance at f = 1 MHz, V = 0 V, T = 25°C (pin1 to pin 2).
R
A
5. Surge current waveform per Figure 5.
6. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 2. ESD Clamping Voltage Screenshot
Figure 1. ESD Clamping Voltage Screenshot
Negative 8 kV contact per IEC 61000−4−2
Positive 8 kV contact per IEC 61000−4−2
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2
ESDR0502B
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
I
peak
Test
Voltage
(kV)
First Peak
Current
(A)
100%
90%
Current at
30 ns (A)
Current at
60 ns (A)
Level
1
2
3
4
2
4
6
8
7.5
15
4
8
2
4
6
8
I @ 30 ns
22.5
30
12
16
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Oscilloscope
ESD Gun
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
PEAK VALUE I
@ 8 ms
RSM
90
80
70
60
50
40
30
20
PULSE WIDTH (t ) IS DEFINED
P
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I /2 @ 20 ms
RSM
t
P
10
0
0
20
40
t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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3
ESDR0502B
PACKAGE DIMENSIONS
SC−75/SOT−416
CASE 463−01
ISSUE F
−E−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
2
MILLIMETERS
DIM MIN NOM MAX
0.70
A1 0.00
INCHES
NOM MAX
3
MIN
e
−D−
A
0.80
0.05
0.90 0.027 0.031 0.035
0.10 0.000 0.002 0.004
0.30 0.006 0.008 0.012
0.25 0.004 0.006 0.010
1.65 0.059 0.063 0.067
0.90 0.027 0.031 0.035
0.04 BSC
1
b 3 PL
0.20 (0.008)
b
C
D
E
e
0.15
0.10
1.55
0.70
0.20
0.15
1.60
0.80
1.00 BSC
0.15
M
D
H
0.20 (0.008) E
E
L
0.10
1.50
0.20 0.004 0.006 0.008
1.70 0.061 0.063 0.065
H
1.60
E
C
STYLE 4:
A
PIN 1. CATHODE
2. CATHODE
3. ANODE
L
A1
SOLDERING FOOTPRINT*
0.356
0.014
1.803
0.071
0.787
0.031
0.508
0.020
1.000
0.039
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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For additional information, please contact your local
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ESDR0502B/D
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