FAN3268TMX [ONSEMI]
低电压 18V PMOS-NMOS 桥式驱动器;
| 型号： | FAN3268TMX |
| 厂家： | 
ONSEMI |
| 描述： | 低电压 18V PMOS-NMOS 桥式驱动器 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总15页 (文件大小：1065K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 A Low-Voltage
PMOS-NMOS Bridge Driver
FAN3268
Description
The FAN3268 dual 2 A gate driver is optimized to drive a high−side
P−channel MOSFET and a low−side N−channel MOSFET in motor
control applications operating from a voltage rail up to 18 V. The
driver has TTL input thresholds and provides buffer and level
translation functions from logic inputs. Internal circuitry provides an
under−voltage lockout function that prevents the output switching
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devices from operating if the V
supply voltage is below the
DD
operating level. Internal 100 kW resistors bias the non−inverting
output low and the inverting output to V to keep the external
MOSFETs off during startup intervals when logic control signals may
not be present.
SOIC8
CASE 751EB
DD
MARKING DIAGRAM
The FAN3268 driver incorporates MillerDrivet architecture for
the final output stage. This bipolar−MOSFET combination provides
high current during the Miller plateau stage of the MOSFET turn−on /
turn−off process to minimize switching loss, while providing
rail−to−rail voltage swing and reverse current capability.
The FAN3268 has two independent enable pins that default to on if
not connected. If the enable pin for non− inverting channel A is pulled
low, OUTA is forced low; if the enable pin for inverting channel B is
pulled low, OUTB is forced high. If an input is left unconnected,
internal resistors bias the inputs such that the external MOSFETs are
off.
3268T
ALYW
3268T= Specific Device Code
A
L
= Assembly Site
= Wafer Lot Number
YW = Assembly Start Week
Features
• 4.5 V to 18 V Operating Range
• Drives High−Side PMOS and Low−Side NMOS in Motor Control or
Buck Step−Down Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
• Inverting Channel B Biases High−Side PMOS Device Off (with
Internal 100 kW Resistor) when V is below UVLO Threshold
DD
• TTL Input Thresholds
• 2.4 A Sink / 1.6 A Source at V
= 6 V
OUT
• Internal Resistors Turn Driver Off If No Inputs
• MillerDrive Technology
• 8−Lead SOIC Package
• Rated from –40°C to +125°C Ambient
• This is a Pb−Free Device
Applications
• Motor Control with PMOS / NMOS Half−Bridge Configuration
• Buck Converters with High−Side PMOS Device; 100% Duty Cycle
Operation Possible
• Logic−Controlled Load Circuits with High−Side PMOS Switch
Related Resources
AN−6069 − Application Review and Comparative Evaluation of
Low−Side Gate Drivers
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
September, 2020 − Rev. 3
FAN3268/D
FAN3268
+VRAIL (4.5 − 18 V)
FAN3268
ENA ENB
Controller
1
2
3
4
8
7
6
A
MOTOR
GND
VDD
B
5
CBYP
Figure 1. Typical Motor Drive Application
PACKAGE OUTLINE
1
2
3
4
8
7
6
5
ENA
INA
ENB
OUTA
GND
INB
VDD
OUTB
Figure 2. Pin Configuration (Top View)
THERMAL CHARACTERISTICS (Note 1)
Package
Q
JL
(Note 2)
40
Q
JL
(Note 3)
31
Q
JL
(Note 4)
89
Y
JL
(Note 5)
43
Y
JL
(Note 6)
3
Units
8−Pin Small Outline Integrated Circuit (SOIC)
°C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (Q ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
JL
that are typically soldered to a PCB.
3. Theta_JT (Q ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
JT
temperature by a top−side heatsink.
4. Theta_JA (Q ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
JA
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (Y ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
JB
circuit board reference point for the thermal environment defined in Note 4. For the SOIC−8 package, the board reference is defined as the
PCB copper adjacent to pin 6.
6. Psi_JT (Y ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
JT
the top of the package for the thermal environment defined in Note 4.
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2
FAN3268
PIN DEFINITIONS
Pin No. Name
Description
1
8
3
2
4
7
5
ENA
ENB
GND
INA
Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds.
Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds.
Ground. Common ground reference for input and output circuits.
Input to Channel A.
INB
Input to Channel B.
OUTA Gate Drive Output A: Held low unless required input(s) are present and V is above the UVLO threshold.
DD
OUTB Gate Drive Output B (inverted from the input): Held high unless required input is present and V is above UVLO
DD
threshold.
6
VDD
Supply Voltage. Provides power to the IC.
OUTPUT LOGIC
FAN3268 (Channel A)
FAN3268 (Channel B)
ENA
INA
OUTA
ENB
INB
OUTB
0
0 (Note 7)
0
0
0
1
0
0 (Note 7)
1
1
1
0
0
1
0 (Note 7)
1
0
1
0 (Note 7)
1
1 (Note 7)
1 (Note 7)
1 (Note 7)
1 (Note 7)
7. Default input signal if no external connection is made.
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FAN3268
BLOCK DIAGRAM
VDD
VDD
100 kW
100 kW
1
8
ENB
ENA
2
3
INA
OUTA
VDD
7
6
100 kW
100 kW
GND
UVLO
V
DD_OK
100 kW
5
OUTB
4
INB
100 kW
Figure 3. Block Diagram
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
20.0
Unit
V
VDD to GND
−0.3
GND − 0.3
GND − 0.3
GND − 0.3
−
V
V
DD
EN
V
ENA, ENB to GND
INA, INB to GND
OUTA, OUTB to GND
V
V
V
+ 0.3
DD
DD
DD
V
+ 0.3
+ 0.3
V
IN
V
OUT
V
T
Lead Soldering Temperature (10 Seconds)
Junction Temperature
+260
°C
°C
°C
L
T
−55
+150
+150
J
T
STG
Storage Temperature
−65
Symbol
Parameter
Supply Voltage Range
Min
4.5
0
Max
Unit
V
V
18.0
DD
EN
V
Enable Voltage (ENA, ENB)
Input Voltage (INA, INB)
V
DD
V
DD
V
V
IN
0
V
T
A
Operating Ambient Temperature
−40
+125
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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FAN3268
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
SUPPLY
Parameter
Conditions
Min
Typ
Max
Unit
V
Operating Range
Supply Current Inputs / EN Not Connected
4.5
−
18.0
1.20
V
DD
DD
I
−
0.75
mA
FAN3268T UVLO
V
Device Turn−On Voltage
Device Turn−Off Voltage
INA = ENA = V , INB = ENB = 0 V
3.5
3.3
3.9
3.7
4.3
4.1
V
V
ON
DD
V
OFF
INA = ENA = V , INB = ENB = 0 V
DD
INPUT (Note 8)
FAN3268T
V
INx Logic Low Threshold
INx Logic High Threshold
Logic Hysteresis Voltage
0.8
−
1.2
1.6
0.4
−
V
V
V
IL
V
IH
2.0
0.8
V
HYS
0.2
ENABLE
V
Enable Logic Low Threshold
EN from 5 V to 0 V
EN from 0 V to 5 V
0.8
−
1.2
1.6
0.4
100
−
2.0
−
V
V
ENL
ENH
HYS
V
V
Enable Logic High Threshold
Logic Hysteresis Voltage (Note 9)
Enable Pull−up Resistance (Note 9)
−
V
R
−
−
kW
PU
OUTPUT
I
Out Current, Mid−Voltage, Sinking (Note 9)
Out at VDD/2, C
= 0.1 mF, f = 1 kHz
= 0.1 mF, f = 1 kHz
−
−
−
−
−
−
2.4
−1.6
3
−
−
A
A
SINK
LOAD
I
Out Current, Mid−Voltage, Sourcing (Note 9) Out at VDD/2, C
SOURCE
LOAD
I
Out Current, Peak, Sinking (Note 9)
Out Current, Peak, Sourcing (Note 9)
Output Rise Time (Note 10)
C
C
C
C
= 0.1 mF, f = 1 kHz
= 0.1 mF, f = 1 kHz
= 1000 pF
−
A
PK_SINK
LOAD
LOAD
LOAD
LOAD
I
−3
12
9
−
A
PK_SOURCE
t
t
22
17
ns
ns
RISE
FALL
Output Fall Time (Note 10)
= 1000 pF
FAN3268T
t
D1
t
D2
Propagation Delay
Propagation Delay
0 − 5 V , 1 V/ns Slew Rate
7
14
19
25
34
ns
ns
IN
0 − 5 V , 1 V/ns Slew Rate
10
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. EN inputs have TTL thresholds; refer to the ENABLE section.
9. Not tested in production.
10.See the Timing Diagrams of Figure 4 and Figure 5.
TIMING DIAGRAMS
90%
10%
90%
10%
Output
Output
Input
or
Enable
Input
or
Enable
VINH
VINL
VINH
VINL
tD1
tD2
tD2
tD1
tFALL
tFALL
tRISE
tRISE
Figure 4. Non−Inverting
Figure 5. Inverting
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5
FAN3268
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted.)
A
DD
Figure 6. IDD (Static) vs. Supply Voltage (Note 11)
Figure 7. IDD (No−Load) vs. Frequency
Figure 8. IDD (1 nF Load) vs. Frequency
Figure 9. IDD (Static) vs. Temperature (Note 11)
Figure 10. Input Thresholds vs. Supply Voltage
Figure 11. Input Thresholds vs. Temperature
NOTE:
11. For any inverting inputs pulled low, non−inverting inputs pulled high, or outputs driven high, static I increases by the current flowing
DD
through the corresponding pull−up/down resistor shown in the block diagram in Figure 3.
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FAN3268
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted.) (continued)
A
DD
Figure 12. UVLO Threshold vs. Temperature
Figure 13. Propagation Delays vs. Supply Voltage
Figure 14. Propagation Delays vs. Supply Voltage
Figure 15. Propagation Delays vs. Temperature
Figure 16. Propagation Delays vs. Temperature
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FAN3268
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted.) (continued)
A
DD
Figure 17. Fall Time vs. Supply Voltage
Figure 18. Rise Time vs. Supply Voltage
Figure 19. Rise and Fall Times vs. Temperature
Figure 20. Rise/Fall Waveforms with 1 nF Load
Figure 21. Rise/Fall Waveforms with 10 nF Load
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FAN3268
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at T = 25°C and V = 12 V unless otherwise noted.) (continued)
A
DD
Figure 22. Quasi−Static Source Current with VDD = 12 V
Figure 23. Quasi−Static Sink Current with VDD = 12 V
Figure 24. Quasi−Static Source Current with VDD = 8 V
Figure 25. Quasi−Static Sink Current with VDD = 8 V
TEST CIRCUIT
VDD
120 mF
Al. El.
4.7
mF
ceramic
Current Probe
LECROY AP015
IOUT
IN
1 k Hz
0.1 mF
ceramic
CLOAD
VOUT
0.1 mF
Figure 26. Quasi−Static IOUT / VOUT Test Circuit
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FAN3268
APPLICATIONS INFORMATION
VDD
Input Thresholds
The FAN3268 driver has TTL input thresholds and
provides buffer and level translation functions from logic
inputs. The input thresholds meet industry−standard
TTL−logic thresholds, independent of the V voltage, and
DD
there is a hysteresis voltage of approximately 0.4 V. These
levels permit the inputs to be driven from a range of input
logic signal levels for which a voltage over 2 V is considered
logic high. The driving signal for the TTL inputs should
have fast rising and falling edges with a slew rate of 6 V/ms
or faster, so a rise time from 0 to 3.3 V should be 550 ns or
less. With reduced slew rate, circuit noise could cause the
driver input voltage to exceed the hysteresis voltage and
retrigger the driver input, causing erratic operation.
Input
stage
VOUT
Static Supply Current
In the I (static) typical performance characteristics (see
DD
Figure 6), the curve is produced with all inputs / enables
Figure 27. MillerDrive Output Architecture
Under−Voltage Lockout
Internal circuitry provides an under−voltage lockout
function that prevents the output switching devices from
floating (OUT is low) and indicates the lowest static I
DD
current for the tested configuration. For other states,
additional current flows through the 100 kW resistors on the
inputs and outputs shown in the block diagram (see
Figure 3). In these cases, the actual static I current is the
DD
operating if the V supply voltage is below the operating
DD
value obtained from the curves plus this additional current.
level. When V is rising, but below the 3.9 V operational
DD
level, internal 100 kW resistors bias the non−inverting
MillerDrive Gate Drive Technology
output low and the inverting output to V
to keep the
DD
FAN3268 gate drivers incorporate the MillerDrive
architecture shown in Figure 1. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
external MOSFETs off during startup intervals when logic
control signals may not be present. After the part is active,
the supply voltage must drop 0.2 V before the part shuts
down. This hysteresis helps prevent chatter when low V
supply voltages have noise from the power switching.
DD
the current as OUT swings between one and two thirds V
DD
and the MOS devices pull the output to the high or low rail.
The purpose of the MillerDrive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on / turn−off process.
For applications with zero voltage switching during the
MOSFET turn−on or turn−off interval, the driver supplies
high peak current for fast switching even though the Miller
plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched on.
V
Bypass Capacitor Guidelines
DD
To enable this IC to turn a device on quickly, a local
high−frequency bypass capacitor C with low ESR and
ESL should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to
bulk electrolytic capacitance of 10 mF to 47 mF commonly
found on driver and controller bias circuits.
BYP
A typical criterion for choosing the value of C
is to
BYP
keep the ripple voltage on the V supply to ≤5%. This is
DD
often achieved with a value ≥20 times the equivalent load
capacitance C
, defined here as Q
EQV
/V . Ceramic
GATE DD
capacitors of 0.1 mF to 1 mF or larger are common choices,
as are dielectrics, such as X5R and X7R, with good
temperature characteristics and high pulse current
capability.
The output pin slew rate is determined by V voltage and
DD
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
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FAN3268
If circuit noise affects normal operation, the value ofC
BYP
VDD
may be increased to 50 − 100 times the C
or C
may
EQV
BYP
UVLO
Turn−on threshold
be split into two capacitors. One should be a larger value,
based on equivalent load capacitance, and the other a smaller
value, such as 1 − 10 nF mounted closest to the VDD and
GND pins to carry the higher frequency components of the
current pulses. The bypass capacitor must provide the pulsed
current from both of the driver channels and, if the drivers
are switching simultaneously, the combined peak current
INA
sourced from the C
would be twice as large as when a
BYP
single channel is switching.
OUTA
Layout and Connection Guidelines
The FAN3268 gate driver incorporates fast−reacting input
circuits, short propagation delays, and powerful output
stages capable of delivering current peaks over 2 A to
facilitate voltage transition times from under 10ns to over
150 ns. The following layout and connection guidelines are
strongly recommended:
Figure 28. Non−Inverting Startup Waveforms
Figure 29 illustrates startup waveforms for inverting
channel B. At power−up, the driver output for channel B is
• Keep high−current output and power ground paths
separate from logic and enable input signals and signal
ground paths. This is especially critical when dealing with
TTL−level logic thresholds at driver inputs and enable
pins.
tied to V through an internal 100 kW resistor until the
DD
V
DD
voltage reaches the UVLO turn−on threshold, then
OUTB operates out of phase with INB.
• Keep the driver as close to the load as possible to
minimize the length of high−current traces. This reduces
the series inductance to improve high−speed switching,
while reducing the loop area that can radiate EMI to the
driver inputs and surrounding circuitry.
VDD
UVLO
Turn−on threshold
• If the inputs to a channel are not externally connected, the
internal 100 kW resistors indicated on block diagrams
command a low output (channel A) or a high output
(channel B). In noisy environments, it may be necessary
to tie inputs or enables of an unused channel to VDD or
GND using short traces to prevent noise from causing
spurious output switching.
INB
OUTB
• Many high−speed power circuits can be susceptible to
noise injected from their own output or other external
sources, possibly causing output re−triggering. These
effects can be obvious if the circuit is tested in breadboard
or non−optimal circuit layouts with long input, enable, or
output leads. For best results, make connections to all pins
as short and direct as possible.
Figure 29. Inverting Startup Waveforms
Thermal Guidelines
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
• The turn−on and turn−off current paths should be
minimized.
Operational Waveforms
Figure 28 shows startup waveforms for non−inverting
channel A. At power−up, the driver output for channel A
The total power dissipation in a gate driver is the sum of
two components, P
and P
:
GATE
PTOTAL + PGATE ) PDYNAMIC
DYNAMIC
remains low until the V
voltage reaches the UVLO
DD
(eq. 1)
turn−on threshold, then OUTA operates in−phase with INA.
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FAN3268
Gate Driving Loss: The most significant power loss
As an example of a power dissipation calculation,
consider an application driving two MOSFETs with a gate
results from supplying gate current (charge per unit time) to
switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
charge of 60 nC with V = V = 7 V. At a switching
GS
DD
frequency of 500 kHz, the total power dissipation is:
a MOSFET at a specified gate−source voltage, V , with
GS
PGATE + 60 nC 7 V 500 kHz 2 + 0.42 W
(eq. 5)
gate charge, Q , at switching frequency, f , is determined
G
SW
by:
PDYNAMIC + 3 mA 7 V 2 + 0.042 W
PTOTAL + 0.46 W
(eq. 6)
PGATE + QG VGS fSW n
(eq. 2)
(eq. 7)
where n is the number of driver channels in use (1 or 2).
Dynamic Pre−drive / Shoot−through Current: A power
loss resulting from internal current consumption under
dynamic operating conditions, including pin pull−up /
The SOIC−8 has
characterization parameter of Y = 43°C/W. In a system
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
a
junction−to−board thermal
JB
pull−down resistors, can be obtained using the “I
DD
(No−Load) vs. Frequency” graphs in Typical Performance
Characteristics to determine the current I
drawn
DYNAMIC
from V under actual operating conditions:
DD
150°C; with 80% derating, T would be limited to 120°C.
Rearranging Equation 4 determines the board temperature
J
PDYNAMIC + IDYNAMIC VDD n
(eq. 3)
required to maintain the junction temperature below 120°C:
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
TB + TJ * PTOTAL YJB
(eq. 8)
TB + 120°C 0.46 W 43°CńW + 100°C
Y
JB
was determined for a similar thermal design (heat
(eq. 9)
sinking and air flow):
TJ + PTOTAL YJB ) TB
(eq. 4)
where:
T = driver junction temperature
J
Y
JB
= (psi) thermal characterization parameter relating
temperature rise to total power dissipation
T = board temperature in location defined in Note 1 under
B
Thermal Resistance table.
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FAN3268
Table 1. RELATED PRODUCTS
Part
Gate Drive (Note 12)
Input
Number
(Sink/Src)
Threshold
Type
Logic
Single Channel of Dual−Input/Single−Output
Package
FAN3111C Single 1 A
FAN3111E Single 1 A
+1.1 A / −0.9 A
+1.1 A / −0.9 A
CMOS
SOT23−5, MLP6
External
(Note 13)
Single Non−Inverting Channel with External Reference SOT23−5, MLP6
FAN3100C Single 2 A
FAN3100T Single 2 A
FAN3226C Dual 2 A
FAN3226T Dual 2 A
FAN3227C Dual 2 A
FAN3227T Dual 2 A
FAN3228C Dual 2 A
FAN3228T Dual 2 A
FAN3229C Dual 2 A
FAN3229T Dual 2 A
FAN3268T Dual 2 A
+2.5 A / −1.8 A
+2.5 A / −1.8 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
+2.4 A / −1.6 A
CMOS
TTL
Single Channel of Two−Input/One−Output
Single Channel of Two−Input/One−Output
SOT23−5, MLP6
SOT23−5, MLP6
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
CMOS
TTL
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input/One−Output, Pin Config.1
Dual Channels of Two−Input/One−Output, Pin Config.1
Dual Channels of Two−Input/One−Output, Pin Config.2
Dual Channels of Two−Input/One−Output, Pin Config.2
CMOS
TTL
CMOS
TTL
TTL
Non−Inverting Channel (NMOS) and Inverting Channel
(PMOS) + Dual Enables
FAN3223C Dual 4 A
FAN3223T Dual 4 A
FAN3224C Dual 4 A
FAN3224T Dual 4 A
FAN3225C Dual 4 A
FAN3225T Dual 4 A
FAN3121C Single 9 A
FAN3121T Single 9 A
FAN3122T Single 9 A
FAN3122C Single 9 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+4.3 A / −2.8 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
+9.7 A / −7.1 A
CMOS
TTL
Dual Inverting Channels + Dual Enable
Dual Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Non−Inverting Channels + Dual Enable
Dual Channels of Two−Input/One−Output
Dual Channels of Two−Input/One−Output
Single Inverting Channel + Enable
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
SOIC8, MLP8
CMOS
TTL
CMOS
TTL
CMOS
TTL
Single Inverting Channel + Enable
CMOS
TTL
Single Non−Inverting Channel + Enable
Single Non−Inverting Channel + Enable
12.Typical currents with OUT at 6 V and V = 12 V.
DD
13.Thresholds proportional to an externally supplied reference voltage.
ORDERING INFORMATION
†
Device
Logic
Package
Input Threshold
Shipping
FAN3268TMX
Non−Inverting Channel and Inverting
SOIC8
(Pb−Free)
TTL
2500 / Tape & Reel
Channel + Dual Enables
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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