FAN53870UC00X [ONSEMI]
Two Low Input LDOs, Three High PSRR LDOs, Two General Purpose LDOs PMIC;
| 型号： | FAN53870UC00X |
| 厂家： | 
ONSEMI |
| 描述： | Two Low Input LDOs, Three High PSRR LDOs, Two General Purpose LDOs PMIC 集成电源管理电路 |
| 文件： | 总60页 (文件大小：1853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Two Low Input LDOs, Three
High PSRR LDOs, Two
General Purpose LDOs
PMIC
WLCSP20 1.61x1.96x0.432
CASE 567YA
FAN53870, FAN53871
MARKING DIAGRAM
General Description
12KK
XYZ
The FAN53870 family are low Iq PMICs intended for mobile power
application camera modules. The PMIC contains two high power
LDOs which can operate with an input as low as 1.0 V for digital
cores, three LDOs which are designed to have ultra low noise and high
PSRR for sensitive analog/RF circuit loads, and two other general
purpose LDOs which provide excellent overall performance.
The device is available in 20−bump, 0.35 mm pitch, Wafer−Level
Chip−Scale Package (WLCSP).
1
12
KK
X
Y
Z
= Alphanumeric Device Marking
= Lot Run Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
• LDO1 and LDO2:
♦ 1 A and 1.2 A Output Current Capability Device Options
♦ Programmable Output Voltage 0.8 V to 1.5 V in 8 mV Steps
♦ 1.0 V to 2.0 V Input Voltage Range
♦ 1.5% Accuracy
Applications
• LDO3, LDO4 and LDO5:
• Smart Phones
• Wearables
• Smart Watch
• Health Monitoring
• Sensor Drive
• Energy Harvesting
• Utility and Safety Modules
• RF Modules
♦ 300 mA Output Current Capability
♦ Programmable Output Voltage 1.5 V to 3.4 V in 8 mV Steps
♦ 1.9 V to 5.5 V Input Voltage Range
♦ 14 mV (Typ) Noise
• LDO6 and LDO7:
♦ 300 mA Output Current Capability
♦ Programmable Output Voltage 1.5 V to 3.4 V in 8 mV Steps
♦ 1.9 V to 5.5 V Input Voltage Range
• Operation Guaranteed with Battery Voltage Down to 2.5 V
• Soft−Start function (SS) to Limit Inrush Current
• Programmable Power Start−Up/Down Sequencing
• Current Limit to Protect Against Short Circuit
2
• I C Protection Fault (UVLO, OCP, UVP and OTP) Registers
• Thermal and Under Voltage Global Shutdown Protection
2
• I C Serial Control to Program Output Voltage and Features
• Small Footprint: 20−Bump WLCSP, 1.61 x 1.96 mm / 0.35 mm pitch
• Pb−Free Devices
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
April, 2023 − Rev. 10
FAN53870/D
FAN53870, FAN53871
TABLE OF CONTENTS
Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Product Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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2
FAN53870, FAN53871
ORDERING INFORMATION
I/O
Logic
LDO1,2
LDO1,2 LDO3,4 LDO5 LDO6,7 Interrupt
2
I C
I
VOUT
VOUT
VOUT
VOUT
Pin
Temperature
Range
OUT
†
Shipping
Part Number
Marking Level* Address Capability** Default Default Default Default Polarity
Package
FAN53870UC00X
FAN53870UC12X
FAN53871UC00X
FAN53871UC12X
LX
YF
LY
1.8 V
7’h35
7’h20
7’h20
7’h20
1.0 A
1.2 A
1.0 A
1.2 A
1.05 V
2.8 V
1.8 V
2.8 V
Active
High:
INT
−40°C to
+85°C
20−Bump 3000 / Tape
WLCSP
& Reel
(Pb−Free)
1.2 V
Active
Low:
INT_B
YG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*RESET_B, SDA, SCL (open drain type pins).
** See Maximum Ratings table for Maximum Current on a Single Pin
APPLICATION CIRCUIT
Application Circuit Diagram
VSYS
VSYS
REF
CSYS
CREF
AGND
VLDO1
INT/INT_B
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
CLDO1
VLDO2
RESET_B
SCL
CLDO2
VLDO3
SDA
VIN12
CLDO3
FAN5387x
VIN12
VIN34
VIN5
VLDO4
VIN34
CVIN12
CLDO4
VIN5
CVIN34
VLDO5
VIN6
CVIN6
CLDO5
VLDO6
CVIN5
VIN6
VIN7
CVIN7
VIN7
CLDO6
VLDO7
CLDO7
AGND
Figure 1. Application Circuit Diagram
Application Circuit Components
Table 1. RECOMMENDED EXTERNAL COMPONENTS
Component
, C
Manufacturer
Part Number
Value
Case Size
Voltage Rating
C
, C
,
,
Murata
GRM033R61A105ME15
1.0 mF
0201/0603 (0.6 mm x 0.3 mm)
10 V
VIN12
VIN34
VIN5
, C
VIN7 SYS
C
, C
VIN6
C
, C
LDO6
, C
LDO7
Murata
GRM033R60J225ME47D
2.2 mF
0201/0603 (0.6 mm x 0.3 mm)
6.3 V
LDO3
LDO4
LDO5
C
, C
C
, C
Taiyo Yuden
Murata
JMK105CBJ106MV−F
10 mF
0402/1005 (1.0 mm x 0.5 mm)
0201/0603 (0.6 mm x 0.3 mm)
6.3 V
6.3 V
LDO1
LDO2
C
GRM033R60J104KE19J
0.1 mF
REF
Table 2. RECOMMENDED ALTERNATIVE COMPONENTS
Component
Manufacturer
Part Number
Value
Case Size
Voltage Rating
C
, C
LDO6
, C
,
Semco
CLO3A225MQ3CRNC
2.2 mF
0201 (0.6 mm x 0.3 mm)
6.3 V
LDO3
LDO4
LDO5
, C
LDO7
C
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FAN53870, FAN53871
PRODUCT PIN ASSIGNMENTS
Pin Configuration
VIN6
A1
VIN7
A2
LDO7
A3
LDO2
A4
VIN12
A5
A5
B5
C5
D5
A1
B1
C1
D1
A4
B4
C4
D4
A3
B3
C3
D3
A2
B2
C2
D2
LDO6
B1
INT/INT_B
B2
SDA
B3
SCL
B4
LDO1
B5
LDO4
C1
AGND
C2
AGND
C3
RESET_B
C4
VREF
C5
LDO3
D1
VIN34
D2
VSYS
D3
VIN5
D4
LDO5
D5
Top View
Bottom View
Figure 2. Pin Configuration
Pin Descriptions
PIN DEFINITIONS
Pin
A1
A2
A3
A4
A5
B1
B2
Pin Name
VIN6
Description
Input power pin for LDO6. Place C
Input power pin for LDO7. Place C
as close to this pin as possible.
as close to this pin as possible.
VIN6
VIN7
VIN7
LDO7
LDO2
VIN12
LDO6
INT
This is the output pin for LDO7. Place C
as close to this pin as possible.
as close to this pin as possible.
LDO7
LDO2
This is the output pin for LDO2 Place C
Input power pin for LDO1 and LDO2. Place C
as close to this pin as possible.
VIN12
This is the output pin for LDO6. Place C
as close to this pin as possible.
LDO6
Fault interrupt pin is a push−pull, active high configuration and pulls high to indicate an interrupt event has
occurred. This pin returns to low when all I C interrupt bits are equal to 0.
2
INT_B
Fault interrupt pin is an open−drain configuration and pulls low to indicate an interrupt event has occurred. This
2
pin returns to Hi−Z when all I C interrupt bits equal 0. An external pull−up resistor is required.
2
B3
B4
B5
C1
C2
C3
C4
SDA
SCL
I C Data pin. Node should be tied high through a pull up resistor.
2
I C Clock pin. Node should be tied high through a pull up resistor.
LDO1
LDO4
AGND
AGND
This is the output pin for LDO1. Place C
This is the output pin for LDO4. Place C
as close to this pin as possible.
as close to this pin as possible.
LDO1
LDO4
Digital/Analog ground connection. Tie to analog ground plane.
Digital/Analog ground connection. Tie to analog ground plane.
RESET_B RESET_B pin is used to enable basic circuits necessary for controlling the PMIC. The RESET_B pin has an
2
internal 4 MW (typ) pull−down and should not be left floating. When RESET_B pin is low, I C is not accessible.
C5
D1
D2
D3
VREF
LDO3
VIN34
VSYS
Reference bypass pin. If used, connect a 100 nF capacitor between this pin and analog ground.
This is the output pin for LDO3. Place C as close to this pin as possible.
LDO3
This is the input power pin for LDO3 and LDO4. Place C
as close to this pin as possible.
VIN34
System power pin. Route trace from system to this pin. Connect the C
as possible.
capacitor as close to this pin
SYS
D4
D5
VIN5
Input power pin for LDO5. Place C
as close to this pin as possible.
VIN5
LDO5
This is the output pin for LDO5. Place C
as close to this pin as possible.
LDO5
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FAN53870, FAN53871
PRODUCT BLOCK DIAGRAM
Block Diagram
VIN12
LDO1
LDO2
uvlo12
Vin12_ref
Ldo2_uvp
Ldo1_ocp
Ldo1_ref
Ldo1_ilim
LDO1 Control
LDO2 Control
Ldo2_uvp
Ldo2_ocp
Ldo2_ref
Ldo2_ilim
VIN34
LDO3
LDO4
uvlo34
Vin37_ref
Ldo3_uvp
Ldo3_ocp
Ldo3_ref
Ldo3_ilim
LDO3 Control
LDO4 Control
Ldo4_uvp
Ldo4_ref
Ldo4_ocp
Ldo4_ilim
FAN5387x
VIN5
VIN6
VIN7
LDO5
LDO6
LDO7
Ldo5_uvp
Ldo5_ref
Ldo5_ocp
uvlo5
Vin37_ref
LDO5 Control
LDO6 Control
LDO7 Control
Ldo5_ilim
Ldo6_ref
Ldo6_ocp
Ldo6_uvp
uvlo6
uvlo7
Ldo6_ilim
Vin37_ref
Vin37_ref
Ldo7_uvp
Ldo7_ref
Ldo7_ocp
Ldo7_ilim
Ldo1_ocp
Ldo2_ocp
Ldo3_ocp
Ldo4_ocp
Ldo5_ocp
Ldo6_ocp
Ldo7_ocp
uvlo12
Digital
Core Analog
Block
uvlo34
uvlo5
uvlo6
uvlo7
uvlos
VSYS
REF
Control
uvlos
Vsys_ref
Ldo1_uvp
Ldo2_uvp
Ldo3_uvp
Ldo5_uvp
Ldo6_uvp
Ldo7_uvp
Ldo4_uvp
RESET_ B
Thermal
Protection
Reference
I2C
SCL
SDA
INT/INT_B
AGND
AGND
Figure 3. Block Diagram
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FAN53870, FAN53871
MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.3
−0.3
−0.3
Typ
−
Max
Unit
V
V
System Input Voltage
6
6
6
SYS
IN12
V
Low Voltage LDO Input
Mid Voltage LDO Input
−
V
V
, V
,
−
V
IN34
IN6
IN5
IN7
V
, V
V
SDA, SCL and RESET_B Pins
INT Pin
− 0.3
− 0.3
− 0.3
− 0.3
−
−
−
6
V
V
CTRL
V
V
SYS
INT
INT_B Pin
−
6
V
Power Output Pins
Maximum current on a single pin
−
6
1.5
V
A
LDO1−7
Ipin_max
ESD
−
Electrostatic Discharge Protection Level
Electrostatic Discharge Protection Level
Junction Temperature
Human Body Model
−
2.0
1500
−
−
kV
V
ESD
Charged Device Model
−
−
T
J
−40
−40
−
+150
+150
+260
°C
°C
°C
T
Storage Temp
−
STG
T
L
Soldering Temp (10 Seconds)
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (Junction−to−ambient thermal resistance is a function of application and board layout. This data is
measured with two−layer 2s2p boards with vias in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed
junction temperature T
at a given ambient temperature T .)
J(max)
A
Symbol
Characteristic
Conditions
Min
Typ
Max
Unit
Q
Junction −to−Ambient Thermal Resistance
−
40.4
−
°C/W
JA
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
Supply Voltage Range
Power Dissipation
Conditions
Min
2.5
1.0
1.9
1.9
1.9
1.9
−
Typ
−
Max
5.5
2.0
5.5
5.5
5.5
5.5
0.99
85
Unit
V
V
V
V
V
V
V
V
SYS
IN12
IN34
SYS
IN12
IN34
IN5
V
V
−
V
−
V
V
−
V
IN5
IN6
IN7
V
−
V
IN6
V
−
V
IN7
P
D
PD = (125°C − 85°C) / 40.4°C/W = 0.99 W
−
W
°C
°C
T
A
Operating Ambient Temperature
Junction Temperature
−40
−40
−
T
J
−
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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FAN53870, FAN53871
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V;
SYS
OUT1/2
V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V & ≥ V
+ 300 mV, T = −40°C to 125°C, unless
IN12
LDO1/2
IN34/5/6/7
LDO3/4/5/6/7 J
otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
= 1.3 V, V
= V
= V
= 3.8 V, V = 2.05 V,
IN5
A
SYS
IN12
IN34
IN6
IN7
V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V = 2.8 V.)
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
POWER SUPPLY UVLO
Parameter
Conditions
Min
Typ
Max
Unit
V
Under−Voltage Lockout Threshold
Under−Voltage Lockout Threshold
Under−Voltage Lockout Threshold
Under−Voltage Lockout Threshold
Under−Voltage Lockout Threshold
Under−Voltage Lockout Threshold
Rising V
Falling V
2.30
2.20
0.90
0.80
1.80
1.70
2.35
2.25
0.95
0.85
1.85
1.75
2.40
2.30
1.00
0.92
1.90
1.80
V
V
V
V
V
V
SYS
UVLO_RS
SYS
V
SYS
UVLO_FL
SYS
V
Rising V
Falling V
Rising V
Falling V
VIN12
UVLO_RS
IN12
V
VIN12
UVLO_FL
IN12
V
VIN_H
UVLO_RS
IN34/5/6/7
IN34/5/6/7
V
VIN_H
UVLO_FL
LDO1/2
QUIESCENT CURRENT
IQ Quiescent Current, No Load
L12
I
= 0 A, total V
and V current
IN12
−
72
85
mA
OUT
SYS
when either LDO1 or LDO2 is enabled and all
other LDOs are disabled.
OUTPUT VOLTAGE
VO
LDO1/2 Output Voltage Accuracy
I
= 5 mA and 500 mA, V = 2.0 V,
IN12
−1.5
−
−
+1.5
200
%
L12_ACC
OUT
V
= 3.8 V, V
= 0.8 V to 1.5 V
SYS
OUT
V
LDO1/2 Dropout Voltage
V
= V
− 50 mV,
OUT_TARGET
−
mV
L1/2_DO
OUT
OUT_TARGET
I
= 800 mA, V
= 1.05 V,
OUT
V
= 2.65 V
SYS
CURRENT LIMIT
I
Current Limit (FAN53870UC00X,
FAN53871UC00X)
V
+ 300 mV ≤ V
and
700
750
925
1100
1250
1500
1100
1350
1450
1800
mA
mA
LIM_L12
OUT
IN12
V
IN12
V
SYS
= 1.0 V to 2.0 V,
= 2.5 V to 4.5 V and V
≥ V
+ 1.6 V
SYS
OUT
Current Limit (FAN53870UC12X,
FAN53871UC12X)
I
Current Limit (FAN53870UC00X,
FAN53871UC00X)
1050
1200
LIM_H12
Current Limit (FAN53870UC12X,
FAN53871UC12X)
OUTPUT PROTECTION
UVP
LDO1/2 Falling UVP Output Thresh-
old
V
= 3.8 V, V
= 3.8 V, V
= 1.05 V
86
91
80
90
95
94
% of
L12_FL
SYS
OUT
V_Target
UVP
LDO1/2 Rising UVP Output Thresh-
old
V
SYS
= 1.05 V
98.5
120
% of
V_Target
L1/2_RS
OUT
R
Output Discharge Resistance
100
W
L1/2_DCHG
LDO3/4
QUIESCENT CURRENT
IQ LDO3/4 Quiescent Current, No Load
L34
I
= 0 A, total V
and V current when
IN34
−
63
75
mA
OUT
SYS
either LDO3 or LDO4 is enabled and all other
LDOs disabled.
OUTPUT VOLTAGE
VO LDO3/4 Output Voltage Accuracy
I
= 5 mA and 300 mA, V
OUT
= V =
SYS
−2.0
−
+2.0
%
L3/4_ACC
OUT
IN34
3.8 V, V
= 1.5 to 3.4 V
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FAN53870, FAN53871
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V;
SYS
OUT1/2
V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V & ≥ V
+ 300 mV, T = −40°C to 125°C, unless
IN12
LDO1/2
IN34/5/6/7
LDO3/4/5/6/7 J
otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
= 1.3 V, V
= V
= V
= 3.8 V, V = 2.05 V,
IN5
A
SYS
IN12
IN34
IN6
IN7
V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V
= 2.8 V.) (continued)
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
OUTPUT VOLTAGE
LDO3/4 Dropout Voltage
Parameter
Conditions
Min
Typ
Max
Unit
V
V
= V
− 100 mV,
−
−
200
mV
L3/4_DO
OUT
OUT_TARGET
= 300 mA, V
I
= 2.8 V,
OUT
OUT_TARGET
V
SYS
= 3.8 V
CURRENT LIMIT
I
LDO3/4 Current Limit
V
+ 500 mV ≤ V
SYS
and V
and V
= 2.0 V to
= 2.0 V to
300
525
400
650
500
775
mA
mA
LIM_L3/4
OUT
IN34
IN34
5.5 V, V
= 3.8 V
I
LDO3/4 Current Limit
V
OUT
+ 500 mV ≤ V
SYS
LIM_H3/4
IN34
IN34
5.5 V, V
= 3.8 V
OUTPUT PROTECTION
UVP
LDO3/4 Falling UVP Output Thresh-
old
V
V
= 3.8 V, V
= 3.8 V, V
= 2.8 V
= 2.8 V
78
88
80
80
90
84
94
% of
L3/4_FL
SYS
OUT
V_Target
UVP
LDO3/4 Rising UVP Output Thresh-
old
% of
V_Target
L3/4_RS
SYS
OUT
R
Output Discharge Resistance
100
120
W
L3/4_DCHG
LDO5
QUIESCENT CURRENT
IQ Quiescent Current, No Load
L5
I
= 0 A, total V
and V current
IN5
−
63
75
mA
OUT
SYS
when LDO5 is enabled and all other LDOs
are disabled.
OUTPUT VOLTAGE
VO
LDO5 Output Voltage Accuracy
I
= 5 mA and 300 mA, V
OUT
= V = 3.8 V,
SYS
−2.0
−
−
+2.0
200
%
L5_ACC
OUT
IN5
V
= 1.5 V to 3.4 V
V
L5_DO
LDO5 Dropout Voltage
V
= V
− 100 mV,
OUT_TARGET
−
mV
OUT
OUT_TARGET
I
= 300 mA, V
= 1.8 V,
OUT
V
= 3.8 V
SYS
CURRENT LIMIT
I
Current Limit
V
+ 500 mV ≤ V
SYS
and V
and V
= 2.0 V to
300
525
400
650
500
775
mA
mA
LIM_L5
OUT
IN5
IN5
5.5 V, V
= 3.8 V
I
Current Limit
V
OUT
+ 500 mV ≤ V
SYS
= 2.0 V to
LIM_H5
IN5
IN5
5.5 V, V
= 3.8 V
OUTPUT PROTECTION
UVP
LDO5 Falling UVP Output Threshold
LDO5 Rising UVP Output Threshold
Output Discharge Resistance
V
V
= 3.8 V, V
= 3.8 V, V
= 2.8 V
= 2.8 V
78
88
80
80
90
84
94
% of
L5_FL
SYS
OUT
V_Target
UVP
% of
V_Target
L5_RS
SYS
OUT
R
100
120
W
L5_DCHG
LDO6/7
QUIESCENT CURRENT
IQ Quiescent Current, No Load
L6/7
I
= 0 A, total current on V
IN7
and V
IN6
−
63
75
mA
OUT
SYS
or V
when LDO6 or LDO7 is enabled and
all other LDOs are disabled.
OUTPUT VOLTAGE
VO
LDO6/7 Output Voltage Accuracy
I
= 5 mA and 300 mA, V
OUT
= V =
SYS
−2.0
−
−
+2.0
300
%
L6/7_ACC
OUT
IN6/7
3.8 V, V
= 1.5 V to 3.4 V
V
LDO6/7 Dropout Voltage
V
= V
− 100 mV,
−
mV
L6/7_DO
OUT
OUT_TARGET
I
= 300 mA, V
= 2.8 V,
OUT_TARGET
OUT
V
= 3.8 V
SYS
www.onsemi.com
8
FAN53870, FAN53871
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V;
SYS
OUT1/2
V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V & ≥ V
+ 300 mV, T = −40°C to 125°C, unless
IN12
LDO1/2
IN34/5/6/7
LDO3/4/5/6/7 J
otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
= 1.3 V, V
= V
= V
= 3.8 V, V = 2.05 V,
IN5
A
SYS
IN12
IN34
IN6
IN7
V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V = 2.8 V.) (continued)
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
CURRENT LIMIT
Parameter
Conditions
Min
Typ
Max
Unit
I
LDO6/7 Current Limit
V
+ 500 mV ≤ V
and V
and V
= 2.0 V
= 2.0 V
300
525
400
650
500
775
mA
mA
LIM_L6/7
OUT
IN6/7
IN6/7
to 5.5 V, V
= 3.8 V
SYS
I
LDO6/7 Current Limit
V
OUT
+ 500 mV ≤ V
LIM_H6/7
IN6/7
IN6/7
to 5.5 V, V
= 3.8 V
SYS
OUTPUT PROTECTION
UVP
LDO6/7 Falling UVP Output Thresh-
old
V
V
= 3.8 V, V
= 3.8 V, V
= 2.8 V
= 2.8 V
78
88
80
80
90
84
94
% of
L6/7_FL
SYS
OUT
V_Target
UVP
LDO6/7 Rising UVP Output Thresh-
old
% of
V_Target
L6/7_RS
SYS
OUT
R
Output Discharge Resistance
RESET_B Logic Low Threshold
RESET_B Logic High Threshold
100
120
W
L6/7_DCHG
I/O LEVELS
V
FAN53870
FAN53871
FAN53870
FAN53871
Isink = 5 mA
0.4
V
IL
0.325
V
1.2
0.825
−
V
IN
V
IN
IH
V
Interrupt Pin Low Level
−
−
−
0.3
1.9
0.5
V
V
OL_INT
V
INT Pin (FAN53870) High Level
Interrupt Pin Leakage
V
SYS
V
INT
= 2.5 V, I
= 1 mA
1.7
−
OH_INT
OUT
I
= V
= 5.5 V
uA
INT
INT_B
IQ CONDITIONS
I
Shutdown Supply Current
Shutdown Supply Current
Shutdown Supply Current
Shutdown Supply Current
Current on V
xxx_EN bits = 0, xxx_SEQ bits = 000,
RESET_B = SDA = SCL = Low, T = 85°C
when = 5.5 V and all
−
−
−
−
−
−
−
3.0
1.5
1.5
1.5
425
mA
mA
mA
mA
mA
Q VSYS_SD
Q VIN12_SD
Q VIN34_SD
SYS
J
I
I
Total current on V
xxx_EN bits = 0, xxx_SEQ bits = 000,
RESET_B = SDA = SCL = Low, T = 85°C
when = 2.0 V and all
IN12
J
Current on V
when = 5.5 V and all
−
IN34
xxx_EN bits = 0, xxx_SEQ bits = 000,
RESET_B = SDA = SCL = Low, TJ = 85°C
I
Current on V
or V
or V when = 5.5 V
IN7
−
Q VIN5/6/7_SD
IN5
IN6
and all xxx_EN bits = 0, xxx_SEQ bits = 000,
RESET_B = SDA = SCL = Low, T = 85°C
J
I
Standby Supply Current − All LDOs Total current on V
enabled and no load.
and all VINs when
IN6
380
Q_STBY
SYS
IN5
V
V
= V
= V
= V
= 5.5 V and
SYS
IN12
IN34
= 2.0 V, RESET_B = High, all xxx_EN
bits = 1, xxx_SEQ = 000
I
Sleep Supply Current
Total current on V and all VINs when
−
12
20
mA
SLP
SYS
V
SYS
V
IN12
= V
= V
= V
= 5.5 V and
IN34
IN5
IN6
= 2.0 V, RESET_B = High, all xxx_EN
2
bits = 0, xxx_SEQ = 000, no I C activity
2
I C TIMING AND PERFORMANCE *
V
SDA and SCL Logic Low threshold
FAN53870
FAN53871
−0.5
−0.5
−
−
−
−
−
−
0.3 V
V
V
IL
DD
0.325
5.5
5.5
0.4
−
V
IH
SDA and SCL Logic High threshold FAN53870
FAN53871
0.7 V
DD
0.825
−
V
OL
SDA Logic Low Output
SDA Sink Current
3 mA Sink
V
I
OL
20
mA
www.onsemi.com
9
FAN53870, FAN53871
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V;
SYS
OUT1/2
V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V & ≥ V
+ 300 mV, T = −40°C to 125°C, unless
IN12
LDO1/2
IN34/5/6/7
LDO3/4/5/6/7 J
otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
= 1.3 V, V
= V
= V
= 3.8 V, V = 2.05 V,
IN5
A
SYS
IN12
IN34
IN6
IN7
V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V = 2.8 V.) (continued)
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2
I C TIMING AND PERFORMANCE *
fSCL
tBUF
SCL Clock Frequency
Fast Mode Plus
−
−
−
1000
kHz
Bus−Free Time Between STOP and Fast Mode Plus
START Conditions
0.5
−
ms
tHD;STA
START or Repeated START Hold
Time
Fast Mode Plus
260
−
−
ns
tLOW
tHIGH
tSU;STA
tSU;DAT
tVD;DAT
tVD;ACK
tR
SCL LOW Period
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
0.5
260
260
50
−
−
−
−
−
−
−
−
−
−
−
ms
ns
ns
ns
ns
ns
ns
ns
SCL HIGH Period
Repeated START Setup Time
Data Setup Time
−
−
Data Valid Time
450
450
120
120
Data Valid Acknowledge Time
SDA and SCL Rise Time
SDA and SCL Fall Time
−
−
tF
20 x V
DD
/ 5.5 V
tSU;STO
Stop Condition Setup Time
Fast Mode Plus
260
−
−
−
−
−
−
ns
pF
pF
ns
Ci
SDA and SCL Input Capacitance
Capacitive Load for SDA and SCL
10
Cb
−
550
50
t
SP
Spike pulse width that input filter
must be suppress
SCL, SDA only
0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Guarantee Levels:
*Guaranteed by Design Only. Not Characterized or Production Tested.
www.onsemi.com
10
FAN53870, FAN53871
SYSTEM CHARACTERISTICS (The following system specifications are guaranteed by design and are not performed in production
testing. They reflect closed loop performance using the Recommended Layout and External Components. Minimum and maximum
values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V, V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V &
SYS
LDO1/2
IN12
LDO1/2
IN34/5/6/7
V
≥ V
+ 300 mV, T = −40°C to +85°C unless otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
=
IN34/5/6/7
LDO3/4/5/6/7
A
A
SYS
IN12
1.3 V, V
= V
= V
= 3.8 V, V
= 2.05 V, V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V
= 2.8 V.)
IN34
IN6
IN7
IN5
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
LDO1/2
Parameter
Conditions
Min
Typ
Max
Unit
SOFT START
T
Startup Time
EN bit = 1 to 90% of V
OUT
(1.05 V),
−
400
−
ms
SS_LDO12
OUT
I
= 10 mA, COUT = 20 mF
PSRR & NOISE
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
Power Supply Rejection Ratio on VIN12
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN12
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN12
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN12
Power Supply Rejection Ratio on VSYS
LDO1/2 Output Noise
V
OUT
C
= 1.35 V, V = 1.2 V,
OUT
−
−
−
−
−
−
−
−
−
68
70
52
57
34
41
30
37
18
−
−
−
−
−
−
−
−
−
dB
dB
L1/2_VIN
L1/2_VS
L1/2_VIN
L1/2_VS
L1/2_VIN
L1/2_VS
L1/2_VIN
L1/2_VS
IN12
I
= 150 mA, C
= 1.0 mF,
IN12
= 10 mF, FREQ = 1 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 1 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 10 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 10 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 100 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 100 kHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 1 MHz
OUT1/2
V
OUT
C
= 1.35 V, V
= 1.2 V,
dB
IN12
OUT
IN12
I
= 150 mA, C
= 1.0 mF,
= 10 mF, FREQ = 1 MHz
OUT1/2
V
N_L1/2
FREQ: 10 Hz to 100 kHz, I
= 100 mA
uVrms
OUT
REGULATION & TRANSIENT PERFORMANCE
REG
REG
LDO Load Regulation
LDO Line Regulation
I
= 1 mA to 800 mA, V
= 3.8 V
−0.001
−0.10
−
−
+0.001 %/mA
L1/2_LD
L1/2_LN
OUT
SYS
V
= 2.5 V to 4.5 V & V
≥ V
+
+0.10
%
SYS
SYS
OUT
1.6 V, V
+ 300 mV ≤ V
≤ 2.0 V,
OUT
IN12
I
= 50 mA
OUT
V
LDO Load Transient
I
= 1 mA ↔ 500 mA, 100 mA/ms,
≥ V + 1.6 V
−40
−
+40
mV
L1/2 TR_LD
OUT
SYS
V
OUT
SHORT CIRCUIT
T
T
Default Short Circuit Debounce Timer
−
−
1.0
20
−
−
ms
ms
L12 SC_DEB
L12 SC_RST
Period from Short Circuit Shutdown to
Restart
LDO3/4
SOFT START
T
Soft Start Time
LDO3_EN or LDO4_EN bit = 1 to 90%
of V = 2.8 V, I = 10 mA,
−
100
−
ms
SS_L3/4
OUT
OUT
C
= 1 mF, C
= 4.7 mF
IN
OUT
www.onsemi.com
11
FAN53870, FAN53871
SYSTEM CHARACTERISTICS (The following system specifications are guaranteed by design and are not performed in production
testing. They reflect closed loop performance using the Recommended Layout and External Components. Minimum and maximum
values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V, V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V &
SYS
LDO1/2
IN12
LDO1/2
IN34/5/6/7
V
≥ V
+ 300 mV, T = −40°C to +85°C unless otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
=
IN34/5/6/7
LDO3/4/5/6/7
A
A
SYS
IN12
1.3 V, V
= V
= V
= 3.8 V, V
= 2.05 V, V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V
= 2.8 V.) (continued)
IN34
IN6
IN7
IN5
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
PSRR & NOISE
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
PSRR
Power Supply Rejection Ratio on VIN34
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN34
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN34
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN34
Power Supply Rejection Ratio on VSYS
LDO3/4 Output Noise
I
= 50 mA, C = 1.0 mF,
IN34
−
−
−
−
−
−
−
−
−
89
85
84
70
57
52
40
36
14
−
−
−
−
−
−
−
−
−
dB
dB
L3/4_VIN
L3/4_VS
L3/4_VIN
L3/4_VS
L34_VIN
L34_VS
OUT
C
= 2.2 mF, FREQ = 1 kHz
OUT3/4
OUT3/4
OUT3/4
OUT3/4
OUT3/4
OUT3/4
OUT3/4
OUT3/4
I
= 50 mA, C
= 1.0 mF,
OUT
IN34
C
= 2.2 mF, FREQ = 1 kHz
I
= 50 mA, C
= 1.0 mF,
dB
OUT
IN34
C
= 2.2 mF, FREQ = 10 kHz
I
= 50 mA, C
= 1.0 mF,
dB
OUT
IN34
C
= 2.2 mF, FREQ = 10 kHz
I
= 50 mA, C
= 1.0 mF,
dB
OUT
IN34
C
= 2.2 mF, FREQ = 100 kHz
I
= 50 mA, C
= 1.0 mF,
dB
OUT
IN34
C
= 2.2 mF, FREQ = 100 kHz
I
= 50 mA, C
IN34
= 1.0 mF,
dB
L3/4_VIN
L3/4_VS
OUT
C
= 2.2 mF, FREQ = 1 MHz
I
= 50 mA, C
= 1.0 mF,
dB
OUT
IN34
C
= 2.2 mF, FREQ = 1 MHz
V
N_L34
FREQ: 10 Hz to 100 kHz, I
= 300 mA
uVRMS
OUT
REGULATION & TRANSIENT PERFORMANCE
REG
LDO Load Regulation
I
= 100 mA to 300 mA, V =
SYS
−0.001
−0.1
−
−
−
−
+0.001 %/mA
L3/4_LD
OUT
VIN34 = 3.8 V, V
= 2.8 V
OUT
REG
LDO Line Regulation
V
V
, V
IN34
= 2.5 to 5.5 V and V ,
SYS
+0.1
+0.3
+40
%
L3/4_LN
SYS
IN34
. V
+ 500 mV, I
= 50 mA
OUT
OUT
V
V
, V
= 2.5 to 5.5 V and V
,
−0.1
SYS
IN34
IN34
SYS
≥ V
+ 500 mV, I
= 300 mA
OUT
OUT
V
LDO Load Transient
I
= 1 mA ↔ 200 mA, 100 mA/ms,
−40
mV
L3/4 TR_LD
OUT
V
= V
= 3.8 V
SYS
IN34
SHORT CIRCUIT
T
Short Circuit Debouncer Timer
−
−
1.0
20
−
−
ms
ms
L3/4 SC_DEB
T
Period from Short Circuit Shutdown to
Restart
LDO34 SC_RST
LDO5
SOFT START
T
Soft Start Time
LDO5_EN bit = 1 to 90% of V
= 2.8 V,
−
100
−
ms
SS_L5
OUT
I
= 10 mA, C = 1 mF, C
= 4.7 mF
OUT
IN
OUT
PSRR & NOISE
PSRR
PSRR
Power Supply Rejection Ratio on VIN5
FREQ = 1 kHz
−
−
−
72
81
80
−
−
−
dB
dB
dB
L5_VIN
L5_VS
Power Supply Rejection Ratio on VSYS FREQ = 1 kHz
PSRR
Power Supply Rejection Ratio on VIN5
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN5
I
= 150 mA, FREQ = 1 kHz,
L5_HV_VIN
OUT
IN
C
= 1.0 mF, C
= 2.2 mF, V
IN5
= 3.8 V,
= 3.8 V,
OUT
V
= 1.8V
OUT
PSRR
I
= 150 mA, FREQ = 1 kHz,
−
−
82
60
−
−
dB
dB
L5_HV_VS
OUT
IN
C
= 1.0 mF, C
= 2.2 mF, V
OUT IN5
V
= 1.8 V
OUT
PSRR
I
= 150 mA, C
OUT5
= 1.0 mF,
L5_VIN
OUT
IN5
C
= 2.2 mF, FREQ = 10 kHz
www.onsemi.com
12
FAN53870, FAN53871
SYSTEM CHARACTERISTICS (The following system specifications are guaranteed by design and are not performed in production
testing. They reflect closed loop performance using the Recommended Layout and External Components. Minimum and maximum
values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V, V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V &
SYS
LDO1/2
IN12
LDO1/2
IN34/5/6/7
V
≥ V
+ 300 mV, T = −40°C to +85°C unless otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
=
IN34/5/6/7
LDO3/4/5/6/7
A
A
SYS
IN12
1.3 V, V
= V
= V
= 3.8 V, V
= 2.05 V, V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V
= 2.8 V.) (continued)
IN34
IN6
IN7
IN5
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
PSRR & NOISE
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
PSRR
PSRR
PSRR
PSRR
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN5
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN5
Power Supply Rejection Ratio on VSYS
LDO5 Output Noise
I
= 150 mA, C = 1.0 mF,
IN5
OUT5
−
−
−
−
−
−
67
40
57
26
36
14
−
−
−
−
−
−
dB
dB
L5_VS
L5_VIN
L5_VS
L5_VIN
L5_VS
OUT
C
= 2.2 mF, FREQ = 10 kHz
I
= 150 mA, C
OUT5
= 1.0 mF,
OUT
IN5
C
= 2.2 mF, FREQ = 100 kHz
I
= 150 mA, C
OUT5
= 1.0 mF,
dB
OUT
IN5
C
= 2.2 mF, FREQ = 100 kHz
I
= 150 mA, C
OUT5
= 1.0 mF,
dB
OUT
IN5
C
= 2.2 mF, FREQ = 1 MHz
I
= 150 mA, C
OUT5
= 1.0 mF,
dB
OUT
IN5
C
= 2.2 mF, FREQ = 1 MHz
V
N_L5
FREQ: 10 Hz to 100 kHz, I
= 300 mA
mVRMS
OUT
REGULATION & TRANSIENT PERFORMANCE
REG
LDO Load Regulation
I
= 100 mA to 300 mA, V
OUT
= V =
IN5
−0.001
−0.1
−
−
+0.001 %/mA
L5_LD
OUT
SYS
3.8 V, V
= 1.8 V
REG
LDO Line Regulation
V
= 2.5 V to 5.5 V, V
= 2.0 V to 5.5 V,
+0.1
+0.4
+40
%
L5_LN
SYS
IN5
and V
, V
≥ V
+ 500 mV,
SYS
IN5
OUT
I
= 50 mA
OUT
V
= 2.5 V to 5.5 V, V
= 2.0 V to 5.5 V, −0.1
−
−
SYS
IN5
+ 500 mV,
and V
, V
≥ V
SYS
IN5
OUT
I
= 300 mA
OUT
V
LDO Load Transient
I
= 1 mA ↔ 200 mA, 100 mA/ms,
= 3.8 V, V = 2.05 V, V = 1.8 V
−40
mV
L5 TR_LD
OUT
V
SYS
IN5
OUT
SHORT CIRCUIT
T
Short Circuit Debouncer Timer
−
−
1.0
20
−
−
ms
ms
L5 SC_DEB
T
Period from Short Circuit Shutdown to
Restart
LDO5 SC_RST
LDO6/7
SOFT START
T
Soft Start Time
LDO6_EN or LDO7_EN bit = 1 to 90% of
−
100
−
ms
SS_L6/7
V
= 2.8 V, I
= 10 mA, C = 1 mF,
OUT
OUT IN
C
OUT
= 4.7 mF
PSRR & NOISE
PSRR
Power Supply Rejection Ratio on VIN6/7
Power Supply Rejection Ratio on VSYS
I
= 150 mA, FREQ = 1 kHz,
−
−
80
72
−
−
dB
dB
L6/7_VIN
OUT
IN
C
= 1.0 mF, C
= 2.2 mF,
OUT
SYS
V
= 2.05 V, V
= 3.8 V, V
= 1.8 V
= 1.8 V
IN6/7
OUT
PSRR
I
= 150 mA, FREQ = 1 kHz,
L6/7_VS
OUT
C
= 1.0 mF, C
IN6/7
= 2.2 mF,
SYS
IN
OUT
V
= 2.05 V, V
= 3.8 V, V
OUT
PSRR
Power Supply Rejection Ratio on VIN6/7
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN6/7
Power Supply Rejection Ratio on VSYS
I
= 150 mA, C
= 1.0 mF,
−
−
−
−
75
75
70
70
−
−
−
−
dB
dB
dB
dB
L6/
7_HV_VIN
OUT
IN6/7
C
= 2.2 mF, FREQ = 1 kHz
OUT6/7
OUT6/7
OUT6/7
OUT6/7
PSRR
L6/
7_HV_VS
I
= 150 mA, C
= 1.0 mF,
OUT
IN6/7
C
= 2.2 mF, FREQ = 1 kHz
PSRR
L6/
7_HV_VIN
I
= 150 mA, C
= 1.0 mF,
OUT
IN6/7
C
= 2.2 mF, FREQ = 10 kHz
PSRR
L6/
7_HV_VS
I
= 150 mA, C
= 1.0 mF,
OUT
IN6/7
C
= 2.2 mF, FREQ = 10 kHz
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13
FAN53870, FAN53871
SYSTEM CHARACTERISTICS (The following system specifications are guaranteed by design and are not performed in production
testing. They reflect closed loop performance using the Recommended Layout and External Components. Minimum and maximum
values are at V
= 2.5 V to 5.5 V & ≥ V
+ 1.6 V, V
= 1.0 V to 2.0 V & ≥ V
+ 200 mV, V
= 1.9 V to 5.5 V &
SYS
LDO1/2
IN12
LDO1/2
IN34/5/6/7
V
≥ V
+ 300 mV, T = −40°C to +85°C unless otherwise noted. Typical values are at T = 25°C, V
= 3.8 V, V
=
IN34/5/6/7
LDO3/4/5/6/7
A
A
SYS
IN12
1.3 V, V
= V
= V
= 3.8 V, V
= 2.05 V, V
= 1.05 V, V
= 2.8 V, V
= 1.8 V and V
= 2.8 V.) (continued)
IN34
IN6
IN7
IN5
LDO1/2
LDO3/4
LDO5
LDO6/7
Symbol
PSRR & NOISE
PSRR
Parameter
Conditions
Min
Typ
Max
Unit
Power Supply Rejection Ratio on VIN6/7
Power Supply Rejection Ratio on VSYS
Power Supply Rejection Ratio on VIN6/7
Power Supply Rejection Ratio on VSYS
LDO6/7 Output Noise
I
= 150 mA, C = 1.0 mF,
IN6/7
−
−
−
−
−
53
46
40
33
40
−
−
−
−
−
dB
dB
L6/
7_HV_VIN
OUT
C
= 2.2 mF, FREQ = 100 kHz
OUT6/7
OUT6/7
OUT6/7
OUT6/7
PSRR
L6/
7_HV_VS
I
= 150 mA, C
= 1.0 mF,
OUT
IN6/7
C
= 2.2 mF, FREQ = 100 kHz
PSRR
L6/
7_HV_VIN
I
= 150 mA, C
= 1.0 mF,
dB
OUT
IN6/7
C
= 2.2 mF, FREQ = 1 MHz
PSRR
L6/
7_HV_VS
I
= 150 mA, C
= 1.0 mF,
dB
OUT
IN6/7
C
= 2.2 mF, FREQ = 1 MHz
V
N_L6/7
FREQ: 10 Hz to 100 kHz, I
= 300 mA
mVRMS
OUT
REGULATION & TRANSIENT PERFORMANCE
REG
LDO Load Regulation
I
= 100 mA to 300 mA, V =
SYS
−0.001
−0.1
−
−
+0.001 %/mA
L6/7_LD
OUT
V
= 3.8 V, V
= 2.8 V
IN6/7
OUT
REG
LDO Line Regulation
V
= 2.5 V to 5.5 V, V
= 2.0 V to
OUT
+0.1
+0.5
+40
%
L6/7_LN
SYS
IN6/7
5.5 V, and V
, V
≥ V
+ 500 mV,
SYS
IN6/7
I
= 50mA
OUT
V
= 2.5 V to 5.5 V, V
= 2.0 V to
OUT
−0.1
−40
−
−
SYS
IN6/7
5.5 V, and V
, V
≥ V
+ 500 mV,
SYS
IN6/7
I
= 300 mA
OUT
V
LDO Load Transient
I
= 1 mA ↔ 200 mA, 100 mA/ms,
= V = 3.8 V, V = 2.8 V
mV
L6/7 TR_LD
OUT
V
SYS
IN6/7
OUT
SHORT CIRCUIT
T
Short Circuit Debouncer Timer
−
−
1.0
20
−
−
ms
ms
L6/7 SC_DEB
T
Period from Short Circuit Shutdown to
Restart
LDO6/7 SC_RST
THERMAL PROTECTION
T
Thermal Warning
−
−
−
125
140
15
−
−
−
°C
°C
°C
WRN
T
Thermal Shutdown
SD
T
Thermal Hysteresis for TSD and TWRN
HYS
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14
FAN53870, FAN53871
TYPICAL CHARACTERISTICS
(UNLESS OTHERWISE NOTED, T = 25°C, V
= 3.8 V, V
= 1.3 V, V
, V , V
IN6
= 3.8 V, V
= 2.05 V, V
= 1.05 V,
A
SYS
IN12
IN34
IN7
IN5
LDO1/2
V
= 2.8 V, V
= 1.8 V AND V
= 2.8 V, RECOMMENDED LAYOUT AND EXTERNAL COMPONENTS.)
LDO3/4
LDO5
LDO6/7
Figure 4. LDO1/2 Output Regulation vs. Load
Current and Input Voltage, VOUT = 1.05 V
Figure 5. LDO3/4 Output Regulation vs. Load
Current and Input Voltage, VOUT = 2.8 V
Figure 6. LDO5 Output Regulation vs. Load
Current and Input Voltage, VOUT = 1.8 V
Figure 7. LDO6/7 Output Regulation vs. Load
Current and Input Voltage, VOUT = 2.8 V
Figure 8. LDO1/2 Dropout Voltage vs. Target
Output Voltage and Temperature, IOUT = 800 mA
Figure 9. LDO3/4/5 Dropout Voltage vs. Target
Output Voltage and Temperature, IOUT = 300 mA
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15
FAN53870, FAN53871
TYPICAL CHARACTERISTICS (CONTINUED)
(UNLESS OTHERWISE NOTED, T = 25°C, V
= 3.8 V, V
= 1.3 V, V
, V , V
= 3.8 V, V
= 2.05 V, V
= 1.05 V,
A
SYS
IN12
IN34
IN6
IN7
IN5
LDO1/2
V
= 2.8 V, V
= 1.8 V AND V
= 2.8 V, RECOMMENDED LAYOUT AND EXTERNAL COMPONENTS.)
LDO3/4
LDO5
LDO6/7
Figure 10. LDO6/7 Dropout Voltage vs. Target
Output Voltage and Temperature, IOUT = 300 mA
Figure 11. LDO1/2 PSRR vs. Frequency,
150 mA Load
Figure 12. LDO3/4 PSRR vs. Frequency,
50 mA Load
Figure 13. LDO5 PSRR vs. Frequency,
150 mA Load
Figure 14. LDO6/7 PSRR vs. Frequency,
150 mA Load
Figure 15. LDO1/2 Output Noise vs. Frequency,
100 mA Load
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16
FAN53870, FAN53871
TYPICAL CHARACTERISTICS (CONTINUED)
(UNLESS OTHERWISE NOTED, T = 25°C, V
= 3.8 V, V
= 1.3 V, V
, V , V
= 3.8 V, V
= 2.05 V, V
= 1.05 V,
A
SYS
IN12
IN34
IN6
IN7
IN5
LDO1/2
V
= 2.8 V, V
= 1.8 V AND V
= 2.8 V, RECOMMENDED LAYOUT AND EXTERNAL COMPONENTS.)
LDO3/4
LDO5
LDO6/7
Figure 16. LDO3/4 Output Noise vs. Frequency,
300 mA Load
Figure 17. LDO5 Output Noise vs. Frequency,
300 mA Load
Figure 19. LDO1/2 Load Transient, VIN = 1.3 V,
V
OUT = 1.05 V, 1 mA e 500 mA, 5 ms Edge
Figure 18. LDO6/7 Output Noise vs. Frequency,
300 mA Load
Figure 20. LDO3/4 Load Transient, VIN = 3.8 V,
Figure 21. LDO5 Load Transient, VIN = 2.05 V, VOUT
V
OUT = 2.8 V, 1 mA e 200 mA, 2 ms Edge
= 1.8 V, 1 mA e 200 mA, 2 ms Edge
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17
FAN53870, FAN53871
TYPICAL CHARACTERISTICS (CONTINUED)
(UNLESS OTHERWISE NOTED, T = 25°C, V
= 3.8 V, V
= 1.3 V, V
, V , V
= 3.8 V, V
= 2.05 V, V
= 1.05 V,
A
SYS
IN12
IN34
IN6
IN7
IN5
LDO1/2
V
= 2.8 V, V
= 1.8 V AND V
= 2.8 V, RECOMMENDED LAYOUT AND EXTERNAL COMPONENTS.)
LDO3/4
LDO5
LDO6/7
Figure 22. LDO6/7 Load Transient, VIN = 3.8 V,
V
OUT = 2.8 V, 1 mA e 200 mA, 2 ms Edge
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18
FAN53870, FAN53871
FUNCTIONAL SPECIFICATIONS
Device Operation
Overview
reach the UVP rising threshold, an UVP fault will be
The FAN53870 micro Power Management IC(PMIC) is
optimized to supply different sub systems of battery
powered mobile applications. It integrates seven
low−dropout regulators: two high current LDOs, three ultra
low noise / high PSRR LDOs, two general purpose LDOs.
The features of the FAN53870 can be programmed
declared.
To disable the FAN53870 LDOs, set the LDOx_EN bits
to “0”. The active discharge feature is enabled by default,
with which, an 100 W resister is connected between VOUT
and GND to discharge the output capacitors when the
LDOx_en bits are set to “0”.
2
through an I C interface.
To do a global shutdown of all LDOs, set RESET_B pin
low.
Under Voltage Lockout (UVLO)
When enabling, if VSYS is above Power−On Reset (POR)
voltage but below its UVLO rising threshold, or if VINs of
the LDOs are below their UVLO rising threshold, the
assigned UVLO interrupt bit and UVLO status bit will be
set, and the Interrupt pin asserted. The UVLO status bit
remains set as long as the input voltage is below its UVLO
rising threshold.
When VSYS or VINs fall below their UVLO falling
threshold, the LDO(s) will shut down, an UVLO interrupt
will be declared. The UVLO status bit remains set until the
input voltage rises above its UVLO rising threshold, and the
LDO(s) performs startup immediately.
The suspend bits will be set upon shutdown. The LDO(s)
will stay in shutdown for a minimum of 20 ms and then
attempt a restart if VSYS or VINs have risen above their
UVLO rising threshold. The suspend bits are cleared upon
restart. The LDO(s) will be disabled permanently after the
4th UVLO fault.
Over−current Protection (OCP)
The LDOs are protected from excessive load and
short−circuit. The current limit level can be programmed
2
through the I C interface.
When an over−load event occurs, the current is
automatically limited to the programmed current limit. And
once the current limit is detected, the associated OCP status
bit is set, and if the LDO remains in current limit for more
than 1 ms, the OCP interrupt bit will be set, and the Interrupt
pin asserted. Then the LDO will shut down permanently
without attempting any restart, meanwhile the associated
suspend bit is set and status bit is cleared.
2
The OCP debounce timer is programmable through I C.
Hiccup mode option is also available for OCP, which can be
accommodated by contacting an onsemi representative.
Under Voltage Protection (UVP)
If the output voltage falls approximately 20% (10% for
LDO1/2) below the target VOUT, the associated UVP status
bit will be set. If the fault persists for more than 50 ms, the
UVP interrupt bit will be set, and the Interrupt pin asserted.
The LDO will then be disabled, the associated status bit is
cleared and the suspend bit is set. The interrupt bit will be
cleared upon a read of the bit.
The LDO will attempt a restart in 20 ms and the suspend
bit will be reset to “0” upon restart. And after the 4th UVP
fault, the LDO shuts down permanently.
Thermal Management
When the die temperature rises to a nominal 125°C, the
thermal Warning status bit will be set to “1” and remain set
until the die temperature drops to a nominal 110°C.
If the die temperature continues to rise to a nominal
140°C, a Thermal Shutdown event is activated, all the LDOs
are disabled, the Thermal Shutdown interrupt bit is set but
2
I C communication remains. The Thermal Shutdown status
bit is also set and will remain set as long as the device is
above the Thermal Warning temperature. The chip suspend
bit is set upon shutdown.
After the die temperature falls below the Thermal
Warning threshold, the Thermal Shutdown status and chip
suspend bits will be cleared, and the device will return to the
operating conditions prior to the thermal shutdown event.
4−Fault Shutdown
To prevent repetitive starting and faulting of an LDO or of
the IC itself, detection of 4 failures will result in a permanent
shutdown of the LDO, or if it is a system fault, the entire IC
will shut down permanently.
Individual LDO Fault: the LDO will be latched−off after
the 4th individual LDO fault (any combination of UVP,
and/or OCP, and/or VINx UVLO), and the LDOx_EN bit
will be cleared. In order to clear the latch−off and re−enable
the LDOs, set the LDOx_EN bits to “1”.
Chip Fault: all the LDOs will be latched−off after the 4th
chip fault (any combination of Thermal Shutdown, and/or
VSYS UVLO) with all the LDOx_EN bits cleared. In order
to clear the latch−off, RESET_B pin needs to be pulled low.
Enabling / Disabling
The FAN53870 LDOs can be enabled and disabled
independently with the LDOx_EN bits in the ENABLE
register.
To enable FAN53870 LDOs, with RESET_B pin high, set
the LDOx_EN bits to “1”. The FAN53870 LDOs have
internal soft−start, which limits the inrush current to the
ILIM setting. The LDOs will ignore faults during the first
1.5 ms at startup. After 1.5 ms, if the LDO output fails to
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19
FAN53870, FAN53871
Reset
When the RESET_B pin is pulled LOW, the
I2C Slave Address
The default I C slave address is shown in Table 3. The
2
INTERRUPTx and STATUSx bits will be cleared. All the
other registers will remain set to their programmed values,
but I C communication with the device is disabled.
LSB of the address byte is used as the read/write bit and is
not included in the 7 bit Hex, Decimal or Binary value as
shown in Table 3. Table 4 is an example (using the
FAN53870) to show the location of the R/W bit.
2
Additionally, all internal fault counters will reset to 0.
2
2
When the RESET_B pin is pulled HIGH, the I C block is
The I C address can also be changed by setting in the
turned on. The Reset_B pin should not be asserted high
while there is data transmission on the I C bus. This will
I2C_ADDR_SEL register.
Other default slave addresses can be accommodated by
contacting an onsemi representative.
2
ensure the FAN53870 doesn’t mis−interpret a logic low on
SDA as a falling edge and inadvertently create a “Start”
condition, and unintended data written to the FAN53870
registers. It is recommended that the FAN53870 is enabled
Table 3. I2C SLAVE ADDRESS
Device
Hex
7’h35
7‘h20
Decimal
53d
7 bit Binary
011 0101
2
when there is a brief break in I C data transmissions.
FAN53870
FAN53871
The SOFT_RESET bits in the RESET register can be used
to clear all registers to their default values.
32d
010 0000
Power Up/Down Sequence
Power up and power down sequence can be programmed
and controlled with the dedicated registers xxxx_SEQ and
SEQUENCING.
Table 4. I2C (7 bit) SLAVE ADDRESS BYTE
7
6
5
4
3
2
1
0
0
1
1
0
1
0
1
R/W
If an LDO faults during a start−up sequence, the other
LDOs will still be starting up in their assigned time slot. The
xxxx_SEQ register bits for the faulted LDO will remain set
to the previously values. The system can then attempt to start
the faulted LDO in another sequence by setting the
SEQ_CONTROL bits to “01” or by clearing the xxxx_SEQ
bits to “000” and writing a “1” to the enable bit for the faulted
LDO.
Bus Timing
As shown in Figure 23, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
Data change allowed
No Fault Shutdown
FAN53870 provides a “No Fault Shutdown” feature,
which prevents LDOs from shutting down during an OCP or
UVP event . It is activated by setting the FLT_SD_B bit in
RESET register to “1”.
SDA
tH
By setting FLT_SD_B to “1”, it prevents the shutdown
during an OCP or UVP event, but not during LDO VIN
UVLO event. With FLT_SD_B=1, when LDO VIN UVLO,
OCP or OVP event occurs, the interrupt and status bits will
still indicate the fault has occurred, but the fault counter will
not be incremented.
tSU
SCL
Figure 23. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 24.
I2C Functionality
2
I C Interface
The FAN53870 serial interface is compatible with
2
Standard, Fast and Fast Plus Mode I C Bus specifications.
tHD;STA
Slave Address
MS Bit
SDA
SCL
The SCL line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
Please refer to the Reset section for guidance on
RESET_B LOW to HIGH pin timing for proper enabling of
Figure 24. Start Bit
2
the I C block.
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20
FAN53870, FAN53871
Transactions end with a STOP condition, which is SDA
Read and Write Transactions
transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 25.
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Master Drives Bus
Slave Drives Bus
defined as
and
.
Slave Releases
Master Drives
tHD,STO
All addresses and data are MSB first.
ACK(0) or
NACK(1)
Multi−Byte (Sequential) Read and Write Transactions
SDA
SCL
Sequential Write (Figure 29)
The Slave Address, Reg Addr address, and the first data
byte are transmitted to the FAN53870 in the same way as in
a single−byte write (Figure 27). However, instead of
generating a Stop condition, the master transmits additional
bytes that are written to consecutive sequential registers
after the falling edge of the eighth bit. After the last byte
written and its ACK bit received, the master issues a STOP
bit. The IC contains an 8−bit counter that increments the
address pointer after each byte is written.
Figure 25. Stop Bit
During a read from the FAN53870, the master issues a
Repeated Start after sending the register address and before
resending the slave address. The Repeated Start is a 1−to−0
transition on SDA while SCL is HIGH, as shown in Figure
26.
Sequential Read (Figure 30)
Sequential reads are initiated in the same way as a
single−byte read (Figure 28), except that once the slave
transmits the first data byte, the master issues an
acknowledge instead of a STOP condition. This directs the
Slave Releases
t SU,STU
t HD,STA
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
2
slave’s I C logic to transmit the next sequentially addressed
8−bit word. The FAN53870 contains an 8−bit counter that
increments the address pointer after each byte is read, which
allows the entire memory contents to be read during one I C
Figure 26. Repeated Start Timing
2
transaction.
Figure 27. Single−Byte Write Transaction
Figure 28. Single−Byte Read Transaction
Figure 29. Multi−Byte (Sequential) Write Transaction
Figure 30. Multi−Byte (Sequential) Read Transaction
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21
FAN53870, FAN53871
REGISTER MAPPING TABLE
Table 5. REGISTER MAPPING
Read Only
Bit[4]
Write Only
Bit[3]
Read / Write Read / Clear Write / Clear
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
Name
PRODUCT ID
SILICON REV ID
IOUT
Bit[7]
Bit[6]
Bit[5]
Bit[2]
Bit[1]
Bit[0]
Product ID
Revision
0
0
LDO7_ILIM
LDO7_EN
LDO6_ILIM
LDO6_EN
LDO5_ILIM
LDO5_EN
LDO4_ILIM
LDO4_EN
LDO3_ILIM
LDO3_EN
LDO2_ILIM
LDO2_EN
LDO1_ILIM
LDO1_EN
ENABLE
LDO1
LDO1_VOUT
LDO2
LDO2_VOUT
LDO3_VOUT
LDO4_VOUT
LDO5_VOUT
LDO6_VOUT
LDO7_VOUT
LDO3
LDO4
LDO5
LDO6
LDO7
LDO12_SEQ
LDO34_SEQ
LDO56_SEQ
LDO7_SEQ
SEQUENCING
DISCHARGE
RESET
0
0
0
LDO2_SEQ
LDO1_SEQ
LDO3_SEQ
LDO5_SEQ
LDO7_SEQ
SEQ_COUNT
LDO6_DIS
LDO4_SEQ
LDO6_SEQ
0
SEQ_SPEED
LDO1_DIS
SOFT_RESET
SEQ_CONTROL
SEQ_ON
LDO4_DIS
0
0
LDO2_DIS
LDO3_DIS
LDO5_DIS
LDO7_DIS
FLT_SD_B
OCP_TIMER
I2C_ADDR
0
I2C_ADDR_SEL
LDO4_COMP_SEL
LDO3_COMP_SEL
LDO7_COMP_SEL
LDO2_COMP_SEL
LDO6_COMP_SEL
LDO4_UVP LDO3_UVP
LDO1_COMP_SEL
LDO5_COMP_SEL
LDO_COMP0
LDO_COMP1
INTERRUPT1
0
0
LDO7_UVP
_INT
LDO6_UVP
_INT
LDO5_UVP
_INT
LDO2_UVP
_INT
LDO1_UVP
_INT
_INT
_INT
0x16
0x17
0x18
0x19
0x1A
INTERRUPT2
INTERRUPT3
STATUS1
0
LDO7_OCP
_INT
LDO6_OCP
_INT
LDO5_OCP
_INT
LDO4_OCP
_INT
LDO3_OCP
_INT
LDO2_OCP
_INT
LDO1_OCP
_INT
TSD_INT
TSD_WRN
_INT
VSYS_UVLO
_INT
LDO7_UVLO
_INT
LDO6_UVLO
_INT
LDO5_UVLO LDO34_UVLO LDO12_UVLO
_INT
_INT
_INT
0
0
LDO7_UVP
_STAT
LDO6_UVP
_STAT
LDO5_UVP
_STAT
LDO4_UVP
_STAT
LDO3_UVP
_STAT
LDO2_UVP
_STAT
LDO1_UVP
_STAT
STATUS2
LDO7_OCP
_STAT
LDO6_OCP
_STAT
LDO5_OCP
_STAT
LDO4_OCP
_STAT
LDO3_OCP
_STAT
LDO2_OCP
_STAT
LDO1_OCP
_STAT
STATUS3
TSD_STAT
TSD_WRN
_STAT
VSYS_UVLO
_STAT
LDO7_UVLO
_STAT
LDO6_UVLO
_STAT
LDO5_UVLO
_STAT
LDO34_UVL LDO12_UVLO
_STAT
O_STAT
0x1B
0x1C
STATUS4
MINT1
CHIP_SUSD
LDO7_SUSD
LDO6_SUSD
LDO5_SUSD
LDO4_SUSD
LDO3_SUSD
LDO2_SUSD
LDO1_SUSD
0
MASK_LDO7
_UVP
MASK_LDO6
_UVP
MASK_LDO5
_UVP
MASK_LDO4
_UVP
MASK_LDO3
_UVP
MASK_LDO2
_UVP
MASK_LDO1
_UVP
0x1D
0x1E
MINT2
MINT3
0
MASK_LDO7
_OCP
MASK_LDO6
_OCP
MASK_LDO5
_OCP
MASK_LDO4
_OCP
MASK_LDO3
_OCP
MASK_LDO
2_OCP
MASK_LDO
1_OCP
MASK_TSD
MASK_TSD
_WRN
MASK_VSYS
_UVLO
MASK_LDO7
_UVLO
MASK_LDO6 MASK_LDO5 MASK_LDO34 MASK_LDO12
_UVLO _UVLO _UVLO
_UVLO
www.onsemi.com
22
FAN53870, FAN53871
REGISTER DETAILS
Table 6. REGISTER DETAILS − 0x00 PRODUCT ID
0x00 PRODUCT ID
Default = 00000001
Description
Bit
Name
Product ID
Default
Type
7:0
00000001
Read
Identifies vendor and device type
Code
Product
FAN53870
00000001
Table 7. REGISTER DETAILS − 0x01 SILICON REV ID
0x01 SILICON REV ID
Default = 00000001
Description
Bit
Name
Default
Type
7:0
Revision
00000001
Read
Identifies silicon revision
Table 8. REGISTER DETAILS − 0x02 IOUT
0x02 IOUT
Default = 01111111
Description
Bit
7
Name
Default
Type
UNUSED
LDO7_ILIM
6
1
R/W
Code
Current Limit
400 mA
0
1
650 mA
5
4
3
2
1
0
LDO6_ILIM
LDO5_ILIM
LDO4_ILIM
LDO3_ILIM
LDO2_ILIM
LDO1_ILIM
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Code
Current Limit
400 mA
0
1
650 mA
Code
Current Limit
400 mA
0
1
650 mA
Code
Current Limit
400 mA
0
1
650 mA
Code
Current Limit
400 mA
0
1
650 mA
Code
Current Limit
925 mA
0
1
Code
0
1250 mA
Current Limit
925 mA
1
1250 mA
www.onsemi.com
23
FAN53870, FAN53871
Table 9. REGISTER DETAILS − 0x03 ENABLE
0x03 ENABLE
Default = 00000000
Description
Bit
7
Name
Default
Type
UNUSED
LDO7_EN
6
0
R/W
Enable bit for LDO7. This bit only controls
the state of LDO7 if LDO7_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
5
4
3
2
1
0
LDO6_EN
LDO5_EN
LDO4_EN
LDO3_EN
LDO2_EN
LDO1_EN
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Enable bit for LDO6. This bit only controls
the state of LDO6 if LDO6_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
Enable bit for LDO5. This bit only controls
the state of LDO5 if LDO5_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
Enable bit for LDO4. This bit only controls
the state of LDO4 if LDO4_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
Enable bit for LDO3. This bit only controls
the state of LDO3 if LDO3_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
Enable bit for LDO2. This bit only controls
the state of LDO2 if LDO2_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
Enable bit for LDO1. This bit only controls
the state of LDO1 if LDO1_SEQ = 000.
Code
Status of LDO
Disabled
0
1
Enabled
www.onsemi.com
24
FAN53870, FAN53871
Table 10. REGISTER DETAILS − 0x04 LDO1
0x04 LDO1
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO1_VOUT 00000000 R/W
Sets LDO1 regulation target voltage.
Equation: Vout = 0.800 V + [(d − 99) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.800 V
1.032 V
1.040 V
1.048 V
1.056 V
1.064 V
1.072 V
1.080 V
1.088 V
1.096 V
1.104 V
1.112 V
1.120 V
1.128 V
1.136 V
1.144 V
1.152 V
1.160 V
1.168 V
1.176 V
1.184 V
1.192 V
1.200 V
1.208 V
1.216 V
1.224 V
1.232 V
1.240 V
1.248 V
1.256 V
1.264 V
1.272 V
1.280 V
1.288 V
1.296 V
1.304 V
1.312 V
1.320 V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
0.808 V
www.onsemi.com
25
FAN53870, FAN53871
Table 10. REGISTER DETAILS − 0x04 LDO1 (continued)
0x04 LDO1
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
1.328 V
1.336 V
1.344 V
1.352 V
1.360 V
1.368 V
1.376 V
1.384 V
1.392 V
1.400 V
1.408 V
1.416 V
1.424 V
1.432 V
1.440 V
1.448 V
1.456 V
1.464 V
1.472 V
1.480 V
1.488 V
1.496 V
1.504 V
Reserved
Reserved
Reserved
Reserved
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.816 V
0.824 V
0.832 V
0.840 V
0.848 V
0.856 V
0.864 V
0.872 V
0.880 V
0.888 V
0.896 V
0.904 V
0.912 V
0.920 V
0.928 V
0.936 V
0.944 V
0.952 V
0.960 V
0.968 V
0.976 V
0.984 V
0.992 V
1.000 V
1.008 V
1.016 V
1.024 V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
www.onsemi.com
26
FAN53870, FAN53871
Table 11. REGISTER DETAILS − 0x05 LDO2
0x05 LDO2
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO2_VOUT 00000000 R/W
Sets LDO2 regulation target voltage.
Equation: Vout = 0.800 V + [(d − 99) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.800 V
1.032 V
1.040 V
1.048 V
1.056 V
1.064 V
1.072 V
1.080 V
1.088 V
1.096 V
1.104 V
1.112 V
1.120 V
1.128 V
1.136 V
1.144 V
1.152 V
1.160 V
1.168 V
1.176 V
1.184 V
1.192 V
1.200 V
1.208 V
1.216 V
1.224 V
1.232 V
1.240 V
1.248 V
1.256 V
1.264 V
1.272 V
1.280 V
1.288 V
1.296 V
1.304 V
1.312 V
1.320 V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
0.808 V
www.onsemi.com
27
FAN53870, FAN53871
Table 11. REGISTER DETAILS − 0x05 LDO2 (continued)
0x05 LDO2
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
1.328 V
1.336 V
1.344 V
1.352 V
1.360 V
1.368 V
1.376 V
1.384 V
1.392 V
1.400 V
1.408 V
1.416 V
1.424 V
1.432 V
1.440 V
1.448 V
1.456 V
1.464 V
1.472 V
1.480 V
1.488 V
1.496 V
1.504 V
Reserved
Reserved
Reserved
Reserved
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0.816 V
0.824 V
0.832 V
0.840 V
0.848 V
0.856 V
0.864 V
0.872 V
0.880 V
0.888 V
0.896 V
0.904 V
0.912 V
0.920 V
0.928 V
0.936 V
0.944 V
0.952 V
0.960 V
0.968 V
0.976 V
0.984 V
0.992 V
1.000 V
1.008 V
1.016 V
1.024 V
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
www.onsemi.com
28
FAN53870, FAN53871
Table 12. REGISTER DETAILS − 0x06 LDO3
0x06 LDO3
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO3_VOUT 00000000 R/W
Sets LDO3 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
www.onsemi.com
29
FAN53870, FAN53871
Table 12. REGISTER DETAILS − 0x06 LDO3 (continued)
0x06 LDO3
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
1.668 V
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
2.180 V
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
2.692 V
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
3.204 V
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
30
FAN53870, FAN53871
Table 13. REGISTER DETAILS − 0x07 LDO4
0x07 LDO4
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO4_VOUT 00000000 R/W
Sets LDO4 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
www.onsemi.com
31
FAN53870, FAN53871
Table 13. REGISTER DETAILS − 0x07 LDO4 (continued)
0x07 LDO4
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
2.692 V
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
1.668 V
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
2.180 V
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
3.204 V
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
32
FAN53870, FAN53871
Table 14. REGISTER DETAILS − 0x08 LDO5
0x08 LDO5
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO5_VOUT 00000000 R/W
Sets LDO5 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
www.onsemi.com
33
FAN53870, FAN53871
Table 14. REGISTER DETAILS − 0x08 LDO5 (continued)
0x08 LDO5
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
2.180 V
2.188 V
2.196V
2.204 V
2.212 V
2.220 V
2.228V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
1.668 V
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
2.692 V
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
3.204 V
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
34
FAN53870, FAN53871
Table 15. REGISTER DETAILS − 0x09 LDO6
0x09 LDO6
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO6_VOUT 00000000 R/W
Sets LDO6 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) x 8 mV], where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
www.onsemi.com
35
FAN53870, FAN53871
Table 15. REGISTER DETAILS − 0x09 LDO6 (continued)
0x09 LDO6
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
2.180 V
2.188V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
1.668 V
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
2.692 V
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
3.204 V
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
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FAN53870, FAN53871
Table 16. REGISTER DETAILS − 0x0A LDO7
0x0A LDO7
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO7_VOUT 00000000 R/W
Sets LDO7 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) x 8 mV];, where d is the decimal value of the register
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
VOUT
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
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FAN53870, FAN53871
Table 16. REGISTER DETAILS − 0x0A LDO7 (continued)
0x0A LDO7
Name Default
Default = 00000000
Description
Bit
Type
Hex
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
1.668 V
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
Hex
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
Hex
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
VOUT
Hex
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
VOUT
2.180 V
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
2.692 V
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
3.204 V
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
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FAN53870, FAN53871
Table 17. REGISTER DETAILS − 0x0B LDO12_SEQ
0x0B LDO12_SEQ
Default = 00000000
Description
Bit
7:6
5:3
Name
Default
Type
UNUSED
LDO2_SEQ
000
R/W
The LDO2 sequencing is selected by setting bits [5:3].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO2_EN bit
Selects slot 1 for the LDO2 to be enabled in at power up
Selects slot 2 for the LDO2 to be enabled in at power up
Selects slot 3 for the LDO2 to be enabled in at power up
Selects slot 4 for the LDO2 to be enabled in at power up
Selects slot 5 for the LDO2 to be enabled in at power up
Selects slot 6 for the LDO2 to be enabled in at power up
Selects slot 7 for the LDO2 to be enabled in at power up
2:0
LDO1_SEQ
000
R/W
The LDO1 sequencing is selected by setting bits [2:0].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO1_EN bit
Selects slot 1 for the LDO1 to be enabled in at power up
Selects slot 2 for the LDO1 to be enabled in at power up
Selects slot 3 for the LDO1 to be enabled in at power up
Selects slot 4 for the LDO1 to be enabled in at power up
Selects slot 5 for the LDO1 to be enabled in at power up
Selects slot 6 for the LDO1 to be enabled in at power up
Selects slot 7 for the LDO1 to be enabled in at power up
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FAN53870, FAN53871
Table 18. REGISTER DETAILS − 0x0C LDO34_SEQ
0x0x0C LDO34_SEQ
Default = 00000000
Description
Bit
7:6
5:3
Name
Default
Type
UNUSED
LDO4_SEQ
000
R/W
The LDO4 sequencing is selected by setting bits [5:3].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO4_EN bit.
Selects slot 1 for the LDO4 to be enabled in at power up.
Selects slot 2 for the LDO4 to be enabled in at power up.
Selects slot 3 for the LDO4 to be enabled in at power up.
Selects slot 4 for the LDO4to be enabled in at power up.
Selects slot 5 for the LDO4 to be enabled in at power up.
Selects slot 6 for the LDO4 to be enabled in at power up.
Selects slot 7 for the LDO4 to be enabled in at power up.
2:0
LDO3_SEQ
000
R/W
The LDO3 sequencing is selected by setting bits [2:0].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO3_EN bit.
Selects slot 1 for the LDO3 to be enabled in at power up.
Selects slot 2 for the LDO3 to be enabled in at power up.
Selects slot 3 for the LDO3 to be enabled in at power up.
Selects slot 4 for the LDO3 to be enabled in at power up.
Selects slot 5 for the LDO3 to be enabled in at power up.
Selects slot 6 for the LDO3 to be enabled in at power up.
Selects slot 7 for the LDO3 to be enabled in at power up.
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FAN53870, FAN53871
Table 19. REGISTER DETAILS − 0x0D LDO56_SEQ
0x0D LDO56_SEQ
Default = 00000000
Description
Bit
7:6
5:3
Name
Default
Type
UNUSED
LDO6_SEQ
000
R/W
The LDO6 sequencing is selected by setting bits [5:3].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO6_EN bit.
Selects slot 1 for the LDO6 to be enabled in at power up.
Selects slot 2 for the LDO6 to be enabled in at power up.
Selects slot 3 for the LDO6 to be enabled in at power up.
Selects slot 4 for the LDO6 to be enabled in at power up.
Selects slot 5 for the LDO6 to be enabled in at power up.
Selects slot 6 for the LDO6 to be enabled in at power up.
Selects slot 7 for the LDO6 to be enabled in at power up.
2:0
LDO5_SEQ
000
R/W
The LDO5 sequencing is selected by setting bits [2:0].
Code
Code
000
001
010
011
Slot Selected
Slot Selected
2
Controlled through I C by setting the LDO5_EN bit.
Selects slot 1 for the LDO5 to be enabled in at power up.
Selects slot 2 for the LDO5 to be enabled in at power up.
Selects slot 3 for the LDO5 to be enabled in at power up.
Selects slot 4 for the LDO5 to be enabled in at power up.
Selects slot 5 for the LDO5 to be enabled in at power up.
Selects slot 6 for the LDO5 to be enabled in at power up.
Selects slot 7 for the LDO5 to be enabled in at power up.
100
101
110
111
Table 20. REGISTER DETAILS − 0x0E LDO7_SEQ
0x0E LDO7_SEQ
Default = 00000000
Description
Bit
7:3
2:0
Name
Default
Type
UNUSED
LDO7_SEQ
000
R/W
The LDO7 sequencing is selected by setting bits [2:0].
Code
000
001
010
011
100
101
110
111
Slot Selected
2
Controlled through I C by setting the LDO7_EN bit.
Selects slot 1 for the LDO7 to be enabled in at power up.
Selects slot 2 for the LDO7 to be enabled in at power up.
Selects slot 3 for the LDO7 to be enabled in at power up.
Selects slot 4 for the LDO7 to be enabled in at power up.
Selects slot 5 for the LDO7 to be enabled in at power up.
Selects slot 6 for the LDO7 to be enabled in at power up.
Selects slot 7 for the LDO7 to be enabled in at power up.
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FAN53870, FAN53871
Table 21. REGISTER DETAILS − 0x0F SEQUENCING
0x0F SEQUENCING
Default = 00000000
Description
Bit
Name
Default
Type
7:6
SEQ_SPEED
00
R/W
Code
00
Period per Slot
500 ms
1.0 ms
01
10
1.5 ms
11
2.0 ms
5:4
SEQ_CONTROL
00
W/CLR
Code
00
Initialize Power Up or Power Down
Default
01
Starts an LDO power up sequence.
Starts an LDO shutdown sequence.
Bit configuration is ignored.
State of Sequence
10
11
3
SEQ_ON
0
Read
Read
Code
0
Indicates that the sequencing is not in process.
Indicates that the sequencing is executing and somewhere
between the start of slot 1 and the end of slot 7. The bit
remains a 1 until slot 7 has completed at start−up or slot 1 has
finished at shutdown, regardless of what slots are used.
1
2:0
SEQ_COUNT
000
Code
000
001
010
011
100
101
110
111
Present Slot
Indicates sequencing has completed or not started.
Indicates was in slot 1 during register read.
Indicates was in slot 2 during register read.
Indicates was in slot 3 during register read.
Indicates was in slot 4 during register read.
Indicates was in slot 5 during register read.
Indicates was in slot 6 during register read.
Indicates was in slot 7 during register read.
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FAN53870, FAN53871
Table 22. REGISTER DETAILS − 0x10 DISCHARGE
0x10 DISCHARGE
Default = 01111111
Description
Bit
7
Name
Default
Type
UNUSED
LDO1_DIS
6
1
R/W
Code
Discharge Enabled/Disabled
0
LDO1 Active Discharge feature is disabled. Pull−down will not
be activated when LDO1 is disabled by any event.
1
LDO1 Active Discharge feature is enabled. Pull−down will be
activated when LDO1 is disabled by RESET_B going low or
LDO1_EN = 0 or a sequenced shutdown or in an UVP event.
5
4
3
2
1
0
LDO2_DIS
LDO3_DIS
LDO4_DIS
LDO5_DIS
LDO6_DIS
LDO7_DIS
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Code
Discharge Enabled/Disabled
0
LDO2 Active Discharge feature is disabled. Pull−down will not
be activated when LDO2 is disabled by any event.
1
LDO2 Active Discharge feature is enabled. Pull−down will be
activated when LDO2 is disabled by RESET_B going low or
LDO2_EN = 0 or a sequenced shutdown or in an UVP event.
Code
Discharge Enabled/Disabled
0
LDO3 Active Discharge feature is disabled. Pull−down will not
be activated when LDO3 is disabled by any event.
1
LDO3 Active Discharge feature is enabled. Pull−down will be
activated when LDO3 is disabled by RESET_B going low or
LDO3_EN = 0 or a sequenced shutdown or in an UVP event.
Code
Discharge Enabled/Disabled
0
LDO4 Active Discharge feature is disabled. Pull−down will not
be activated when LDO4 is disabled by any event.
1
LDO4 Active Discharge feature is enabled. Pull−down will be
activated when LDO4 is disabled by RESET_B going low or
LDO4_EN = 0 or a sequenced shutdown or in an UVP event.
Code
Discharge Enabled/Disabled
0
LDO5 Active Discharge feature is disabled. Pull−down will not
be activated when LDO5 is disabled by any event.
1
LDO5 Active Discharge feature is enabled. Pull−down will be
activated when LDO5 is disabled by RESET_B going low or
LDO5_EN = 0 or a sequenced shutdown or in an UVP event.
Code
Discharge Enabled/Disabled
0
LDO6 Active Discharge feature is disabled. Pull−down will not
be activated when LDO6 is disabled by any event.
1
LDO6 Active Discharge feature is enabled. Pull−down will be
activated when LDO6 is disabled by RESET_B going low or
LDO6_EN = 0 or a sequenced shutdown or in an UVP event.
Code
Discharge Enabled/Disabled
0
LDO7 Active Discharge feature is disabled. Pull−down will not
be activated when LDO7 is disabled by any event.
1
LDO7 Active Discharge feature is enabled. Pull−down will be
activated when LDO7 is disabled by RESET_B going low or
LDO7_EN = 0 or a sequenced shutdown or in an UVP event.
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FAN53870, FAN53871
Table 23. REGISTER DETAILS − 0x11 RESET
0x11 RESET
Default = 00000110
Description
Bit
Name
Default
Type
7:4
SOFT_RESET
0000
Write
Code
Software Reset
1011
Writing a ”1011” begins a soft reset of the device I2C registers
to their default values. This bit is cleared upon the execution
of the reset function.
Any other value than “1011” will be ignored.
3
UNUSED
2:1
OCP_TIMER
11
R/W
Option bits to control the length of the deglitch timer for current limit on all
LDOs before a fault is triggered.
Code
00
Deglitch Timer
125 ms
01
250 ms
10
500 ms
1 ms
11
0
FLT_SD_B
0
R/W
Code
0
Prevents Shutdown when a Fault Occurs
LDO shuts down if a UVP or OCP event occurs or if the
LDO’s input VIN12, VIN34, VIN5, VIN6 or VIN7 have a UVLO
event.
1
LDO does not shut down if a UVP or OCP event occurs. If the
LDO’s input VIN12, VIN34, VIN5, VIN6 or VIN7 have a UVLO
event, the associated LDO will shut down until the supply
returns, but the fault will not be counted.
NOTE: If this bit function is desired, FLT_SD_B should be set to ”1” prior to
enabling any LDOs after a Power−On−Reset.
Table 24. REGISTER DETAILS − 0x12 I2C_ADDR
0x12 I2C_ADDR
Default = 00000000
Description
Bit
7:2
1:0
Name
UNUSED
Default
Type
2
I2C_ADDR_SEL
01
R/W
Code
00
I C Address Settings
0x20
0x35
0x61
0x72
01
10
11
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FAN53870, FAN53871
Table 25. REGISTER DETAILS − 0x13 LDO_COMP0
0x13 LDO_COMP0
Default = 00000101
Description
Bit
Name
Default
00
Type
7:6
LDO4_COMP_SEL
R/W
The LDO4 Compensation is selected by modifying these bits to account
for different COUT values.
The Cout_min and Cout_max values are nominal 0DCV bias capacitance
values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
<4.7 mF
<15 mF
<47 mF
NA
01
10
11
NA
5:4
LDO3_COMP_SEL
00
R/W
The LDO3 Compensation is selected by modifying these bits to account
for different COUT value.
The Cout_min and Cout_max values are nominal 0DCV bias capacitance
values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
<4.7 mF
<15 mF
<47 mF
NA
01
10
11
NA
3:2
LDO2_COMP_SEL
01
R/W
The LDO2 Compensation is selected by modifying these bits to account
for different COUT value.
Code
00
COUT_MIN
−
COUT_MAX
<5.5 mF
<17 mF
<34 mF
−
01
5.5 mF
17 mF
34 mF
10
11
1:0
LDO1_COMP_SEL
01
R/W
The LDO1 Compensation is selected by modifying these bits to account
for different COUT value.
Code
00
COUT_MIN
−
COUT_MAX
<5.5 mF
<17 mF
<34 msF
−
01
5.5 mF
17 mF
34 mF
10
11
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FAN53870, FAN53871
Table 26. REGISTER DETAILS − 0x14 LDO_COMP1
0x14 LDO_COMP1
Default = 00000000
Description
Bit
7:6
5:4
Name
UNUSED
Default
Type
LDO7_COMP_SEL
00
00
00
R/W
The LDO7 Compensation is selected by modifying these bits to account
for different COUT value.
The Cout_min and Cout_max values are nominal 0DCV bias capacitance
values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
<4.7 mF
<15 mF
<47 mF
NA
01
10
11
NA
3:2
LDO6_COMP_SEL
R/W
The LDO6 Compensation is selected by modifying these bits to account
for different COUT value.
The Cout_min and Cout_max values are nominal 0DCV bias capacitance
values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
<4.7 mF
<15 mF
<47 mF
NA
01
10
11
NA
1:0
LDO5_COMP_SEL
R/W
The LDO5 Compensation is selected by modifying these bits to account
for different COUT value.
The Cout_min and Cout_max values are nominal 0DCV bias capacitance
values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
<4.7 mF
<15 mF
<47 mF
NA
01
10
11
NA
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46
FAN53870, FAN53871
Table 27. REGISTER DETAILS − 0x15 INTERRUPT1
0x15 INTERRUPT1
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
6
LDO7_UVP_INT
0
0
0
0
0
0
0
R/CLR
Code
LDO7 UVP Interrupt
0
Clear
1
Under−Voltage event occurred on LDO7 output.
5
4
3
2
1
0
LDO6_UVP_INT
LDO5_UVP_INT
LDO4_UVP_INT
LDO3_UVP_INT
LDO2_UVP_INT
LDO1_UVP_INT
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
Code
LDO6 UVP Interrupt
0
Clear
1
Under−Voltage event occurred on LDO6 output.
Code
LDO5 UVP Interrupt
0
Clear
Under−Voltage event occurred on LDO5 output.
LDO4 UVP Interrupt
1
Code
0
Clear
1
Under−Voltage event occurred on LDO4 output.
LDO3 UVP Interrupt
Code
0
Clear
1
Under−Voltage event occurred on LDO3 output.
LDO2 UVP Interrupt
Code
0
Clear
1
Code
0
Under−Voltage event occurred on LDO2 output.
LDO1 UVP Interrupt
Clear
1
Under−Voltage event occurred on LDO1 output.
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47
FAN53870, FAN53871
Table 28. REGISTER DETAILS − 0x16 INTERRUPT2
0x16 INTERRUPT2
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
6
LDO7_OCP_INT
0
0
0
0
0
0
0
R/CLR
Code
LDO7 OCP Interrupt
0
Clear
1
Over−Current event detected on LDO7 output.
5
4
3
2
1
0
LDO6_OCP_INT
LDO5_OCP_INT
LDO4_OCP_INT
LDO3_OCP_INT
LDO2_OCP_INT
LDO1_OCP_INT
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
Code
LDO6 OCP Interrupt
0
Clear
Over−Current event detected on LDO6 output.
LDO5 OCP Interrupt
1
Code
0
Clear
1
Over−Current event detected on LDO5 output.
LDO4 OCP Interrupt
Code
0
Clear
1
Over−Current event detected on LDO4 output.
LDO3 OCP Interrupt
Code
0
Clear
1
Over−Current event detected on LDO3 output.
LDO2 OCP Interrupt
Code
0
Clear
1
Code
0
Over−Current event detected on LDO2 output.
LDO1 OCP Interrupt
Clear
1
Over−Current event detected on LDO1 output.
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48
FAN53870, FAN53871
Table 29. REGISTER DETAILS − 0x17 INTERRUPT3
0x17 INTERRUPT3
Default = 00000000
Description
Bit
Name
Default
Type
7
TSD_INT
0
0
0
R/CLR
Code
Thermal Shutdown Interrupt
Clear
0
1
A Thermal Shutdown event detected or that the temperature has fallen
below the hysteresis level.
6
5
TSD_WRN_INT
R/CLR
R/CLR
Code
Thermal Warning Interrupt
0
1
Clear
Thermal Shutdown Warning threshold was surpassed or that the
temperature has fallen below the hysteresis level.
VSYS_UVLO_INT
Code
VSYS Under−Voltage−Lock−Out Interrupt
0
1
Clear
VSYS fell below the UVLO falling threshold or that VSYS have risen above
the UVLO rising threshold after a UVLO fault.
Reading the the associated status bit provides present state of the input voltage.
4
3
2
1
LDO7_UVLO_INT
LDO6_UVLO_INT
LDO5_UVLO_INT
LDO34_UVLO_INT
0
0
0
0
R/CLR
R/CLR
R/CLR
R/CLR
Code
VIN7 Under−Voltage−Lock−Out Interrupt
0
1
Clear
VIN7 fell below the UVLO falling threshold while LDO7 was enabled or that
VIN7 has risen above the UVLO rising threshold after a UVLO fault.
Reading the associated status bit provides present state of the input voltage.
Code
VIN6 Under−Voltage−Lock−Out Interrupt
0
1
Clear
VIN6 fell below the UVLO falling threshold while LDO6 was enabled or that
VIN6 has risen above the UVLO rising threshold after a UVLO fault.
Reading the associated status bit provides present state of the input voltage.
Code
VIN5 Under−Voltage−Lock−Out Interrupt
0
1
Clear
VIN5 fell below the UVLO falling threshold while LDO5 was enabled or that
VIN5 has risen above the UVLO rising threshold after a UVLO fault.
Reading the associated status bit provides present state of the input voltage.
Code
VIN34 Under−Voltage−Lock−Out Interrupt
0
1
Clear
VIN34 fell below the UVLO falling threshold while LDO3 and/or LDO4 were
enabled or that VIN34 has risen above the rising UVLO thresholds after a
UVLO fault.
Reading the associated status bit provides present state of the input voltage.
0
LDO12_UVLO_INT
0
R/CLR
Code
VIN12 Under−Voltage−Lock−Out Interrupt
0
1
Clear
VIN12 fell below the UVLO falling threshold while LDO1 and/or LDO2 were
enabled or that VIN12 has risen above the UVLO rising threshold after a
UVLO fault.
Reading the associated status bit provides present state of the input voltage.
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49
FAN53870, FAN53871
Table 30. REGISTER DETAILS − 0x18 STATUS1
0x18 STATUS1
Name
Default = 00000000
Description
Bit
7
Default
Type
UNUSED
6
LDO7_UVP_STAT
0
Read
Code
LDO7 UVP Status
0
Normal Operation
An Under−Voltage condition exists on LDO7 output.
LDO6 UVP Status
1
5
4
3
2
1
0
LDO6_UVP_STAT
LDO5_UVP_STAT
LDO4_UVP_STAT
LDO3_UVP_STAT
LDO2_UVP_STAT
LDO1_UVP_STAT
0
0
0
0
0
0
Read
Read
Read
Read
Read
Read
Code
0
Normal Operation
1
An Under−Voltage condition exists on LDO6 output.
LDO5 UVP Status
Code
0
Normal Operation
1
An Under−Voltage condition exists on LDO5 output.
LDO4 UVP Status
Code
0
Normal Operation
1
An Under−Voltage condition exists on LDO4 output.
LDO3 UVP Status
Code
0
Normal Operation
1
An Under−Voltage condition exists on LDO3 output.
LDO2 UVP Status
Code
0
Normal Operation
1
Code
0
An Under−Voltage condition exists on LDO2 output.
LDO1 UVP Status
Normal Operation
1
An Under−Voltage condition exists on LDO1 output.
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50
FAN53870, FAN53871
Table 31. REGISTER DETAILS − 0x19 STATUS2
0x19 STATUS2
Name
Default = 00000000
Description
Bit
7
Default
Type
UNUSED
6
LDO7_OCP_STAT
0
Read
Code
LDO7 OCP Status
0
Normal Operation
An Over−Current condition exists on LDO7 output.
LDO6 OCP Status
1
5
4
3
2
1
0
LDO6_OCP_STAT
LDO5_OCP_STAT
LDO4_OCP_STAT
LDO3_OCP_STAT
LDO2_OCP_STAT
LDO1_OCP_STAT
0
0
0
0
0
0
Read
Read
Read
Read
Read
Read
Code
0
Normal Operation
1
An Over−Current condition exists on LDO6 output.
LDO5 OCP Status
Code
0
Normal Operation
1
An Over−Current condition exists on LDO5 output.
LDO4 OCP Status
Code
0
Normal Operation
1
An Over−Current condition exists on LDO4 output.
LDO3 OCP Status
Code
0
Normal Operation
1
An Over−Current condition exists on LDO3 output.
LDO2 OCP Status
Code
0
Normal Operation
1
Code
0
An Over−Current condition exists on LDO2 output.
LDO1 OCP Status
Normal Operation
1
An Over−Current condition exists on LDO1 output.
www.onsemi.com
51
FAN53870, FAN53871
Table 32. REGISTER DETAILS − 0x1A STATUS3
0x1AB STATUS3
Default = 00000000
Description
Bit
Name
Default
Type
7
TSD_STAT
0
Read
Code
Thermal Shutdown Status
Normal Operation
0
1
Code
0
Device is in Thermal Shutdown.
Thermal Warning Status
Normal Operation
6
TSD_WRN_STAT
0
Read
1
The temperature is above the Thermal Warning
level and shutdown is impending.
5
4
VSYS_UVLO_STAT
LDO7_UVLO_STAT
0
0
Read
Read
Code
VSYS Under−Voltage−Lock−Out Status
Normal Operation
0
1
Code
0
VSYS is below the UVLO threshold.
VIN7 Under−Voltage−Lock−Out Status
Normal Operation
1
VIN7 is below the UVLO threshold while LDO7 is
enabled.
3
2
1
0
LDO6_UVLO_STAT
LDO5_UVLO_STAT
LDO34_UVLO_STAT
LDO12_UVLO_STAT
0
0
0
0
Read
Read
Read
Read
Code
VIN6 Under−Voltage−Lock−Out Status
0
1
Normal Operation
VIN6 is below the UVLO threshold while LDO6 is
enabled.
Code
VIN5 Under−Voltage−Lock−Out Status
0
1
Normal Operation
VIN5 is below the UVLO threshold while LDO5 is
enabled.
Code
VIN34 Under−Voltage−Lock−Out Status
0
1
Normal Operation
VIN34 is below the UVLO threshold while LDO3
and/or LDO4 are enabled.
Code
VIN12 Under−Voltage−Lock−Out Status
0
1
Normal Operation
VIN12 is below the UVLO threshold while LDO1
and/or LDO2 are enabled.
www.onsemi.com
52
FAN53870, FAN53871
Table 33. REGISTER DETAILS − 0x1B STATUS4
0x1B STATUS4
Name
Default = 00000000
Description
Bit
Default
Type
6
CHIP_SUSD
0
Read
Code
Chip Suspension
0
1
Chip in normal state
The entire chip has been suspended due to a global
fault condition.
6
5
4
3
2
1
0
LDO7_SUSD
LDO6_SUSD
LDO5_SUSD
LDO4_SUSD
LDO3_SUSD
LDO2_SUSD
LDO1_SUSD
0
0
0
0
0
0
0
Read
Read
Read
Read
Read
Read
Read
Code
LDO7 Output Suspended
LDO7 in normal state
0
1
LDO7 has been suspended due to a fault condition.
LDO6 Output Suspended
Code
0
LDO6 in normal state
1
LDO6 has been suspended due to a fault condition.
LDO5 Output Suspended
Code
0
LDO5 in normal state
1
LDO5 has been suspended due to a fault condition.
LDO4 Output Suspended
Code
0
LDO4 in normal state
1
LDO4 has been suspended due to a fault condition.
LDO3 Output Suspended
Code
0
LDO3 in normal state
1
LDO3 has been suspended due to a fault condition.
LDO2 Output Suspended
Code
0
LDO2 in normal state
1
Code
0
LDO2 has been suspended due to a fault condition.
LDO1 Output Suspended
LDO1 in normal state
1
LDO1 has been suspended due to a fault condition.
www.onsemi.com
53
FAN53870, FAN53871
Table 34. REGISTER DETAILS − 0x1C MINT1
0x1C MINT1
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
6
MASK_LDO7_UVP
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Code
LDO7 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO7
Under−Voltage interrupt occurs.
5
4
3
2
1
0
MASK_LDO6_UVP
MASK_LDO5_UVP
MASK_LDO4_UVP
MASK_LDO3_UVP
MASK_LDO2_UVP
MASK_LDO1_UVP
0
0
0
0
0
0
Code
LDO6 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO6
Under−Voltage interrupt occurs.
Code
LDO5 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO5
Under−Voltage interrupt occurs.
Code
LDO4 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO4
Under−Voltage interrupt occurs.
Code
LDO3 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO3
Under−Voltage interrupt occurs.
Code
LDO2 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO2
Under−Voltage interrupt occurs.
Code
LDO1 UVP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO1
Under−Voltage interrupt occurs.
www.onsemi.com
54
FAN53870, FAN53871
Table 35. REGISTER DETAILS − 0x1D MINT2
0x1D MINT2
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
6
MASK_LDO7_OCP
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Code
LDO7 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO7
Over−Current interrupt occurs
5
4
3
2
1
0
MASK_LDO6_OCP
MASK_LDO5_OCP
MASK_LDO4_OCP
MASK_LDO3_OCP
MASK_LDO2_OCP
MASK_LDO1_OCP
0
0
0
0
0
0
Code
LDO6 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO6
Over−Current interrupt occurs
Code
LDO5 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO5
Over−Current interrupt occurs
Code
LDO4 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO4
Over−Current interrupt occurs
Code
LDO3 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO3
Over−Current interrupt occurs
Code
LDO2 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO2
Over−Current interrupt occurs
Code
LDO1 OCP MASK
0
1
No masking of interrupt
INT pin will not change states when LDO1
Over−Current interrupt occurs
www.onsemi.com
55
FAN53870, FAN53871
Table 36. REGISTER DETAILS − 0x1E MINT3
0x1E MINT3
Default = 00000000
Description
Bit
Name
Default
Type
7
MASK_TSD
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Code
Thermal Shutdown MASK
No masking of interrupt
0
1
INT pin will not change states when a Thermal
Shutdown interrupt occurs.
6
5
4
3
2
1
0
MASK_TSD_WRN
MASK_VSYS_UVLO
MASK_LDO7_UVLO
MASK_LDO6_UVLO
MASK_LDO5_UVLO
MASK_LDO34_UVLO
MASK_LDO12_UVLO
0
0
0
0
0
0
0
Code
Thermal Warning MASK
0
1
No masking of interrupt
INT pin will not change states when a Thermal
Warning interrupt occurs.
Code
VSYS UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VSYS Input
Power Under−Voltage interrupt occurs.
Code
LDO7 UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VIN7 Input
Power Under−Voltage interrupt occurs.
Code
VIN6 UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VIN6 Input
Power Under−Voltage interrupt occurs.
Code
VIN5 UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VIN5 Input
Power Under−Voltage interrupt occurs.
Code
VIN34 UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VIN34 Input
Power Under−Voltage interrupt occurs.
Code
VIN12 UVLO MASK
0
1
No masking of interrupt
INT pin will not change states when VIN12 Input
Power Under−Voltage interrupt occurs.
www.onsemi.com
56
FAN53870, FAN53871
APPLICATION GUIDELINES
LDO Input Capacitor Considerations
to ensure optimum performance and stability, specify the
amount of capacitance each LDO output will have with an
onsemi representative.
Use only X5R and X7R ceramic capacitors with adequate
voltage rating for the output capacitors.
If long wires are used to bring power to an evaluation
board, additional “bulk” capacitance (electrolytic or
tantalum) should be placed (on the evaluation board)
between C and the power source lead to reduce ringing
IN
that can occur between the inductance of the power source
PCB Layout Recommendations
leads and C . Use only X5R and X7R ceramic capacitors
IN
Input and output capacitors should be placed as close to
the associated power pin. The ground terminal of the
capacitor should be connected to a good ground plane −
preferably on the surface of the board. Input power should
be routed to the input capacitor first and then to the input pin
of the IC. For power from layers other than the layer on
which the capacitor sits, should be routed to the capacitor
layer with vias in pad or close to the positive terminal of the
capacitor. Power traces from the LDO output should be
routed to the output capacitor first and then to (if necessary)
other layers.
with adequate voltage rating for the input capacitors.
The effective capacitance value decreases as the voltage
across the capacitor increases due to DC bias effects. Adding
additional capacitance to the minimum recommended
ensures reliable operation.
LDO Output Capacitor Considerations
FAN53870 LDOs are initially set at the factory for a range
of 5.5 to 17 mF (unbiased) on LDO1 and LDO2, and a range
of 1.0 to 4.7 mF (unbiased) on LDO3−7. All LDOs can be
trimmed at the factory for up to 47 mF total (unbiased)
capacitance. When evaluating and ordering the FAN53870,
0201
0201
0201
0402
VIN6
A1
VIN7
LDO7
A3
LDO2
A4
VIN12
A5
0201
A2
LDO6
B1
INT
B2
SDA
B3
SCL
B4
LDO1
B5
LDO4
C1
AGND
C2
AGND RESET_B VREF
C3
VSYS
D3
C4
VIN5
D4
C5
LDO5
D5
LDO3
D1
VIN34
D2
0201
0201
0201
0201
Figure 31. Recommended PCB Assembly (Top View)
www.onsemi.com
57
FAN53870, FAN53871
Figure 32. Recommended PCB Layout
www.onsemi.com
58
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP20 1.61x1.96x0.432
CASE 567YA
ISSUE O
DATE 02 JUL 2019
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON08754H
WLCSP20 1.61x1.96x0.432
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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