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April 2015

FAN54053

High Efficiency, 1.55 A, Li-Ion Switching Charger with

Power Path, USB-OTG, in a Small Solution Footprint

Features

Description

.

Fully Integrated, High-Efficiency Switch-Mode Charger

for Single-Cell Li-Ion and Li-Polymer Batteries

The FAN54053 is a 1.55 A USB-compliant switch-mode

charger featuring power path operation, USB OTG boost

support, JEITA temperature control, and production test mode

support, in a small 25 bump, 0.4 mm pitch WLCSP package.

.

Power Path Circuit Ensures Fast System Startup with a

Dead Battery when VBUS is Connected

To facilitate fast system startup, the IC includes a power

path circuit, which disconnects the battery from the system

rail, ensuring that the system can power up quickly following

a VBUS connection. The power path circuit ensures that the

system rail stays up when the charger is plugged in, even if

the battery is dead or shorted.

.

1.55 A Maximum Charge Current

Programmable High Accuracy Float Voltage:

0.5% at 25°C

1% from 0 to 125°C

.

5% Input and Charge Current Regulation Accuracy

Temperature-Sense Input for JEITA Compliance

Thermal Regulation and Shutdown

4.2 V at 2.3 A Production Test Support

5 V, 500 mA Boost Mode for USB OTG

28 V Absolute Maximum Input Voltage

6 V Maximum Input Operating Voltage

The charging parameters; float voltage, input voltage

regulation, input current, charging current, and other

operating modes are programmable through an I²C Interface

that operates up to 3.4 Mbps. The charger and boost

regulator circuits switch at 3 MHz to minimize the size of

external passive components.

The FAN54053 provides battery charging in three phases:

conditioning, constant current and constant voltage. The IC

automatically restarts the charge cycle when the battery falls

below a voltage threshold. If the input source is removed, the

IC enters a high-impedance mode blocking battery current

from leaking to the input. Charge status is reported back to

the host through the I²C port.

Programmable through High-Speed I²C Interface

(3.4 Mb/s) with Fast Mode Plus Compatibility

Input Current

Fast-Charge / Termination Current

Float Voltage

Dynamic input voltage control prevents a weak adapter’s

voltage from collapsing, ensuring charging capability from

such adapters.

Termination Enable

.

3 MHz Synchronous Buck PWM Controller with

Wide Duty Cycle Range

The FAN54053 is available in a space saving 2.4 mm x

2.0 mm WLCSP package.

.

Small Footprint 1 H External Inductor

Safety Timer with Reset Control

VBUS

C_BUS

L1

SW

Dynamic Input Voltage Control

SYS

C_SYS

PGND

Very Low Battery Current when Charger Inactive

Q5

PMID

GATE

SYSTEM

LOAD

Applications

External

PMOS

C_MID

.

Cell Phones, Smart Phones, PDAs

FAN54053

VBAT

POK_B

SDA

Tablet, Portable Media Players

Gaming Device, Digital Cameras

C_BAT

NTC

REF

R_REF

SCL

DIS

BATTERY

C_REF

STAT

AGND

+

T

All trademarks are the property of their respective owners.

Figure 1.

Typical Application

www.fairchildsemi.com

FAN54053 • Rev. 1.4

Ordering Information

Temperature

PN Bits:

IC_INFO[5:3]

Part Number

Package

Packing Method

Range

25-Bump, Wafer-Level Chip-Scale

Package (WLCSP), 0.4 mm Pitch

FAN54053UCX

-40 to 85°C

010

Tape and Reel

Table 1. Feature Summary

Battery Absent

Watchdog

Timer Default

Part Number

Slave Address Automatic Charge

E1 Pin

Behavior

FAN54053

1101011

No

On

POK_B

Disabled

Block Diagram

VBUS

PMID

SW

Q3

C_BUS

Q1

C_MID

Q1A

Q1B

PGND

CHARGE

PUMP

L1

IBUS &

VBUS

CONTROL

30mA

AGND

C_SYS

PWM

MODULATOR

Q2

SYS

SYSTEM

LOAD

VBUS OVP

POWER OK

PGND

Q5

GATE

External

PMOS

Q4

CC and CV

Battery

Charger

Q4A

Q4B

POK_B

SDA

I2C INTERFACE

VBAT

NTC

SCL

C_BAT

LOGIC AND CONTROL

DIS

TEMP

SENSE

R_REF

STAT

REF

C_REF

BATTERY

+

T

PMID

Greater than V_BAT

Less than V_BAT

Q1A

ON

Q1B

OFF

ON

SYS

Greater than V_BAT

Less than V_BAT

Q4A

ON

Q4B

OFF

ON

OFF

Figure 2.

IC and System Block Diagram

Table 2. Recommended External Components

Component

Description

Vendor

Parameter

Typ.

Unit

L

1.0

48

H

Toko DFE201610E-1R0M

L1

1 H, 20%, 2.7 A, 2016

or Equivalent

DCR (Series R)

m

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C_BAT,C_SYS

C_MID

C

10

4.7

1.0

10 F, 20%, 6.3 V, X5R, 0603

4.7 F, 10%, 10 V, X5R, 0603

1.0 F, 10%, 25 V, X5R, 0603

F

Murata: GRM188R61A475K

TDK: C1608X5R1A475K

C⁽¹⁾

C

Murata GRM188R61E105K

TDK:C1608X5R1E105M

C_BUS,

Q5

C_REF

Fairchild FDMA905P

R_DS(ON)

C

16

PMOS,12 V, 16 m, MLP2x2

1 F, 10%, 6.3 V, X5R, 0402

m

F

1.0

Note:

1. 10 V rating is sufficient for C_MIDsince PMID is protected from over-voltage surges on VBUS by Q3.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

2

Pin Configuration

SDA PGND SW

PMID VBUS

A5

B5

C5

D5

E5

A4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

A1

A2

B2

C2

D2

A3

B3

C3

A4

B4

C4

A5

SCL

B1

B4

B5

DIS

C1

GATE

C5

C4

D4

STAT

D1

SYS VBAT NTC

D3

D4

D5

POK_B AGND

REF

E5

E4

E1

E2

E3

E4

Figure 3.

Top View

Figure 4.

Bottom View

Pin Definitions

Pin #

A1

Name

SDA

Description

I²C Interface Serial Data. This pin should not be left floating.

I²C Interface Serial Clock. This pin should not be left floating.

B1

SCL

Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and

the PWM converter is disabled.

C1

D1

DIS

Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in

progress; can be used to signal the host processor when a fault condition occurs.

STAT

Power OK. Open-drain output that pulls LOW when VBUS is plugged in and the battery has risen

E1

POK_B above V_LOWV. This signal is used to signal the host processor that it can begin to draw significant

current.

Power Ground. Power return for gate drive and power transistors. The connection from this pin to the

bottom of C_MIDshould be as short as possible.

A2 – D2

PGND

E2

AGND

SW

Analog Ground. All IC signals are referenced to this node.

Switching Node. Connect to output inductor.

A3 – C3

System Supply. Output voltage of the switching charger and input to the power path controller. Bypass

SYS to PGND with a 10 μF capacitor.

D3 – E3

A4 – C4

SYS

Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense.

Bypass with a minimum of a 4.7 F, 6.3 V capacitor to PGND.

PMID

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor

to PGND. VBAT is a power path connection.

D4 – E4

A5 – B5

VBAT

VBUS

Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND.

External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used

to augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS

and the drain should be connected to VBAT.

C5

GATE

Thermistor input. The IC compares this node with taps on a resistor divider from REF to inhibit auto-

charging when the battery temperature is outside of permitted fast-charge limits.

D5

E5

NTC

REF

Reference Voltage. REF is a 1.8 V regulated output.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

Continuous

-0.3

-1.0

–0.3

V_BUS

Voltage on VBUS Pin

28.0

V

Pulsed, 100 ms Maximum Non-Repetitive

Voltage on PMID Voltage Pin

7.0

6.5⁽²⁾

V_I

V

Voltage on SW, SYS, VBAT, STAT, DIS Pins

Voltage on Other Pins

V_O

dV_BUS

dt

Maximum V_BUSSlope Above 5.5 V when Boost or Charger Active

4

V/s

Human Body Model per JESD22-A114

Charged Device Model per JESD22-C101

2000

500

15

Electrostatic Discharge

Protection Level

V

ESD

Air Gap

Contact

USB Connector

Pins (V_BUSto GND)

IEC 61000-4-2 System ESD⁽³⁾

kV

8

T_J

T_STG

Junction Temperature

Storage Temperature

–40

–65

+150

+260

°C

T_L

Lead Soldering Temperature, 10 Seconds

Notes:

2. Lesser of 6.5 V or V_I+ 0.3 V.

3. Guaranteed if C_BUS≥1 µF and C_MID≥ 4.7 µF.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to absolute maximum ratings.

Symbol

Parameter

Min.

Max.

Unit

V

V_BUS

Supply Voltage

4

6

4.5

4

V_BAT(MAX)Maximum Battery Voltage when Boost enabled

V

T_A< 60°C

T_A> 60°C

dV_BUS

dt

Negative VBUS Slew Rate during VBUS Short Circuit,

C_MID< 4.7 F, see VBUS Short While Charging



V/s

2

T_A

T_J

Ambient Temperature

–30

+85

+120

°C

Junction Temperature (see Register Bit section)

Thermal Properties

Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer

2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature

T_J(max)at a given ambient temperature T_A.

Symbol

Parameter

Junction-to-Ambient Thermal Resistance

Junction-to-PCB Thermal Resistance

Typical

50

Unit

°C/W

_JA

_JB

20

www.fairchildsemi.com

FAN54053 • Rev. 1.4

4

Electrical Specifications

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE=“0”; OPA_MODE=“0” (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C. Min.

and Max. values are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Supplies

PWM Switching

25

6

mA

V_BAT> V_OREG

I_BUSLIM= 500 mA

I_VBUS

VBUS Current

0°C < T_J< 85°C, HZ_MODE = “1”,

V_BAT> V_LOWV

190

280

10

A

Battery Discharge Current in DIS pin HIGH, or HZ_MODE = “1”,

I_{BAT_HZ}

<1.25

High-Impedance Mode

V_BAT=4.35 V

Battery Leakage Current to

V_BUSin High-Impedance

Mode

DIS pin HIGH, or HZ_MODE = “1”,

V_BUSShorted to Ground, V_BAT=4.35 V

I_{BUS_HZ}

-5.0

-0.2

A

Charger Voltage Regulation

Charge Voltage Range

3.51

–0.5

–1

4.45

+0.5

+1

V

%

V_OREG

T_A= 25°C, V_OREG= 4.35 V

T_J=0 to 125°C

Charge Voltage Accuracy

Charging Current Regulation (Fast Charge)

IO_LEVEL = “0”

550

165

–5

1550

230

+5

mA

%

Output Charge Current

Range

V_LOWV< V_BAT

V_OREG

<

I_OCHRG

IO_LEVEL = “1” (default)

200

Charge Current Accuracy

IO_LEVEL = “0”

Weak Battery Detection

Weak Battery Threshold

Range

3.35

3.75

+5

V

V_LOWV

Weak Battery Threshold

Accuracy

–5

%

Weak Battery Deglitch Time Rising Voltage, 2 mV Overdrive

PWM Charging Threshold

Rising PWM Charging

32

ms

V_BATMIN

3.1

3.2

3.0

3.3

V

Threshold

Falling PWM Charging

Threshold

V_BATFALL

Logic Levels: DIS, SDA, SCL

V_IH

V_IL

I_IN

High-Level Input Voltage

1.05

V

Low-Level Input Voltage

Input Bias Current

0.4

Input Tied to GND or V_BUS

0.01

1

1.00

A

M

R_PD

DIS Pull-Down Resistance

Charge Termination Detection

Termination Current Range

V_BAT> V_OREG– V_RCH, V_BUS> V_SLP

I_TERMSetting < 100 mA

50

–15

–5

400

+15

+5

mA

%

Termination Current

Accuracy

I_(TERM)

I_TERMSetting > 200 mA

Termination Current Deglitch

Time⁽⁴⁾

32

ms

www.fairchildsemi.com

FAN54053 • Rev. 1.4

5

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE=“0”; OPA_MODE=“0” (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C. Min.

and Max. values are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Power Path (Q4) Control (Precharge)

IO_LEVEL = “1” (default)

165

375

610

–6

200

450

730

–5

235

520

840

–3

mA

mV

IO_LEVEL = “0”, I_BUSLIM< “01”

Power Path Maximum

Charge Current

I_PP

IO_LEVEL = “0”, I_BUSLIM> “01”, I_OCHARGE< “02”

IO_LEVEL = “0”, I_BUSLIM> “01”, I_OCHARGE> “02”

(SYS-VBAT) Falling

VBAT to SYS Threshold

V_THSYS

for Q4 and Gate Transition

While Charging

(SYS-VBAT) Rising

-1

+1

2

mV

Production Test Mode

Production Test Output

Voltage

(4)

V_BAT(PTM)

1 mA < I_BAT< 2 A, V_BUS=5.5 V

4.116 4.200 4.284

2.3

V

A

Production Test Output

Current

(4)

I_BAT(PTM)

20% Duty with Max. Period 10 ms

Battery Temperature Monitor (NTC)

T1 (0°C) Temperature

Threshold

T1

71.9

62.6

31.9

21.3

73.9

64.6

32.9

23.3

75.9

66.6

34.9

25.3

T2 (10°C) Temperature

Threshold

T2

% of

V_REF

T3 (45°C) Temperature

Threshold

T3

T4 (60°C) Temperature

Threshold

T4

Input Power Source Detection

V_IN(MIN)1

VBUS Input Voltage Rising To Initiate and Pass VBUS Validation

4.35

4.45

3.94

V

Minimum VBUS during

During Charging

Charge

V_IN(MIN)2

3.71

30

(4)

t_{VBUS_VALID}

VBUS Validation Time

ms

V_BUSControl Loop

VBUS Loop Setpoint

Accuracy

Input Current Limit

V_BUSLIM

–3

+3

%

I_BUSLIM= “00”

I_BUSLIM= “01”

I_BUSLIM= “10”

450

972

475

760

500

1188

Charger Input Current

Limit Threshold

I_BUSLIM

mA

1080

V_REFBias Generator

Bias Regulator Voltage

Short-Circuit Current Limit

Battery Recharge Threshold

Recharge Threshold

Deglitch Time

STAT, POK_B Output

V_STAT(OL)STAT Output Low

V_BUS> V_IN(MIN)1

1.8

2.5

V

V_REF

mA

Below V_OREG

100

120

130

150

mV

V_RCH

V_BATFalling Below V_RCHThreshold

ms

I_STAT= 10 mA

V_STAT= 5 V

0.4

1

V

STAT High Leakage

Current

I_STAT(OH)

A

www.fairchildsemi.com

FAN54053 • Rev. 1.4

6

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE=”0”; OPA_MODE=”0” (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C. Min.

and Max. values are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min. Typ. Max. Unit

Battery Detection

Battery Detection Current before

Charge Done (Sink Current)⁽⁵⁾

I_DETECT

t_DETECT

–1.9

mA

ms

Begins after Termination Detected and

V_BAT< V_OREG– V_RCH

Battery Detection Time

262

Sleep Comparator

Sleep-Mode Entry Threshold,

V_BUS– V_BAT

Power Switches (see Figure 2)

Q3 On Resistance (VBUS to PMID) I_IN(LIMIT)= 500 mA

V_SLP

2.3 V < V_BAT< V_OREG, V_BUSFalling

0

0.04

0.10

V

180

130

150

70

400

225

100

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

Q4 On Resistance (SYS to VBAT)

mΩ

R_DS(ON)

V_BAT=4.35 V

mΩ

Synchronous to Non-Synchronous

Current Cut-Off Threshold⁽⁶⁾

Low-Side MOSFET (Q2) Cycle-by-Cycle

Current Limit

I_SYNC

180

mA

Charger PWM Modulator

f_SW

Oscillator Frequency

2.7

3.0

0

3.3 MHz

D_MAX

D_MIN

Maximum Duty Cycle

Minimum Duty Cycle

100

%

Boost Mode Operation (OPA_MODE=1)

2.5 V < V_BAT< 4.5 V, I_LOADfrom 0 to

200 mA

4.80

4.77

5.07

5.20

V_BOOST

Boost Output Voltage at VBUS

V

3.0 V < V_BAT< 4.5 V, I_LOADfrom 0 to

500 mA

I_BAT(BOOST)Boost Mode Quiescent Current

PFM Mode, V_BAT= 3.6 V, I_LOAD= 0 A

250

1550

2.32

2.48

350

A

I_LIMPK(BST)

Q2 Peak Current Limit

1350

1950

mA

While Boost Active

Minimum Battery Voltage for Boost

Operation

UVLO_BST

V

To Start Boost Regulator

2.70

VBUS Load Resistance

Normal Operation

VBUS Validation

500

100

k

R_VBUS

VBUS to PGND Resistance



Protection and Timers

VBUS Over-Voltage Shutdown

V_BUSRising

V_BUSFalling

6.09

1.95

6.29

100

6.49

2.07

V

VBUS_OVP

I_LIMPK(CHG)

V_SHORT

I_SHORT

Hysteresis

mV

Q1 Cycle-by-Cycle Peak Current

Limit

Charge Mode

V_BATRising

3

A

Battery Short-Circuit Threshold

Hysteresis

2.00

100

V

mV

Linear Charging Current

V_BAT< V_SHORT

30

mA

Thermal Shutdown Threshold⁽⁴⁾

Hysteresis⁽⁴⁾

T_JRising

145

25

T_SHUTDWN

°C

T_JFalling

T_CF

t_INT

Thermal Regulation Threshold⁽⁴⁾

Charge Current Reduction Begins

120

2.1

°C

s

Detection Interval

www.fairchildsemi.com

FAN54053 • Rev. 1.4

7

Electrical Specifications (Continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T_Jand T_A;

V_BUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for T_J=25°C. Min. and

Max. values are not tested in production, but are determined by characterization.

Symbol

Parameter

32-Second Timer⁽⁷⁾

Conditions

Charger Enabled

Min. Typ. Max. Unit

20.5

18.0

12.0

–23

25.2

13.5

28.0

34.0

t_32S

s

Charger Disabled

15-Minute Mode

Charger Inactive

t_15MIN

15-Minute Timer

15.0 min

27

∆t_LF

Low-Frequency Timer Accuracy

%

Notes:

4. Guaranteed by design; not tested in production.

5. Negative current is current flowing from the battery to VBUS (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below I_SYNC

.

7. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

8

I²C Timing Specifications

Guaranteed by design.

Symbol

Parameter

Conditions

Standard Mode

Min.

Typ. Max.

Unit

100

400

1000

3400

1700

4.7

Fast Mode

f_SCL

SCL Clock Frequency

Fast Mode Plus

kHz

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

BUS-free Time between STOP and

START Conditions

t_BUF

Fast Mode

1.3

s

Fast Mode Plus

0.5

Standard Mode

4

s

ns

s

ns

s

ns

s

ns

Fast Mode

600

260

160

4.7

START or Repeated START Hold

Time

t_HD;STA

Fast Mode Plus

High-Speed Mode

Standard Mode

Fast Mode

1.3

t_LOW

SCL LOW Period

SCL HIGH Period

Fast Mode Plus

0.5

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

160

320

4

Fast Mode

600

260

60

t_HIGH

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

120

4.7

Fast Mode

600

260

160

250

100

50

t_SU;STA

Repeated START Setup Time

Data Setup Time

Fast Mode Plus

High-Speed Mode

Standard Mode

Fast Mode

t_SU;DAT

ns

Fast Mode Plus

High-Speed Mode

Standard Mode

10

0

3.45

900

450

70

s

ns

Fast Mode

t_HD;DAT

Data Hold Time

SCL Rise Time

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

150

20+0.1C_B

10

20

1000

300

120

80

Fast Mode

t_RCL

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

160

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FAN54053 • Rev. 1.4

9

I²C Timing Specifications (Continued)

Guaranteed by design.

Symbol

Parameter

Conditions

Standard Mode

Min.

20+0.1C_B

10

Typ. Max.

Unit

300

120

40

Fast Mode

t_FCL

SCL Fall Time

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

20

10

20

80

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

t_RCL1

ns

160

1000

300

120

80

20+0.1C_B

Fast Mode

20+0.1C_B

t_RDA

SDA Rise Time

SDA Fall Time

Fast Mode Plus

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

20+0.1C_B

160

300

120

80

Fast Mode

20+0.1C_B

t_FDA

Fast Mode Plus

ns

High-Speed Mode, C_B< 100 pF

High-Speed Mode, C_B< 400 pF

Standard Mode

10

20

4

160

s

ns

pF

Fast Mode

600

120

160

t_SU;STO

Stop Condition Setup Time

Fast Mode Plus

High-Speed Mode

C_B

Capacitive Load for SDA and SCL

400

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FAN54053 • Rev. 1.4

10

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 5.

I²C Interface Timing for Fast and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_HD;DAT

note A

t_RCL

t_SU;STO

SCLH

t_LOW

t_HD;STA

REPEATED

START

= MCS Current Source Pull-up

= R_PResistor Pull-up

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 6.

I²C Interface Timing for High-Speed Mode

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FAN54053 • Rev. 1.4

11

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.35 V, I_OCHARGE=950 mA, V_BUS=5.0 V, and T_A=25°C.

800

700

600

500

400

300

200

100

1,700

1,500

1,300

1,100

900

700

4.7 VBUS

5.0 VBUS

5.5 VBUS

4.7 VBUS

5.0 VBUS

5.5 VBUS

500

300

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

Battery Voltage VBAT (V)

Figure 7.

Battery Charge Current vs. V_BUSwith

I_BUSLIM=500 mA

Figure 8.

Battery Charge Current vs. V_BUSwith

I_BUSLIM=1100 mA

95

94

90

85

80

75

70

65

92

90

88

86

84

82

4.7VBUS, 3.9VBAT

4.7 VBUS

5.0 VBUS

5.5 VBUS

5.0VBUS, 3.9VBAT

5.0VBUS, 4.3VBAT

5.5VBUS, 4.3VBAT

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

550

750

950

1150

1350

1550

Battery Voltage VBAT (V)

Battery Charge Current IBAT (mA)

Figure 10. Efficiency vs. Charging Current,

I_BUSLIM=No Limit

Figure 9.

Efficiency vs. V_BUS, I_BUSLIM=500 mA, I_SYS=0

1,000

800

2.00

1.80

1.60

1.40

1.20

1.00

600

400

-30C

+25C

+85C

-30C

+25C

+85C

200

0

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

0

1

2

3

4

5

VBUS Input Voltage (V)

VREF Load Current (mA)

Figure 11. HZ Mode V_BUSCurrent vs. Temperature,

3.7 V_BAT

Figure 12. V_REFvs. Load Current, Over-Temperature

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FAN54053 • Rev. 1.4

12

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.35 V, I_OCHARGE=950 mA, V_BUS=5.0 V, and T_A=25°C.

Figure 13. Charger Startup at V_BUSPlug-In, 500 mA

I_BUSLIM, 3.1 V_BAT, 50 Ω SYS Load, CE# = 0,

IO_LVL=1

Figure 14. Charger Startup at V_BUSPlug-In, 1100 mA

I_BUSLIM, 3.6 V_BAT, 700 mA SYS Load, CE# = 0,

IO_LVL=0

Figure 16. Charger Startup with HZ Bit Reset,

500 mA I_BUSLIM, 950 mA I_CHARGE, 50 SYS Load,

CE# = 0

Figure 15. Charger Startup at V_BUSPlug-In Using

300 mA Current Limited Source, 500 mA I_BUSLIM

3.1 V_BAT, 200 mA SYS Load, CE# = 0, IO_LVL=0

,

FAN54053 • Rev. 1.4

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13

Charge Mode Typical Characteristics

Unless otherwise specified, circuit of Figure 1, V_OREG=4.35 V, I_OCHARGE=950 mA, V_BUS=5.0 V, and T_A=25°C.

Figure 17. Battery Removal / Insertion while

Charging, TE=0, 3.9 V_BAT, I_CHRG=950 mA, I_BUSLIM=No

Limit, 50 Ω SYS Load

Figure 18. Battery Removal / Insertion when

Charging, TE=1, 3.9 V_BAT, I_BUSLIM=No Limit, 50 Ω

SYS Load

Figure 19. Charger Enable (CE# = 1 -0) with V_BUS

Applied, I_BUSLIM=500 mA, 200 mA SYS Load,

IO_LVL=0

Figure 20. No Battery at V_BUSPower-Up, 100 Ω SYS

Load, 1 kΩ V_BATLoad

FAN54053 • Rev. 1.4

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14

GSM Typical Characteristics

A 2.0 A GSM pulse applied at V_BATwith 5 µs rise / fall time. Simultaneous to GSM pulse, 50 Ω additional load applied at SYS.

Figure 21. 2.0 A GSM Pulse Response,

I_BUSLIM=500 mA Control, I_CHRG=950 mA, 3.7 V_BAT

OREG=4.35 V

Figure 22. 2.0 A GSM Pulse Response,

I_BUSLIM=500 mA, I_CHRG=950 mA, 3.7 V_BAT

OREG=4.35 V, 200 mA Source Current Limit

,

FAN54053 • Rev. 1.4

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15

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

100

95

90

85

80

75

100

95

90

85

80

75

-10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

2.7VBAT

3.6VBAT

4.2VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 23. Efficiency vs. I_BUSOver V_BAT

Figure 24. Efficiency vs. I_BUSOver-Temperature,

3.6 V_BAT

5.15

5.10

5.05

5.00

4.95

4.90

4.85

30

25

20

15

2.7VBAT

3.6VBAT

4.2VBAT

10

2.7VBAT

5

3.6VBAT

4.2VBAT

0

100

200

300

400

500

0

100

200

300

400

500

VBUS Load Current (mA)

Figure 25. Regulation vs. I_BUSOver V_BAT

Figure 26. Output Ripple vs. I_BUSOver V_BAT

350

10

-30C

+25C

+85C

300

250

200

150

100

8

6

4

2

0

-30C

+25C

+85C

2

2.5

3

3.5

4

4.5

5

2

2.5

3

3.5

4

4.5

5

Battery Voltage, VBAT (V)

Figure 27. Quiescent Current (I_Q) vs. V_BATOver-

Temperature

Figure 28. Battery Discharge Current vs. V_BAT, HZ /

Sleep Mode

FAN54053 • Rev. 1.4

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16

Boost Mode Typical Characteristics

Unless otherwise specified, using circuit of Figure 1, V_BAT=3.6 V, T_A=25°C.

Figure 29. OTG Startup, 50 Ω Load, 3.6 V_BAT

Figure 30. OTG V_BUSOverload Response

External / Additional 10 µf on V_BUS

Figure 31. Load Transient, 20-200-20 mA I_BUS

,

Figure 32. Line Transient, 50 Ω Load, 3.9-3.3-

t_RISE/FALL=100 ns

3.9 V_BAT, t_RISE/FALL=10 µs

FAN54053 • Rev. 1.4

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17

Circuit Description / Overview

When charging batteries with a current-limited input source,

such as USB, a switching charger’s high efficiency over a

wide range of output voltages minimizes charging time.

PWM Controller in Charge Mode

The IC uses a current-mode PWM controller to regulate the

output voltage and battery charge currents. The synchronous

rectifier (Q2) has a negative current limit that turns off Q2 at

140 mA to prevent current flow from the battery.

FAN54053 combines a highly integrated synchronous buck

regulator for charging with a synchronous boost regulator,

which can supply 5 V to USB On-The-Go (OTG) peripherals.

The FAN54053 employs synchronous rectification for both

the charger and boost regulators to maintain high efficiency

over a wide range of battery voltages and charge states.

Battery Charging Curve

If the battery voltage is below V_SHORT, a linear current source

pre-charges the battery until V_BATreaches V_SHORT. The PWM

charging circuit is then started and the battery is charged

with a constant current if sufficient input power is available.

The current slew rate is limited to prevent overshoot.

The FAN54053 has four operating modes:

1. Charge Mode:

Charges a single-cell Li-ion or Li-polymer battery.

During the current regulation phase of charging, I_BUSLIMor

the programmed charging current limits the amount of

current available to charge the battery and power the

system.

2. Boost Mode:

Provides 5 V power to USB-OTG with an integrated

synchronous rectification boost regulator, using the

battery as input.

During the voltage regulation phase of charging, assuming

that V_OREGis programmed to the cell’s fully charged “float”

voltage, the current that the battery accepts with the PWM

regulator limiting its output (sensed at VBAT) to V_OREG

declines.

3. High-Impedance Mode:

Both the boost and charging circuits are OFF in this

mode. Current flow from VBUS to the battery or from the

battery to VBUS is blocked in this mode. This mode

consumes very little current from VBUS or the battery.

V_BAT

V_FLOAT

4. Production Test Mode:

I_BAT

This mode provides 4.35 V output on VBAT and

supplies a load current of up to 2.3 A.

I_CHARGE

I_{O_LEVEL}

V_BATMIN

Charge Mode and Registers

I_TERM

Charge Mode

In Charge Mode, FAN54053 employs six regulation loops:

V_SHORT

I_SHORT

1. Input Current: Limits the amount of current drawn from

VBUS. This current is sensed internally and can be

programmed through the I²C interface.

I_SHORT

CHARGE

CONSTANT

VOLTAGE (CV)

PRE-

CONSTANT

CHARGE CURRENT (CC)

RE-

CHARGE

ICHARGE Current Charging

2. Charging Current: Limits the maximum charging current.

This current is sensed using an internal sense

MOSFET.

Figure 33. Charge Curve, I_CHARGENot Limited by

I_BUSLIM

3. VBUS Voltage: This loop is designed to prevent the

input supply from being dragged below V_BUSLIM(typically

4.5 V) when the input power source is current limited.

An example of this would be a travel charger. This loop

cuts back the current when V_BUSapproaches V_BUSLIM,

allowing the input source to run in current limit.

The FAN54053 is designed to work with a current-limited

input source at VBUS as shown below:

V_BAT

V_FLOAT

I_CHARGE

4. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery voltage

rises, the battery’s internal impedance works in

conjunction with the charge voltage regulation to

decrease the amount of current flowing to the battery.

Battery charging is completed when the current through

Q4 drops below the I_TERMthreshold.

I_BA

T

I_{O_LEVEL}

V_BATMIN

I_TERM

V_SHORT

I_SHORT

5. Pre-charge: When V_BATis below V_BATMIN, Q4 operates

as a linear current source and modulates its current to

ensure that the voltage on SYS stays above 3.4 V.

I_SHORT

CHARGE

CONSTANT

VOLTAGE (CV)

PRE-

CONSTANT

CHARGE CURRENT (CC)

RE-

CHARGE

Input Current Limited Charging

6. Temperature: If the IC’s junction temperature reaches

120°C, charge current is reduced until the IC’s

temperature is below 120°C.

Figure 34. Charge Curve, I_BUSLIMLimits I_CHARGE

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FAN54053 • Rev. 1.4

18

The following charging parameters can be programmed by

the host through I²C:

PWM charging stops and the PC_ON bit changes back to

“0”. If the charging current goes above I_TERMwithout first falling

to PC_IT, the PC_ON bit can be reset by using any of these

methods: V_BATmoving below and above V_BATMIN, a V_BUSPOR,

or the CE# or HZ_MODE bit cycled. If V_BATfalls to V_RCHbelow

V_OREG, the Fast Charge cycle starts again.

Table 3. Programmable Charging Parameters

Parameter

Name

Register

Output Voltage Regulation

Battery Charging Current Limit

Input Current Limit

V_OREG

REG2[7:2]

See ITERM Register Bit Definitions

I_OCHARGEREG4[6:3]

Weak Battery Voltage (V_LOWV

)

I_BUSLIM

I_TERM

V_LOWV

V_BUSLIM

REG1[7:6]

REG4[2:0]

REG1[5:4]

REG5[2:0]

The FAN54053 monitors the level of the battery with respect

to a programmable V_LOWV(REG01h<5:4>) threshold (default

3.7 V). The V_LOWVthreshold defines the voltage level of the

battery at which the system is guaranteed to be fully

operational when only powered by the battery.

Charge Termination Limit

Weak Battery Voltage

VBUS Control

The POK_B pin pulls LOW once V_BATreaches V_LOWV, and

remains LOW as long as the IC is in Fast Charge. The IC will

remain in Fast Charge as long as VBAT > 3.0 V.

Output Voltage Regulation (V_OREG

)

The charger output or “float” voltage can be programmed by

the OREG (REG02[7:2]) bits from 3.51 V to 4.45 V in 20 mV

increments. The defauilt setting is 3.55 V.

See VLOWV Register Bit Definitions

VBUS Control loop (V_BUSLIM

)

See OREG Register Bit Definitions

The IC includes a control loop that limits input current in

case a current-limited source is supplying V_BUS

.

Battery Charging Current Limit (I_OCHARGE

)

The control increases the charging current until either:

When the IO_LEVEL bit is set (default), the I_OCHARGEbits are

ignored and charge current is set to 200 mA.

.

I_BUSLIMor I_OCHARGEis reached OR

V_BUS= V_BUSLIM

.

See IOCHARGE Register Bit Definitions

If V_BUScollapses to V_BUSLIM, the VBUS loop reduces its

current to keep V_BUS= V_BUSLIM. When the VBUS control loop

is limiting the charge current, the VLIM bit (REG05h[3]) is

set.

Input Current Limiting (I_BUSLIM

To minimize charging time without overloading VBUS current

limitations, the IC’s input current limit can be programmed by

the I_BUSLIM(REG1[7:6]) bits.

)

See VBUSLIM Register Bit Definitions

For the FAN54053, no charging occurs automatically at V_BUS

POR, so the input current limit is established by the I_BUSLIM

bits.

See IBUSLIM Register Bit Definitions

Charger Operation

Termination Limit (I_TERM

)

VBUS Plug In and Safety Timer

Charge current termination can be enabled or disabled using

the TE (REG01h[3]) bit. By default TE = “0”, therefore,

termination is disabled and charging does not terminate at

the programmed I_TERMlevel.

At VBUS plug in, the TMR_RST (Reg00h[7]) bit must be set

within 2 seconds of V_BUSrising above V_(INMIN)1or all registers,

except for SAFETY (REG06h), are set to their default

values. This functionality occurs regardless of the state of

the CE# and WD_DIS bit. If plug in occurs with the device in

a HZ or Charge Done state and the TMR_RST bit is not set

within 2 seconds of V_BUSrising above V_(INMIN)1, all register,

except for SAFETY, will reset when the device enters PWM

Charging or Recharge.

When TE = “1”, and V_BATreaches V_OREG, the charging

current is reduced, limited by the battery’s ESR and its

internal cell voltage. When the charge current falls below

I_TERM; PWM charging stops; but the STAT pin remains LOW.

The STAT pin then goes HIGH and the STAT bits change to

CHARGE DONE (10), provided the battery and charger are

still connected. If V_BATfalls to V_RCHbelow V_OREG, the Fast

Charge cycle starts again.

By default, the safety timers do not run in the FAN54053. A

Watchdog (t_32s) timer can be enabled by setting the WD_DIS

register bit, (REG13h[1]) to “0”. When WD_DIS = “0”,

charging is controlled by the host with the t_32Stimer running

to ensure that the host is alive. Setting the TMR_RST bit

resets the t_32Stimer. If the t_32Stimer times out; all registers,

except SAFETY, are set to their default values (including

WD_DIS and CE#), the FAULT bits are set to “110”, and

STAT is pulsed.

Post-charging can be enabled to “top-off” the battery to a

lower termination current threshold than I_TERM. The PC_EN

bit (REG07h[3]) must be set to “1” before the battery

charging current reaches I_TERM. The lower termination

current is set by the PC_IT (REG07h[2:0] bits. Post-charging

begins after normal charging is ended (as described above)

with the PC_ON (REG11h[2]) monitor bit set to “1”.

During post-charging, the STAT pin is HIGH, indicating that

the charge current is below the I_TERMlevel. Once the current

reaches the threshold for post-charging completion (PC_IT),

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FAN54053 • Rev. 1.4

19

V_BUSPOR / Non-Compliant Charger Rejection

Power Path Operation

256 ms after VBUS is connected, the IC pulses the STAT pin

and sets the VBUS_CON bit. Before starting to supply

current, the IC applies a 110  load from VBUS to GND.

V_BUSmust remain above V_IN(MIN)1and below VBUS_OVPfor

t_{VBUS_VALID}(32 ms) before the IC initiates charging or

supplies power to SYS.

As long as V_BAT< V_BATMIN, Q4 operates as a linear current

source, (Precharge) with its current (I_PP) limited to 200 mA

when IO_LEVEL (REG05h[5]) is set to its default value of

“1”. If IO_LEVEL is set to “0” and I_INLIM> “01”, charge current

is limited to 450 mA when I_OCHARGE≤ 750 mA, and 730 mA

when I_OCHARGE> 750 mA. Providing the input current is not

limited by the I_BUSLIMsetting or the current available from the

source, during precharge, the IC regulates SYS to 3.55 V

and provides the IO_LEVEL limited current to the battery.

The VBUS validation sequence always occurs before

significant current is available to be drawn from VBUS (for

example, after a VBUS OVP fault or a V_RCH(recharge

initiation). t_{VBUS_VALID}ensures that unfiltered 50/60 Hz

chargers and other non-compliant chargers are rejected.

System power always has the highest priority when power

from the buck is limited ensuring SYS does not fall below

3.4 V. This is managed by folding back the current to charge

the battery until charge current is reduced to 0 A.

USB-Friendly Boot Sequence

The FAN54053 does not automatically initiate charging at

V_BUSPOR. Instead, prior to receiving host commands, the

buck is enabled to provide power to SYS while Q4 and Q5

remain off until register bit CE# (REG01[2]) is set to “0”

through the I²C interface, allowing charging through Q4.

After V_BATreaches V_BATMIN, Q4 closes and is used as a

current-sense element to limit current (I_OCHRG) per the I²C

register settings. This is accomplished by limiting the PWM

modulator’s current (Fast Charge). If SYS drops more than

5 mV (V_THSYS) below V_BATand CE# = “0”, Q4 and Q5 are

turned on (GATE is pulled LOW). If CE# = “1”, only Q5 is

turned on. Once SYS voltage becomes higher than V_BAT, Q5

is turned off and Q4 again serves as the current-sense

Startup with No Battery

The FAN54053 has Battery Absent Behavior enabled. At

V_BUSPOR with the battery absent, the PWM will run,

providing 3.55 V to the system from the input source with

current limited by the default I_BUSLIMsetting.

element to limit I_OCHRG

.

If CE# = “1” and DIS pin is high or CE# = “1” and HZ_MODE

= “1” while V_BAT> V_LOWV, so as to prevent the system from

crashing, Q4 and Q5 are enabled. Q4 and Q5 are also both

turned on when the IC enters SLEEP Mode (V_BUS< V_BAT).

Startup with a Dead Battery

At V_BUSPOR, if V_BAT< V_SHORT, all registers, including the

SAFETY register, are reset to their default values and the

DBAT_B (REG02h[1]) bit is reset. CE# = “1”, so charging is

disabled.

POK_B (see Table 4)

The POK_B pin and POK_B (REG11h[5]) bit are intended to

provide feedback to the baseband processor that the battery

is strong enough to allow the device to fully function.

Whenever the IC is operating in precharge, POK_B is HIGH.

If the battery’s protection switch is open, the PWM will run,

providing 3.55 V to the system from the input source with

current limited by the default I_BUSLIMsetting. This allows the

host processor to awaken and establish host control. Once

this occurs, the host’s low level software can program the

CE# bit to “0” and a linear current source closes the battery

protection switch. When V_BATvoltage rises above V_SHORTand

sufficient power is available, PWM charging begins and the

battery is charged through the BATFET, Q4. The IO_LEVEL

(REG05h[5]) bit is set to “1” by default which limits charge

current to 200 mA.

On exiting Precharge, POK_B remains HIGH until V_BAT

>

V_LOWV. REG01h[5:4] sets the V_LOWVthreshold.POK_B pulls

LOW once V_BATreaches V_LOWV, and remains LOW as long

as the IC is in Fast Charge and the IC will remain in Fast

Charge as long as V_BAT> 3.0 V. If the battery voltage falls

below 3.0 V the IC enters Precharge. If WD_DIS = “0” and

the T_32Sexpires during charging, the POK_B pin will go high.

If the battery was above V_LOWVand has fallen below the

level, the POK_B bit can be set to change the state of the

pin to be high. This setting of the bit and pin can be used to

With CE# = “1” once V_BATrises above V_SHORT, DBAT_B is

set. With CE# = “0” once V_BATrises above V_BATMIN, DBAT_B

is set.

signal the system into

a low-power state, preventing

excessive loading from the system while attempting to

recharge a depleted battery.

The STAT pin pulses any time the POK_B pin changes.

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FAN54053 • Rev. 1.4

20

Table 4. Q4, Q5, POK_B vs. Operating Mode

Operating Mode

V_BUS

V_BAT

CE# PWM V_SYS

BUS Disconnected

Q4

Q5

GATE

POK_B

< V_{BAT OR}

< V_IN(MIN)2

OFF

> V_SHORT

X

OFF < V_BAT

ON

LOW

HIGH

VBUS Plug in with Battery Protection Switch Open

1

HIGH

PWM

Valid

OPEN

ON

V_OREGOFF

OFF

HIGH

0

Indeterminate⁽⁸⁾

30 mA Linear Charging ⁽⁹⁾

< V_SHORT

0

3.55

OFF

HIGH

Charge Mode

> V_SHORTand

< V_BATMIN

Precharge

Precharge:

Valid

0

ON

3.55 Linear

< 3.55 Linear

OFF

HIGH

I_SYS+ I_pp> I_PWM

,

< V_BATMIN

0

ON

I_BAT< I_PP

> V_BATMINand

< V_LOWV

HIGH

LOW

Fast Charge

Precharge

Valid

0

ON

> V_BAT

ON

OFF

HIGH

> V_LOWV

Battery Voltage Falling from Fast Charge

V_BATFALLON 3.55

Battery Supplementing SYS

0

HIGH

> V_SHORT

1

ON

< V_BAT

X

ON

LOW

X

Supplemental Mode :

I_SYS> I_PWM

> V_BATMINand

> V_SYS+ V_THSYS

0

ON

< V_BAT

Note:

8. When V_BATis open it can float to V_SYS, and POK_B = HIGH when V_BAT< V_LOWVand POK_B = LOW when V_BAT> V_LOWV.

9. 30 mA Linear Charging operating mode assumes the host has programmed CE# = “0” during PWM Operating Mode.

The state of the MONITOR register bits listed in High-

Impedance Mode is valid only when V_BUSis valid.

Charger Status / Fault Status

The STAT pin indicates the operating condition of the IC and

provides a fault indicator for interrupt driven systems.

Charge Mode Control Bits

The CE# (REG01h[2]) bit is set to “1’ by default, therefore,

charging is disabled.

Table 5. STAT Pin Function

EN_STAT

Charge State

STAT Pin

Setting the RESET (REG04h[7]) bit clears all registers

(except SAFETY). The CE# bit will only be cleared if RESET

occurs with a valid VBUS and V_BAT< V_LOWV. If HZ_MODE or

the WD_DIS bit was set when the RESET bit is set, this bit is

also cleared. Refer to the Register Bit Definitions section for

more details.

0

X

1

X

OPEN

LOW

Normal Conditions

Charging

128 s Pulse,

then OPEN

X

Fault (Charging or Boost)

The HZ_MODE (REG01h[1]) and DIS pin will put the device

in High-Impedance Mode. If HZ_MODE = “1” or DIS pin is

HIGH, so as to prevent the system from crashing, Q4 and

Q5 are enabled.

The FAULT bits (REG00h[2:0]) indicate the type of fault in

Charge Mode.

Monitor Registers (REG10h, REG11h)

The functionality of the HZ_MODE (REG01h[1]) bit and DIS

pin has a dependence upon V_BATvoltage level and the

WD_DIS (REG13h[1]) bit state. Refer to Table 5 for details.

Additional status monitoring bits enable the host processor

to have more visibility into the status of the IC. The monitor

bits are real-time status indicators and are not internally

debounced or otherwise time qualified.

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FAN54053 • Rev. 1.4

21

Table 6. DIS Pin, HZ_MODE and WD_DIS bits Operation

Conditions

Functionality

Setting either the HZ_MODE bit through I²C or the DIS pin to HIGH will disable

the charger and put the IC into High-Impedance Mode.

Resetting the HZ_MODE bit or the DIS pin to LOW will allow charging to resume.

WD_DIS = 1 and V_BAT> V_LOWV

While in High-Impedance mode, if V_BATdrops below V_LOWV, all registers (except

SAFETY), including HZ_MODE and CE# are reset. Note that charge parameters

will need to be reprogrammed in order to completely charge the battery.

Setting either the HZ_MODE bit through I²C or the DIS pin to HIGH will reset all

registers (except SAFETY), including HZ_MODE and CE#.

Setting either the HZ_MODE bit through I²C or the DIS pin to HIGH will stop the

t_32Stimer from advancing (does not reset it), disable the charger, and put the IC

into High-Impedance Mode.

WD_DIS = 1 and V_BAT< V_LOWV

WD_DIS = 0 and V_BAT> V_LOWV

Resetting the HZ_MODE bit or the DIS pin to LOW will allow charging to resume.

Setting either the HZ_MODE bit through I²C or the DIS pin to HIGH will disable

the charger and put the IC into High-Impedance Mode. The T_32Stimer will

continue to run. If the T_32Stimer is allowed to overflow, all registers (except

SAFETY) are reset, including WD_DIS, HZ_MODE and CE#.

WD_DIS = 0 and V_BAT< V_LOWV

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FAN54053 • Rev. 1.4

22

Flow Charts

VBUS POR

CHARGE STATE

Linear Charging,

Reset SAFETY reg

YES

V_BAT< V_SHORT

NO

YES

V_BAT< V_SHORT

Enable PWM

NO

Write TMR_RST

within 2sec ?

Reset all registers,

except SAFETY

NO

FIRST TIME?

YES

NO

Enable PWM

YES

CE# = 1

NO

Enable Linear

Charge and Q5

YES

Disable Q5 &

Linear Charge

IDLE State

NO

CE# = 1

NO

V_BAT< V_BATMIN

YES

Enable Fast

charge

IDLE State

YES

Protection

switch closed?

YES

Enable Precharge

charging

NO

Battery

Present ?

I_OUT< I_TERM

and TE = 1

YES

NO

Indicate Charge

Complete

NO

YES

Set NOBAT bit

PWM ON

Q4 and Q5 OFF

Reset charge

parameters &

SAFETY reg

V_BAT

<

NO

V_OREG– V_RCH

?

VBUS OK ?

NO

YES

Disable PWM for

2 seconds

EOC = 1

NO

YES

Note: Reset Charge Parameters is a condition

that results in the SAFETY, OREG, IOCHARGE,

IBUSLIM, ITERM, and VLOWV register bits

resetting. It does not reset the IO_Level, EOC,

and TE register bits.

Indicate

VBUS Fault

Figure 35. Charge State Flow Chart

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FAN54053 • Rev. 1.4

23

Standby

State

PWM = OFF

Q4, Q5 = ON

A Register

Written?

NO

YES

HZ or

DISABLE Pin

set?

Charge State

NO

YES

HZ STATE

Figure 36. Standby State

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FAN54053 • Rev. 1.4

24

10. If I_OCHARGEis programmed to less than 650 mA, the

charge current is limited to 340 mA.

Non-Charging States

Sleep Mode

When V_BUSfalls below V_BAT+ V_SLPand V_BUSis above

V_IN(MIN)2, the IC enters Sleep Mode to prevent the battery

from draining into VBUS. During Sleep Mode, reverse

current is disabled by body switching Q1.

Thermistors with other  values can be used, with some shift

in the corresponding temperature threshold, as shown in

Table 9.

Table 9. Thermistor Temperature Thresholds

R_REF= R_THRMat 25°C.

Idle State

Parameter

Various Thermistors

The Idle State is related to the condition of the battery.

During Idle mode the Switch Mode Power Supply (SMPS) is

operating, but the battery is not being charged for one or

more of the following conditions exists: the Safety Timer

expires, charging is complete, or the BATFET is disabled by

the Charge Enable bit, CE# = “1”.

R_THRM(25°C)

10 kΩ

3380

0°C

10 kΩ

3940

3°C

47 kΩ

4050

6

100 kΩ

4250

8



T1

T2

T3

T4

10°C

45°C

60°C

12°C

42°C

55°C

13

14

The PWM Buck continues to supply power to the system, but

the Battery is no longer being charged and the BATFET is

disabled.

41

40

53

51

Standby State

The host processor can disable temperature-driven control

of charging parameters by writing “1” to the TEMP_DIS bit.

Since TEMP_DIS is reset whenever the IC resets its

registers, the temperature controls are enforced whenever

the IC is auto-charging, since auto-charge is always

preceeded by a reset of registers.

The Standby State is an intermediate state where the switch

mode supply is off due to either bad input power, the device

has been put in High-Impedance Mode, or the die

temperature is too hot.

To disable the thermistor circuit, tie the NTC pin to GND.

Before enabling the charger, the IC tests to see if NTC is

shorted to GND. If NTC is shorted to GND, no thermistor

readings occur and the NTC_OK and NTC1-NTC4 is reset.

Charger Protection

Battery Temperature (NTC) Monitor

The FAN54053 reduces the maximum charge current and

termination voltage if an NTC measuring battery temperature

(T_BAT) indicates that it is outside the fast-charging limits (T2

to T3), as described in the JEITA specification¹. There are

four temperature thresholds that change battery charger

operation: T1, T2, T3, and T4, shown in Table 7.

The IC first measures the NTC immediately prior to entering

any PWM charging state, then measures the NTC once per

second, updating the result in NTC1-NTC4 bits (REG

12h[3:0]).

Table 10. NTC1-NTC4 Decoding

T_BAT(°C)

Above T4

NTC4 NTC3 NTC2 NTC1

Table 7. Battery Temperature Thresholds

1

0

1

0

1

0

1

0

For use with 10 kΩ NTC,  = 3380, and R_REF= 10 kΩ.

Between T3 and T4

Between T2 and T3

Between T1 and T2

Below T1

Threshold

Temperature

0°C

% of V_REF

73.9

T1

T2

T3

T4

10°C

64.6

45°C

32.9

60°C

23.3

Safety Register Settings

The IC contains a SAFETY register (REG06h) that prevents

the values in OREG (REG02h[7:2]) and IOCHARGE

(REG04h[7:4]) from exceeding the values of VSAFE

(REG06h[3:0]) and ISAFE (REG06h[7:4]) in the SAFETY

register.

Table 8. Charge Parameters vs. T_BAT

T_BAT(°C)

Below T1

I_CHARGE

V_FLOAT

Charging to VBAT Disabled

Between T1 and T2

Between T2 and T3

Between T3 and T4

Above T4

I_OCHARGE/ 2⁽¹⁰⁾

4.0 V

V_OREG

4.0 V

After V_BATrises above V_SHORT, the SAFETY register is

loaded with its default value and may be written to only

before writing to any other register. The same 8-bit value

should be written to the SAFETY register twice to set the

register value. After writing to any other register, the

I_OCHARGE

I_OCHARGE/ 2⁽¹⁰⁾

Charging to VBAT Disabled

Note:

SAFETY register is locked until V_BATfalls below V_SHORT

.

If the host attempts to write a value higher than VSAFE or

ISAFE to OREG or I_OCHARGE, respectively; the VSAFE,

ISAFE value appears as the OREG, I_OCHARGEregister value,

respectively.

1

Japan Electronics and Information Technology Industries

Association (JEITA) and Battery Association of Japan. “A Guide to

the Safe Use of Secondary Lithium Ion Batteries in Notebook-type

Personal Computers,” April 28, 2007.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

25

The Safety register is reset when the battery is below 3.0 V

and power is removed from the VBUS if CE# = “1”. The

Safety register can be re-written to if it is the first I2C write

anytime after the VBUS removal.

Charge Mode Battery Detection & Protection

V_BATOver-Voltage Protection

The OREG voltage regulation loop prevents V_BATfrom

overshooting V_OREGby more than 50 mV when the battery is

removed. When the PWM charger runs with no battery, the

TE bit is not set and a battery is inserted that is charged to a

voltage higher than V_OREG; PWM pulses stop. If no further

pulses occur for 30 ms, the IC sets the FAULT bits to “100”,

sets the STAT bits to “11”, and pulses the STAT pin

See VSAFE and ISAFE Register Bit Definitions

Thermal Regulation and Shutdown

When the IC’s junction temperature reaches TCF (about

120°C), the charger reduces its output current to 550 mA to

prevent overheating. If the temperature increases beyond

T_SHUTDOWN; charging is suspended, the FAULT bits are set to

101, and STAT is pulsed high. In Suspend Mode, all timers

stop and the state of the IC’s logic is preserved. Charging

resumes at programmed current after the die cools to about

120°C.

Battery Detection during Charging

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set to “1” and CE# = “0”.

During normal charging, once V_BATis close to V_OREGand the

charge current falls below I_TERM; the PWM charger continues

to provide power to SYS and Q4 is turned off. It then turns

on a discharge current, I_DETECT, for t_DETECT. If V_BATis still above

V_OREG– V_RCH, the battery is present and the IC sets the STAT

bits to “10” (Charge Done). If V_BATis below V_OREG– V_RCH, the

battery is absent and the IC:

Note that as power dissipation increases, the effective _JA

decreases due to the larger difference between the die

temperature and ambient.

Charge Mode Input Supply Protection

Input Supply Low-Voltage Detection

1. Sets the charging parameters to their default values.

The IC continuously monitors V_BUSduring charging. If V_BUS

falls below V_IN(MIN)2, the IC:

2. Sets the FAULT bits to “111” (Battery Absent) and sets

the NOBAT bit.

1. Terminates charging

3. If EOC = “0”, the IC turns off the PWM for t_INT, then

resumes charging and retries Battery Detection. If the

battery is still absent, the process repeats with the “No

Battery” fault re-enunciated.

2. Pulses the STAT pin, sets the STAT bits to “11”, and

sets the FAULT bits to “011”.

If V_BUSrecovers above the V_IN(MIN)1rising threshold after time

t_INT(about two seconds), the charging process is repeated.

This function prevents the USB power bus from collapsing or

oscillating when the IC is connected to a suspended USB

port or a low-current-capable OTG device.

4. If EOC = “1”, the PWM remains on to provide power to

SYS, but charge termination and the battery absent test

are performed every t_INT

.

Linear Charging

Input Over-Voltage Detection

If the battery voltage is below the short-circuit threshold

(V_SHORT); a linear current source, I_SHORT, charges V_BATuntil

When the V_BUSexceeds VBUS_OVP, the IC:

V_BAT> V_SHORT

.

1. Turns off Q3

2. Suspends charging

3. Sets the FAULT bits to “001”, sets the STAT bits to

“11”, and pulses the STAT pin.

Production Test Mode (PTM)

PTM provides 4.20 V at up to 2.3 A to VBAT when V_BUS

5.5 V ±5%.

=

When VBUS falls about 100 mV below VBUSOVP, the fault

is cleared and charging resumes after VBUS is revalidated.

The IC enters PTM when the PROD (REG05h[6]) bit is set

after the NOBAT (REG11h[3]) bit has been set. The NOBAT

bit indicates that the IC has detected battery absence. A

battery absence detection test is performed automatically at

current termination. The steps for entering PTM should

include: set the TE (REG01h[3]) bit high, set the CE#

(REG01h[2]) bit low, wait for the NOBAT bit to set HIGH,

then set the PROD bit to “1” to enter PTM. Battery absence

detection is completed within 500 ms from the time that CE#

is set.

SYS Short During Discharge / Supplemental Mode

Caution should be taken to ensure the SYS pin is not

shorted when connected to a battery. This condition can

induce high current flow through the BATFET (Q4) and the

external FET (Q5) until the battery’s own safety circuit trips.

The resulting high current can damage the IC.

VBUS Short While Charging

If VBUS is shorted with a very low impedance while the IC is

charging with I_BUSLIM= 100 mA, the IC may not meet

datasheet specifications until power is removed. To trigger

this condition, V_BUSmust be driven from 5 V to GND with a

high slew rate. Achieving this slew rate requires a 0  short

to the USB cable less than 10 cm from the connector.

In PTM, the GATE bit (REG11h[7]) is LOW, Q5 is on, and all

auxiliary control loops are disabled. Only the OREG loop is

active, which controls V_BATto 4.20 V, regardless of the

OREG register setting. Thermal shutdown remains active.

During PTM, high current pulses (load currents greater than

1.5 A) must be limited to 20% duty cycle with a minimum

period of 10 ms.

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FAN54053 • Rev. 1.4

26

PFM Mode

Boost Mode

If V_BUS> VREF_BOOST(nominally 5.07 V) when the minimum

off-time ends, the regulator enters PFM Mode. Boost pulses

are inhibited until V_BUS< VREF_BOOST. The minimum on-time

is increased to enable the output to pump up sufficiently with

each PFM boost pulse. Therefore, the regulator behaves like

a constant on-time regulator, with the bottom of its output

voltage ripple at 5.07 V in PFM Mode.

Boost Mode can be enabled if the IC is in 32-Second Mode

by setting the OPA_MODE REG01h[0]) bit HIGH and

clearing the HZ_MODE bit.

Table 11. Enabling Boost

HZ_MODE

OPA_MODE

BOOST

Enabled

Disabled

0

1

X

1

X

0

Table 12. Boost PWM Operating States

Mode

Description

Invoked When

LIN

SS

Linear Startup

V_BAT> V_BUS

V_BUS< V_BST

To remain in Boost Mode, the TMR_RST must be set by the

host before the t_32Stimer times out. If t_32Stimes out in Boost

Mode; the IC resets all registers, pulses the STAT pin, sets

the FAULT bits to 110, and resets the BOOST bit. VBUS

POR or reading R0 clears the fault condition.

Boost Soft-Start

V_BAT> UVLO_BSTand

SS Completed

BST

Boost Operating Mode

Startup

Boost PWM Control

When the boost regulator is shut down, current flow is

prevented from V_BATto V_BUS, as well as reverse flow from

VBUS to VBAT.

The IC uses a minimum on-time and computed minimum off-

time to regulate V_BUS. The regulator achieves excellent

transient response by employing current-mode modulation.

This technique causes the regulator to exhibit a load line.

During fast charging, the output voltage drops slightly as the

input current rises. With a constant V_BAT, this appears as a

constant output resistance.

LIN State

When EN rises, if V_BAT> UVLO_BST; the regulator first

attempts to bring PMID within 400 mV of V_BATusing an

internal 450 mA current limited source from V_BAT(LIN State).

If PMID has not achieved V_BAT– 400 mV after 560 s, a fault

state is initiated.

The “droop” caused by the output resistance when a load is

applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 31 and Figure 37.

SS State

When PMID > V_BAT– 400 mV, the boost regulator begins

switching with a reduced peak current limit of about 50% of

its normal current limit. The output slews up until V_BUSis

within 5% of its setpoint; at which time, the regulation loop is

closed and the current limit is set to 100%.

400

360

320

280

240

200

If the output fails to achieve 95% of its setpoint (V_BST) within

128 s, the current limit is increased to 100%. If the output

fails to achieve 95% of its setpoint after this second 384 s

period, a fault state is initiated.

BST State

This is the normal operating mode of the regulator. The

regulator uses a minimum t_OFF-minimum t_ONmodulation

2.0

2.5

3.0

3.5

4.0

4.5

V

IN

scheme. The minimum t_OFFis proportional to

, which

Battery Voltage, VBAT (V)

V

OUT

Figure 37. Output Resistance (R_OUT

)

keeps the regulator’s switching frequency reasonably

constant in CCM. t_ON(MIN)is proportional to V_BATand is a

higher value if the inductor current reached 0 before t_OFF(MIN)

in the prior cycle.

V_BUSas a function of I_LOADcan be computed when the

regulator is in PWM Mode (continuous conduction) as:

V_OUT 5.07 R_OUTI_LOAD

EQ. 1

To ensure V_BUSdoes not overshoot the regulation point, the

boost switch remains off as long as V_FB> V_REF(BST)

.

At V_BAT=3.0 V and I_LOAD=300 mA, V_BUSdrops to:

Boost Faults

V_OUT 5.07 0.300.3  4.98V

EQ. 2

EQ. 3

If a BOOST fault occurs:

1. The STAT pin pulses.

2. OPA_MODE bit is reset.

At V_BAT=3.6 V and I_LOAD=500 mA, V_BUSdrops to:

V_OUT 5.07 0.240.5  4.95V

3. The power stage is in High-Impedance Mode.

4. The FAULT bits (REG0[2:0]) are set per Table 13.

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FAN54053 • Rev. 1.4

27

Restart After Boost Faults

Data change allowed

OPA_MODE is reset on boost faults. Boost Mode can only

be re-enabled by setting the OPA_MODE bit.

SDA

SCL

Table 13. Fault Bits During Boost Mode

Fault Bit

t_H

Fault (REG00h[2:0]) Description

B2 B1 B0

t_SU

0

1

Normal (no fault)

V_BUS> VBUS_OVP

Figure 38. Data Transfer Timing

V_BUSfails to achieve the voltage required to

advance to the next state during soft-start

or sustained (>50 s) current limit during the

BST state.

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which is

defined as SDA transitioning from 1 to 0 with SCL HIGH, as

shown in Figure 39.

0

1

0

1

0

1

0

1

0

1

V_BAT< UVLO_BST

t_HD;STA

Slave Address

MS Bit

NA: This code does not appear.

Thermal shutdown

SDA

SCL

Timer fault; all registers reset.

NA: This code does not appear.

Figure 39. Start Bit

Transactions end with a STOP condition, which is SDA

I²C Interface

transitioning from 0 to 1 with SCL HIGH, as shown in Figure

40.

The FAN54053’s serial interface is compatible with

Standard, Fast, Fast Plus, and High-Speed Mode I²C bus

specifications. The FAN54053 SCL line is an input and the

SDA line is a bi-directional open-drain output; it can only pull

down the bus when active. The SDA line only pulls LOW

during data reads and when signaling ACK. All data is

shifted in MSB (bit 7) first.

Slave Releases

Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

SCL

Slave Address

Table 14. I²C Slave Address Byte

Figure 40. Stop Bit

During a read from the FAN54053 Figure 43 the master

issues a Repeated Start after sending the register address

and before resending the slave address. The Repeated Start

is a 1-to-0 transition on SDA while SCL is HIGH, as shown in

Figure 41.

7

6

5

4

3

2

1

0

1

0

1

0

1

R/W

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6h for all parts in the family. Other

slave addresses can be accommodated upon request.

Contact a Fairchild Semiconductor representative.

Bus Timing

Shown in Figure 38, data is normally transferred when SCL

is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

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FAN54053 • Rev. 1.4

28

High-Speed (HS) Mode

Read and Write Transactions

The protocols for High-Speed (HS), Low-Speed (LS), and

Fast-Speed (FS) Modes are identical except the bus speed

for HS Mode is 3.4 MHz. HS Mode is entered when the bus

master sends the HS master code 00001XXX after a start

condition. The master code is sent in Fast or Fast Plus Mode

(less than 1 MHz clock); slaves do not ACK the

transmission.

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

Master Drives Bus

All addresses and data are MSB first.

Table 15. Bit Definitions for Figure 42- Figure 45

Slave Drives Bus

defined as

and

.

Symbol

Definition

START, see Figure 39

The master then generates a repeated start condition that

causes all slaves on the bus to switch to HS Mode. The

master then sends I²C packets, as described above, using

the HS Mode clock rate and timing.

S

ACK. The slave drives SDA to 0 to acknowledge

the preceding packet.

A

The bus remains in HS Mode until a stop bit is sent by the

master. While in HS Mode, packets are separated by

repeated start conditions Figure 41.

NACK. The slave sends a 1 to NACK the

preceding packet.

R

P

Repeated START, see Figure 41

STOP, see Figure 40

Slave Releases

t_SU;STA

t_HD;STA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Multi-Byte (Sequential) Read and Write

Transactions

Sequential Write

Figure 41. Repeated Start Timing

The Slave Address, Reg Addr address, and the first data

byte are transmitted to the FAN54053 in the same way as in

a byte write Figure 42. However, instead of generating a

Stop condition, the master transmits additional bytes that are

written to consecutive sequential registers after the falling

edge of the eighth bit. After the last byte written and its ACK

bit received, the master issues a STOP bit. The IC contains

an 8-bit counter that increments the address pointer after

each byte is written.

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FAN54053 • Rev. 1.4

29

condition. This directs the slave’s I²C logic to transmit the

next sequentially addressed 8-bit word. The FAN54053

contains an 8-bit counter that increments the address pointer

after each byte is read, which allows the entire memory

contents to be read during one I²C transaction.

Sequential Read

Sequential reads are initiated in the same way as a single-

byte read , except that once the slave transmits the first data

byte, the master issues an acknowledge instead of a STOP

Figure 42. Single-Byte Write Transaction

Figure 43. Single-Byte Read Transaction

Figure 44. Multi-Byte (Sequential) Write Transaction

Figure 45.

Multi-Byte (Sequential) Read Transaction

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FAN54053 • Rev. 1.4

30

Register Descriptions

The Twelve user-accessible IC registers are defined in Table 17.

Table 16. I²C Register Map

Register

BIT NAME

Name

REG#

7

6

5

4

3

2

1

0

CONTROL0

CONTROL1

OREG

0H

1H

2H

3H

4H

TMR_RST

EN_STAT

STAT

BOOST

TE

FAULT

HZ_MODE

DBAT_B

IBUSLIM

VLOWV

CE#

OPA_MODE

EOC

OREG

IC_INFO

IBAT

Vendor Code

RESET

PN

IOCHARGE

REVISION

ITERM

VBUS_

CONTROL

5H

6H

Reserved

PROD

IO_LEVEL VBUS_CON

SP

VBUSLIM

SAFETY

ISAFE

Reserved

VSAFE

POST_

CHARGING

7H

Reserved

VBUS_LOAD

PC_EN

PC_IT

MONITOR0

MONITOR1

NTC

10H ITERM_CMP VBAT_CMP

LINCHG

POK_B

T_120

DIS_LEVEL

NTC_OK

Reserved

ICHG

NOBAT

NTC4

IBUS

PC_ON

NTC3

VBUS_VALID

Reserved

NTC2

CV

11H

12H

GATE

Reserved

VBAT

Reserved

NTC1

TEMP_DIS

Reserved

WD_CONTROL 13H

RESTART FA

Reserved

Reserved EN_REG

WD_DIS

Reserved

RESTART

www.fairchildsemi.com

FAN54053 • Rev. 1.4

31

Table 17. Register Bit Definitions

This table defines the operation of each register bit. Default values are in bold text.

Bit

Name

Value Type

Description

Register Address: 00h(0) Default Value=0100 0000 (40h)

CONTROL0

Writing a 1 resets the t_32Stimer; writing a 0 has no effect.

Reading this bit always returns 0

0

7

6

TMR_RST

W

Prevents STAT pin from going LOW during charging; STAT pin still pulses to

enunciate faults

0

R/W

EN_STAT

1

Enables STAT pin to be LOW when IC is charging

Bit

STAT Description

5

0

1

4

0

1

0

1

Standby

00

5:4

3

STAT

R

PWM enabled. Charging is occurring if CE# = 0

Charge Done

Fault

0

IC is not in Boost Mode

IC is in Boost Mode

Fault Bit

BOOST

1

Type

FAULT Description

2

1

0

R

Normal (No Fault)

VBUS OVP

0

1

0

1

0

1

0

1

0

1

0

1

RC Sleep Mode

See

table

to the

right.

R

Poor Input Source

000

2:0

FAULT

Battery OVP

Thermal Shutdown

RC Timer Fault

RC No Battery

For Boost Mode faults, see Table 13.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

32

Bit

Name

Value Type

Description

Default Value=0011 0100 (34h)

CONTROL1

Register Address: 01h(1)

Input current limit

Bit

I_BUSLIM(mA)

7

0

1

6

0

1

0

1

00

11

7:6

5:4

IBUSLIM

R/W

475

760

1080

No Limit

Weak battery voltage threshold

Bit

V_LOWV(V)

5

0

1

4

0

1

0

1

VLOWV

3.4

3.5

3.6

3.7

0

1

3

2

TE

R/W Setting the TE bit to a 1 will enable Charge Termination.

This is an active low bit and by setting the bit to a “0” will enable Charging. When

CE#

R/W

the bit is reset, it will return to the “1” state and charging will be disabled.

Setting this bit to a “1” puts the device in

High Impendance mode.

0

1

0

HZ_MODE

R/W

See Table 11

The device is in Charge Mode when the

R/W OPA_MODE bit = 0 and in Boost Operation

when the bit = 1.

OPA_MODE

www.fairchildsemi.com

FAN54053 • Rev. 1.4

33

Bit

Name

Value Type

Description

Default Value=0000 1000 (08h)

OREG

Register Address: 02h(2)

Charger output “float” voltage; programmable from 3.51 to 4.45 V in 20 mV

increments.

Dec

0

1

2

3

4

5

6

7

Hex

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

V_OREG

3.51

3.53

3.55

3.57

3.59

3.61

3.63

3.65

3.67

3.69

3.71

3.73

3.75

3.77

3.79

3.81

Dec

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Hex

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

V_OREG

3.83

3.85

3.87

3.89

3.91

3.93

3.95

3.97

3.99

4.01

4.03

4.05

4.07

4.09

4.11

4.13

Dec

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

Hex

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

V_OREG

4.15

4.17

4.19

4.21

4.23

4.25

4.27

4.29

4.31

4.33

4.35

4.37

4.39

4.41

4.43

000010

7:2

OREG

R/W

8

9

10

11

12

13

14

15

47-63 2F-3F 4.45

Indicates that the IC detected a dead battery after VBUS_POR. Writing a 0 to this

bit is ignored.

0

R/W

The IC sets this bit to 1 if a dead battery (V_BAT< V_SHORT) was not detected at

VBUS_POR.

1

DBAT_B

1

If the host sets this bit while the IC is charging the battery and DBAT_B is LOW,

normal Precharge or Fast charging proceeds.

If TE = ”1”, and no battery is detected at I_TERM, the IC turns off the PWM for T_INT

,

then resumes charging and retries Battery Detection. If the battery is still absent,

the process repeats with the “No Battery” fault re-enunciated, and sets the charging

parameters to the default values (see Charge State Flow Chart)

0

EOC

If no battery is detected when a full battery (end of charge) is reached, the PWM

charger stays on, allowing the host processor to continue to run with no battery.

1

IC_INFO

Register Address: 03h(3)

Default Value=1001 0XXX (9Xh)

10

7:6

5:3

2:0

Vendor Code

PN

R

Identifies Fairchild Semiconductor as the IC supplier

Part number bits, see the Ordering Information

010

REV

IC Revision, revision 1.X, where X is the decimal of these three bits

www.fairchildsemi.com

FAN54053 • Rev. 1.4

34

Bit

Name

Value Type

Description

Default Value=1000 0001 (81h)

IBAT

Register Address: 04h(4)

Conditions

Functionality

Setting the RESET bit clears all registers (except

Valid V_BUS, V_BAT> V_LOWVSAFETY and CE#) including WD_DIS and

HZ_MODE.

Setting the RESET bit clears all registers (except

SAFETY) including WD_DIS, HZ_MODE and CE#.

7

RESET

1

W

Valid V_BUS, V_BAT< V_LOWV

Setting the RESET bit clears all registers (except

Absent V_BUS

SAFETY and CE#) including WD_DIS and

HZ_MODE.

Writing a 0 has no effect; read returns 1

Programs the maximum charge current (550 mA default)

Bit

I_OCHARGE(mA)

6

0

1

5

0

1

0

4

0

1

0

1

0

3

0

1

0

1

0

1

0

1

0

1

550

650

750

850

950

1,050

1,150

1,250

1,350

1,450

1,550

0000

6:3

IOCHARGE

R/W

1010-1111

Sets the current used for charging termination

Bit

I_TERM(mA)

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

50

100

150

200

250

300

350

400

001

2:0

ITERM

R/W

www.fairchildsemi.com

FAN54053 • Rev. 1.4

35

Bit

Name

Value Type

Description

Default Value=001X X100

VBUS_CONTROL

Register Address: 05h(5)

0

1

7

6

Reserved

PROD

R

This bit always returns 0

R/W Charger operates in Normal Mode.

Charger operates in Production Test Mode.

Battery current is controlled by I_OCHARGEand I_BUSLIMbits while Fast Charging. During

Precharge Mode, battery current is limited to 450 mA when I_OCHARGE< 750 mA and

730 mA when I_OCHARGE> 750 mA. I_BUSLIMbits must be set to “10” or “11” or

IO_LEVEL current will remain at 200 mA.

0

R/W

5

IO_LEVEL

1

Battery current control is set to 200 mA for Fast Charge and Precharge Mode.

1 Indicates that V_BUSis above 4.4 V (rising) or 3.8 V (falling). When VBUS_CON

changes from 0 to 1, a STAT pulse occurs.

4

3

VBUS_CON

VLIM

R

0

1

VBUS control loop is not active (V_BUSis able to stay above V_BUSLIM

)

VBUS control loop is active and V_BUSis being regulated to V_BUSLIM

VBUS control voltage reference

Bit

V_BUSLIM(V)

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4.213

4.293

4.373

4.453

4.533

4.613

4.693

4.773

100

2:0

VBUSLIM

R/W

SAFETY

Register Address: 06h(6)

Default Value=0100 0000 (4Ah)

Sets the maximum I_OCHARGEvalue used by the control circuit

Bit

I_OCHARGE(MAX)(mA)

7

0

1

6

0

1

0

5

0

1

0

1

0

4

0

1

0

1

0

1

0

1

0

1

550

650

750

850

950

1,050

1,250

1,350

1,450

1,550

0110

7:4

ISAFE

R/W

1010-1111

Sets the maximum V_OREGused by the control circuit

Bit

V_OREG(MAX)(V)

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4.21

4.23

4.25

4.27

4.29

4.31

4.33

4.35

4.37

4.39

4.41

4.43

4.45

1010

3:0

VSAFE

R/W

1100-1111

www.fairchildsemi.com

FAN54053 • Rev. 1.4

36

Bit

POST_CHARGING

7:6 Reserved

Name

Value Type

Description

Default Value=0000 0001 (01h)

Register Address: 07h(7)

00

R

These bits always return 0

After charger termination, in the charge done state, these bits control VBUS loading

to improve detection of AC power removal from the AC adapter.

[5:4]

00

VBUS Loading in Charge Done State:

00

5:4 VBUS_LOAD

R/W

None

Load VBUS for 4 ms every two seconds

Load VBUS for 131 ms every two seconds

Load VBUS for 135 ms every two seconds

01

10

11

0

R/W Post charging or background charging feature is disabled

Post charging or background charging feature is enabled

Sets the termination current for post charging

3

PC_EN

PC_IT

1

Bit

PC_IT (mA)

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

50

100

150

200

250

300

350

400

001

2:0

R/W

MONITOR0

Register Address: 10h (16)

Default Value=XXX0 XXXX (XXh)

7

6

5

ITERM_CMP

R

ITERM comparator output, 1 when I_CHARGE> I_TERM reference

Output of VBAT comparator, 1 when V_BAT< V_BUS

VBAT_CMP

LINCHG

1 when 30 mA linear charger ON (V_BAT< V_SHORT

)

Thermal regulation comparator, 1 when the die temperature is greater than 120°C.

If battery is being charged in Precharge mode, the charge current is limited to

200 mA and in Fast Charge, 550 mA.

4

T_120

R

3

2

1

ICHG

IBUS

R

0 indicates the ICHARGE loop is controlling the battery charge current.

0 indicates the IBUS (input current) loop is controlling the battery charge current.

1 indicates V_BUShas passed validation and is capable of charging.

VBUS_VALID

1 indicates the constant-voltage loop (OREG) is controlling the charger and all

current limiting loops have released.

0

CV

R

MONITOR1

Register Address: 11h (17)

Default Value=XX1X XXX0

The GATE bit indicates the state of the GATE pin. If the bit is “0”, the pin is low,

driving the PFET, Q5 on. A “1” will disable Q5, but current can still flow from battery

to the system through Q5’s body diode.

7

GATE

R

A “1” indicates V_BAT> V_BATMINin PP charging or V_BAT> V_LOWVin PWM charging. A

“0” indicates V_BAT< V_BATMINin PP charging or V_BAT< V_LOWVin PWM charging.

6

5

VBAT

POK_B indicates the state of the POK_B pin (see section on POK_B). This bit can

R/W be set to a 1 if VBAT has fallen below V_LOWV, in turn the open drain POK_B pin will

be Hi-Z.

1

POK_B

This pin indicates the state of the DIS pin. A “1” indicates the DIS pin is high and the

device is in a Hi-Z state on the input and the PWM controller is not running.

4

3

DIS_LEVEL

NOBAT

R

A “1” on this bit indicates that the device has determined there is no battery

connected.

R

2

PC_ON

R

A “1” on this bit indicates that Post charging (background charging) is in progress.

1:0

Reserved

0

These bits always return 0.

www.fairchildsemi.com

FAN54053 • Rev. 1.4

37

Bit

NTC

7:6

Name

Value Type

Description

Default Value=000X XXXX

Register Address: 12H (18)

Reserved

00

R

These bits always return 0.

0

R/W

NTC Temperature measurement results affect charge parameters.

5

TEMP_DIS

NTC Temperature measurement results do not affect charge. Temperature

measurements continue to be updated every second in the NTC1-4 monitor bits.

1

4

3

2

1

0

NTC_OK

NTC4

R

0 if NTC is either shorted to GND, open, or shorted to REF.

1 indicates that NTC is above the T4 threshold.

See Battery Temperature (NTC)

Monitor

NTC3

1 indicates that NTC is above the T3 threshold.

NTC2

1 indicates that NTC is above the T2 threshold.

NTC1

1 indicates that NTC is above the T1 threshold.

WD_CONTROL

Register Address: 13h (19)

This bit always returns 0

This bit always returns 1

This bit always returns 0

This bit always returns 1

Default Value = 0110 1110 (6Eh)

0

1

0

1

7

6

5

4

3

Reserved

R

Reserved

The EN_VREG defaults to a “1” enabling the regulator. To disable the regulator, set

the bit to a “0”.

1

R/W

2

EN_VREG

A “1” disables the Watchdog (t_32s) and t_15MINtimers. Setting the bit to a “0” will

enable the timers (See Safety Timer Section for further information).

1

R/W

1

0

WD_DIS

Reserved

0

R

This bit always returns 0

RESTART

Register Address: FAh (250)

Default Value = 1111 1111 (FFh)

Writing B5h restarts charging when the IC is in the charge done state. This register

reads back FF.

7:0 RESTART

W

www.fairchildsemi.com

FAN54053 • Rev. 1.4

38

PCB Layout Recommendation

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. Power and ground pins should be

routed directly to their bypass capacitors using the top

copper layer. The copper area connecting to the IC should

be maximized to improve thermal performance.

Figure 46. PCB Layout Recommendation

Product-Specific Dimensions

Product

D

E

X

Y

FAN54053UCX

2.40 ±0.030

2.00 ±0.030

0.180

0.380

www.fairchildsemi.com

FAN54053 • Rev. 1.4

39

0.03 C

F

E

A

2X

1.60

0.40

B

(Ø0.200)

Cu Pad

A1

BALL A1

INDEX AREA

(Ø0.300)

Solder Mask

1.60

D

0.40

0.03 C

RECOMMENDED LAND PATTERN

(NSMD PAD TYPE)

2X

TOP VIEW

0.06 C

0.625

0.378±0.018

0.208±0.021

0.547

0.05 C

E

SIDE VIEWS

C

SEATING PLANE

D

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

1.60

0.40

0.005

C A B

Ø0.260±0.02

25X

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E

D

C

B

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

±39 MICRONS (547-625 MICRONS).

1.60

0.40

(Y) ±0.018

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

A

F

2

3

5

4

1

G. DRAWING FILENAME: MKT-UC025AArev3.

(X) ±0.018

BOTTOM VIEW

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1


型号：	FAN54053UCX
厂家：	ONSEMI
描述：	高能效，1.55 A，带功率路径的锂离子开关充电器，USB-OTG，方案占位小开关
文件：	总42页 (文件大小：1818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN54053UCX [ONSEMI]

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