FDG6332C [ONSEMI]
20V N&P沟道Power Trench® MOSFET;
| 型号： | FDG6332C |
| 厂家： | 
ONSEMI |
| 描述： | 20V N&P沟道Power Trench® MOSFET PC 开关 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET– N & P-Channel,
POWERTRENCH)
S
G
D
D
G
S
Pin 1
20 V
SC−88/SC70−6/SOT−363
CASE 419B−02
FDG6332C
PIN CONNECTIONS
General Description
The N & P−Channel MOSFETs are produced using onsemi
advanced POWERTRENCH process that has been especially tailored
to minimize on−state resistance and yet maintain superior switching
performance.
These devices have been designed to offer exceptional power
dissipation in a very small footprint for applications where the bigger
more expensive TSSOP−8 and SSOP−6 packages are impractical.
1
2
3
6
5
4
Complementary
Features
• Q1 0.7 A, 20 V
MARKING DIAGRAM
♦ R
♦ R
=300 mW @ V = 4.5 V
GS
DS(ON)
= 400 mW @ V = 2.5 V
DS(ON)
GS
• Q2 −0.6 A, −20 V
32M
♦ R
♦ R
= 420 mW @ V = −4.5 V
GS
DS(ON)
= 630 mW @ V = −2.5 V
DS(ON)
GS
• Low Gate Charge
32
M
= Specific Device Code
= Assembly Operation Month
• High Performance Trench Technology for Extremely Low R
DS(ON)
• SC70−6 Package: Small Footprint (51% Smaller than SSOT−6); Low
Profile (1 mm Thick)
• These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
• DC−DC Converter
• Load Switch
• LCD Display Inverter
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain−Source Voltage
Gate−Source Voltage
Q1
20
Q2
−20
12
Units
V
V
V
A
DSS
GSS
V
12
I
D
Drain Current
Continuous
(Note 1)
0.7
−0.6
Pulsed
2.1
−2
P
D
Power Dissipation for Single
Operation (Note 1)
0.3
W
T , T
Operating and Storage Junction
Temperature Range
−55 to 150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
May, 2023 − Rev. 5
FDG6332C/D
FDG6332C
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
R
Thermal Resistance, Junction−to−Ambient (Note 1)
415
_C/W
q
JA
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design. R
q
JA
= 415°C/W on
q
q
JC
CA
minimum pad mounting on FR−4 board in still air.
ORDERING INFORMATION
†
Device Marking
Device
Reel Size
Tape Width
Shipping
32
FDG6332C
7”
8 mm
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
Q1
Q2
Q1
Q2
Q1
Q2
20
−20
−
−
−
−
V
V
I
= 0 V, I = 250 mA
DSS
GS
D
= 0 V, I = −250 mA
−
GS
D
DBV
/ DT
Breakdown Voltage Temperature
Coefficient
= 250 mA, Referenced to 25_C
= −250 mA, Referenced to 25_C
14
−14
−
−
mV/_C
mA
DSS
J
D
I
D
−
−
I
Zero Gate Voltage Drain Current
V
= 16V, V = 0 V
−
1
DSS
DS
DS
GS
V
= −16 V, V = 0 V
−
−
−1
100
100
GS
I
I
/ I
Gate−Body Leakage, Forward
Gate−Body Leakage, Reverse
V
DS
V
GS
=
=
12 V, V = 0 V
−
−
nA
nA
GSSF GSSR
GS
/ I
12 V, V = 0 V
−
−
GSSF GSSR
DS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
V
GS(th)
Q1
Q2
Q1
Q2
Q1
0.6
−0.6
−
1.1
−1.2
−2.8
3
1.5
−1.5
−
V
V
= V , I = 250 mA
GS D
DS
V
I
= V , I = −250 mA
GS D
DS
DV
/ DT
Gate Threshold Voltage
Temperature Coefficient
= 250 mA, Referenced to 25_C
= −250 mA, Referenced to 25_C
mV/_C
mW
GS(th)
J
D
I
D
−
−
R
Static Drain−Source
On−Resistance
V
GS
V
GS
V
GS
V
GS
V
GS
V
GS
= 4.5 V, I = 0.7 A
−
180
293
247
300
470
400
300
400
442
420
630
700
DS(on)
D
= 2.5 V, I = 0.6 A
−
D
= 4.5 V, I = 0.7 A, T = 125_C
−
D
J
Q2
= −4.5 V, I = −0.6 A
−
D
= −2.5 V, I = −0.5 A
−
D
= −4.5 V, I = −0.6 A,
−
D
T = 125_C
J
g
Forward Transconductance
Q1
Q2
Q1
Q2
V
DS
V
DS
V
GS
V
GS
= 5 V, I = 0.7 A
−
−
2.8
1.8
−
−
−
−
−
S
A
FS
D
= −5 V, I = −0.6 A
D
I
On−State Drain Current
= 4.5 V, V = 5 V
1
D(on)
DS
= −4.5 V, V = −5 V
−2
−
DS
DYNAMIC CHARACTERISTICS
C
Input Capacitance
Q1
Q2
Q1
Q2
V
DS
V
DS
V
DS
V
DS
= 10 V, V = 0 V, f = 1.0 MHz
−
−
−
−
113
114
34
−
−
−
−
pF
pF
iss
GS
= −10 V, V = 0 V, f = 1.0 MHz
GS
C
Output Capacitance
= 10 V, V = 0 V, f = 1.0 MHz
GS
oss
= −10 V, V = 0 V, f = 1.0 MHz
24
GS
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2
FDG6332C
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
C
Reverse Transfer Capacitance
Q1
Q2
V
V
= 10 V, V = 0 V, f = 1.0 MHz
−
−
16
9
−
−
pF
rss
DS
GS
= −10 V, V = 0 V, f = 1.0 MHz
DS
GS
SWITCHING CHARACTERISTICS (Note 2)
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
For Q1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
5.5
7
10
11
15
25
18
12
3
ns
ns
d(on)
V
DS
V
GS
= 10 V, I = 1 A,
D
= 4.5 V, R
= 6 W
GEN
t
r
For Q2
V
DS
V
GS
= −10 V, I = −1 A,
= −4.5 V, R
14
D
= 6 W
GEN
t
9
ns
d(off)
6
t
f
1.5
1.7
1.1
1.4
0.24
0.3
0.3
0.4
ns
3.4
1.5
2
Q
For Q1
nC
nC
nC
g
V
DS
V
GS
= 10 V, I = 0.7 A,
= 4.5 V, R
D
= 6 W
GEN
Q
−
gs
For Q2
V
DS
V
GS
= −10 V, I =−0.6 A,
= −4.5 V, R
D
−
= 6 W
GEN
Q
−
gd
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Drain−Source
Q1
Q2
Q1
Q2
−
−
−
−
−
−
0.25
−0.25
1.2
A
V
S
Diode Forward Current
V
SD
Drain−Source Diode Forward
Voltage
V
V
= 0 V, I = 0.25 A (Note 2)
0.74
−0.77
GS
S
= 0 V, I = −0.25 A (Note 2)
−1.2
GS
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%
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3
FDG6332C
TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL
4
3
2
1
0
1.8
V
GS = 4.5 V
3.0 V
3.5 V
1.6
2.5 V
VGS = 2.5 V
1.4
3.0 V
1.2
3.5 V
2.0 V
4.0 V
4.5 V
1
0.8
0
1
2
3
4
0
1
2
3
4
I
D , DRAIN CURRENT (A)
VDS , DRAIN−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
1.6
0.8
ID = 0.7 A
ID = 0.4 A
VGS = 4.5 V
1.4
1.2
1
0.6
0.4
0.2
0
TA = 125
C
°
°
TA = 25
C
0.8
0.6
1
2
3
4
5
−50
−25
0
25
50
75
100
125
150
V
GS, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
°
J
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
2.5
10
VGS = 0 V
TA = −55
C
°
VDS = 5 V
25° C
2
1.5
1
1
°
TA = 125
C
125° C
25° C
0.1
0.01
−55°C
0.5
0
0.001
0.0001
0.5
1
1.5
2
2.5
3
0
0.2
V
0.4
0.6
0.8
1
1.2
V
GS , GATE TO SOURCE VOLTAGE (V)
SD , BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature
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4
FDG6332C
TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL (CONTINUED)
200
5
4
3
2
1
0
V
DS = 5 V
f = 1MHz
GS = 0 V
ID = 0.7 A
10 V
V
150
100
50
15 V
CISS
COSS
CRSS
0
0
5
10
15
20
0
0.4
0.8
1.2
1.6
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
10
10
8
SINGLE PULSE
R
qJA = 415°C/W
TA = 25°C
RDS(ON) LIMIT
100 ms
1 ms
10 ms
1
0.1
6
100 ms
1 s
4
VGS = 4.5 V
SINGLE PULSE
DC
R
qJA = 415 °C/W
A = 25°C
2
T
0
0.01
0.001
0.01
0.1
1
10
100
0.1
1
10
100
t1, TIME (sec)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum Power
Dissipation
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FDG6332C
TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL
2
1.6
1.2
0.8
0.4
0
1.8
V
GS = −4.5 V
−3.5 V
−3.0 V
VGS = −2.5 V
1.6
1.4
1.2
1
−2.5 V
−3.0 V
−3.5 V
−4.0 V
−2.0 V
−4.5 V
0.8
0
1
2
3
4
0
0.5
1
1.5
2
−VDS, DRAIN−SOURCE VOLTAGE (V)
−ID , DRAIN CURRENT (A)
Figure 11. On−Region Characteristics
Figure 12. On−Resistance Variation
with Drain Current and Gate Voltage
1.4
1.3
1.2
1.1
1
1.2
1
ID = −0.6A
VGS = −4.5V
I
D = −0.3 A
0.8
0.6
0.4
0.2
°
TA = 125
C
°
TA = 25 C
0.9
0.8
0.7
1
2
3
4
5
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (oC)
−VGS, GATE TO SOURCE VOLTAGE (V)
Figure 13. On−Resistance Variation with
Figure 14. On−Resistance Variation
with Gate−to−Source Voltage
Temperature
10
1
2
VGS = 0V
TA = −55°C
25°C
125°C
VDS = −5 V
1.5
1
TA = 125°C
0.1
25°C
0.01
0.001
0.0001
−55°C
0.5
0
0
0.2
0.4
0.6
0.8
1
1.2
0.5
1
1.5
2
2.5
3
−VSD , BODY DIODE FORWARD VOLTAGE (V)
−VGS , GATE TO SOURCE VOLTAGE (V)
Figure 15. Transfer Characteristics
Figure 16. Body Diode Forward Voltage
Variation with Source Current and Temperature
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FDG6332C
TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL (CONTINUED)
160
5
4
3
2
1
0
f = 1 MHz
VGS = 0 V
ID = −0.6 A
VDS = −5 V
−10 V
120
−15 V
CISS
80
COSS
40
CRSS
0
0
5
10
15
20
0
0.3
0.6
0.9
1.2
1.5
1.8
−VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 17. Gate Charge Characteristics
Figure 18. Capacitance Characteristics
10
10
SINGLE PULSE
RqJA = 415 C/W
°
8
6
4
2
TA = 25
C
°
100 ms
1 ms
RDS(ON) LIMIT
1
0.1
10 ms
100 ms
1 s
DC
VGS = −4.5 V
SINGLE PULSE
R
qJA = 415°C/W
A = 25 °C
T
0.01
0
0.1
1
10
100
0.001
0.01
0.1
1
10
100
−VDS, DRAIN−SOURCE VOLTAGE (V)
SINGLE PULSE TIME (sec)
Figure 19. Maximum Safe Operating Area
Figure 20. Single Pulse Maximum Power
Dissipation
1
D = 0.5
0.2
0.1
R
R
(t) = r(t) * R
= 415°C/W
0.1
q
q
q
JA
JA
0.05
0.02
0.01
JA
P(pk)
t1
0.01
t 2
SINGLE PULSE
T
− T = P * R
A
(t)
q
JA
J
Duty Cycle, D = t / t
1
2
0.001
0.0001
0.001
0.01
0.1
1
10
100
t1, TIME (sec)
Thermal characterization performed using the conditions described in Note 1.
Transient thermal response will change depending on the circuit board design.
Figure 21. Transient Thermal Response Curve
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 1 OF 2
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© Semiconductor Components Industries, LLC, 2019
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SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 2 OF 2
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相关型号：
FDG6335N_NL
Small Signal Field-Effect Transistor, 0.7A I(D), 20V, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SC-70, 6 PIN
FAIRCHILD
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