FDMA8884 [ONSEMI]
30V单N沟道PowerTrench® MOSFET;
| 型号： | FDMA8884 |
| 厂家： | 
ONSEMI |
| 描述： | 30V单N沟道PowerTrench® MOSFET |
| 文件： | 总6页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2014
FDMA8884
Single N-Channel Power Trench® MOSFET
30 V, 6.5 A, 23 mΩ
Features
General Description
Max rDS(on) = 23 mΩ at VGS = 10 V, ID = 6.5 A
Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 6.0 A
High performance trench technology for extremely low rDS(on)
Fast switching speed
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced Power Trench® process that has
been optimized for rDS(on) switching performance.
Application
RoHS Compliant
Primary Switch
Pin 1
G
D
D
Bottom Drain Contact
D
D
S
D
D
Drain
Source
G
D
D
S
MicroFET 2X2 (Bottom View)
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
30
±20
V
V
(Note 3)
Drain Current -Continuous (Package limited) TC = 25 °C
8.0
ID
-Continuous
-Pulsed
TA = 25 °C
(Note 1a)
6.5
A
25
Power Dissipation
Power Dissipation
Operating and Storage Junction Temperature Range
(Note 1a)
(Note 1b)
1.9
PD
W
0.7
TJ, TSTG
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
(Note 1a)
(Note 1b)
65
°C/W
180
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
7 ’’
Tape Width
8 mm
Quantity
884
FDMA8884
MicroFET 2x2
3000 units
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
30
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
15
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
1
μA
Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V
100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
D = 250 μA, referenced to 25 °C
GS = 10 V, ID = 6.5 A
1.2
1.8
-5
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
mV/°C
V
19
25
25
26
23
30
30
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5 V, ID = 6.0 A
mΩ
VGS = 10 V, ID = 6.5 A, TJ = 125 °C
VDD = 5 V, ID = 6.5 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
339
132
18
450
175
28
pF
pF
pF
Ω
VDS = 15 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
1.1
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
5
10
10
ns
ns
1
VDD = 15 V, ID = 6.5 A,
VGS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
11
1
20
ns
10
ns
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V
5.4
2.7
1.0
0.9
7.5
3.7
nC
nC
nC
nC
Qg(TOT)
VDD = 15 V
D = 6.5 A
I
Qgs
Qgd
Drain-Source Diode Characteristics
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
VGS = 0 V, IS = 6.5 A
IF = 6.5 A, di/dt = 100 A/μs
(Note 2)
0.86
16
4
1.2
28
10
V
ns
nC
Qrr
Reverse Recovery Charge
NOTES:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
θJA
R
is guaranteed by design while R
is determined by the user's board design.
θJC
θCA
a. 65 °C/W when mounted
on a 1 in pad of 2 oz copper.
b. 180 °C/W when mounted on a
minimum pad of 2 oz copper.
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
2
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
25
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
20
VGS = 3.5 V
VGS = 4.5 V
15
VGS = 4 V
VGS = 3.5 V
VGS = 4 V
10
5
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
VGS = 10 V
20
VGS = 6 V
15
0
0.4
0.8
1.2
1.6
2.0
0
5
10
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
1.5
80
ID = 6.5 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
VGS = 10 V
60
40
20
0
ID = 6.5 A
TJ = 125 oC
TJ = 25 oC
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
25
30
PULSE DURATION = 80 μs
VGS = 0 V
DUTY CYCLE = 0.5% MAX
10
20
15
10
5
VDS = 5 V
TJ = 150 o
C
1
TJ = 25 o
C
TJ = 150 o
C
TJ = 25 o
C
0.1
0.01
TJ = -55 o
C
TJ = -55 o
C
0
1
2
3
4
5
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
3
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
10
500
100
ID = 6.5 A
Ciss
8
VDD = 10 V
VDD = 15 V
6
Coss
VDD = 20 V
4
2
0
f = 1 MHz
= 0 V
Crss
V
GS
10
0
1
2
3
4
5
6
0.1
1
10
30
Q , GATE CHARGE (nC)
g
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
30
10
200
100
SINGLE PULSE
θJA = 180 oC/W
A = 25 oC
R
T
100 μs
1
0.1
THIS AREA IS
LIMITED BY r
1 ms
10
DS(on)
10 ms
SINGLE PULSE
TJ = MAX RATED
100 ms
1 s
R
θJA = 180 oC/W
10 s
DC
1
T
A = 25 oC
0.01
0.5
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
103
100
0.01
0.1
1
10
100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
Figure10. Single Pulse Maximum
Power Dissipation
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
PDM
0.05
0.02
0.01
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
RθJA = 180 oC/W
0.01
0.005
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
100
10
1000
Figure 11. Junction-to-Ambient Transient Thermal Response Curve
Figure 12.
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
4
www.fairchildsemi.com
Dimensional Outline and Pad Layout
0.05 C
2.0
A
2X
B
2.0
1.70
1.00
(0.20)
No Traces
allowed in
this Area
0.05 C
4
6
PIN#1 IDENT
0.10 C
TOP VIEW
2X
1.05
2.30
ꢀꢁꢂꢃꢀꢁꢀꢃ
ꢀꢁꢄꢀꢀꢁꢀꢃ
0.47(6X)
0.08 C
1
3
SIDE VIEW
C
ꢀꢁꢀꢄꢃꢀꢁꢀꢄꢃ
SEATING
PLANE
0.40(6X)
0.65
RECOMMENDED
LAND PATTERN OPT 1
ꢄꢁꢀꢀꢀꢁꢀꢃ
(0.15)
(0.50)
ꢀꢁꢇꢀꢀꢁꢀꢃ
(0.20)4X
ꢀꢁꢉꢀꢀꢁꢀꢃ
PIN #1 IDENT
1.70
0.45
(0.20)
1
3
1.00
ꢀꢁꢄꢅꢀꢁꢀꢃ
(6X)
ꢀꢁꢃꢆꢀꢁꢀꢃ
ꢈꢁꢀꢀꢀꢁꢀꢃ
4
6
(0.50)
ꢄꢁꢀꢀꢀꢁꢀꢃ
1.05
0.66
2.30
6
4
(6X)
C A B
C
ꢀꢁꢇꢀꢀꢁꢀꢃ
0.10
0.47(6X)
0.65
1
3
1.30
BOTTOM VIEW
0.05
0.40(7X)
RECOMMENDED
LAND PATTERN OPT 2
0.65
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM
TO JEDEC MO-229 REGISTRATION
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP06Lrev4.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, spe-
cifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDEB-C06
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
5
www.fairchildsemi.com
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intended to be an exhaustive list of all such trademarks.
AccuPower™
AX-CAP *
BitSiC™
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
F-PFS™
FRFET
®*
®
®
®
tm
®
Global Power ResourceSM
GreenBridge™
Green FPS™
PowerTrench
PowerXS™
Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
®
TinyCalc™
®
Green FPS™ e-Series™
Gmax™
GTO™
®
TinyLogic
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
Current Transfer Logic™
IntelliMAX™
®
DEUXPEED
ISOPLANAR™
Marking Small Speakers Sound Louder
and Better™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MicroPak2™
MillerDrive™
MotionMax™
Dual Cool™
TranSiC™
®
EcoSPARK
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
TriFault Detect™
TRUECURRENT *
EfficentMax™
ESBC™
®
μSerDes™
SMART START™
®
Solutions for Your Success™
®
®
SPM
Fairchild
®
®
STEALTH™
SuperFET
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS
SyncFET™
Sync-Lock™
UHC
Fairchild Semiconductor
FACT Quiet Series™
®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
VoltagePlus™
XS™
®
®
mWSaver
OptoHiT™
OPTOLOGIC
OPTOPLANAR
FACT
FAST
®
®
FastvCore™
FETBench™
FPS™
®
®
仙童™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Preliminary
First Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
No Identification Needed
Obsolete
Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I68
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDMA8884 Rev.C5
6
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