FDMA908PZ [ONSEMI]
单 P 沟道，PowerTrench® MOSFET，-12V，-12A，12.5mΩ;
| 型号： | FDMA908PZ |
| 厂家： | 
ONSEMI |
| 描述： | 单 P 沟道，PowerTrench® MOSFET，-12V，-12A，12.5mΩ |
| 文件： | 总7页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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ꢀ
V
R
MAX
I MAX
D
MOSFET – Single, P-Channel,
POWERTRENCH)
DS
DS(on)
−12 V
12.5 mW @ −4.5 V
18 mW @ −2.5 V
28 mW @ −1.8 V
−12 A
-12 V, -12 A, 12.5 mW
FDMA908PZ
Pin 1
D
D
G
Source
General Description
Drain
This device is designed specifically for battery charge or load
switching in cellular handset and other ultraportable applications. It
features a MOSFET with low on−state resistance and zener diode
protection against ESD. The MicroFET 2X2 package offers
exceptional thermal performance for its physical size and is well
suited to linear mode applications.
D
D
S
Bottom
Features
DFN6 2x2, 0.65P
(MicroFET 2x2)
CASE 506DT
• Max R
• Max R
• Max R
= 12.5 mW at V = −4.5 V, I = −12 A
GS D
DS(on)
DS(on)
DS(on)
= 18 mW at V = −2.5 V, I = −10 A
GS
D
= 28 mW at V = −1.8 V, I = −8 A
GS
D
MARKING DIAGRAM
• Low Profile − 0.8 mm Maximum in the New Package MicroFET
2x2 mm
• HBM ESD Protection Level > 2.8 kV Typical (Note 3)
• Free from Halogenated Compounds and Antimony Oxides
• This Device is Pb−Free, Halide Free and is RoHS Compliant
&Z&2&K
908
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
A
&Z = Assembly Plant Code
&2 = 2−Digit Date Code
&K = 2−Digits Lot Run Traceability Code
908 = Specific Device Code
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
Unit
V
V
DS
GS
−12
V
8
V
I
D
Drain Current
− Continuous (Note 1a)
− Pulsed
A
PIN ASSIGNMENT
T = 25°C
A
−12
−40
P
D
Power Dissipation
− (Note 1a)
− (Note 1b)
W
D
D
T = 25°C
2.4
0.9
A
T = 25°C
A
D
S
D
G
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
ORDERING INFORMATION
Symbol
Parameter
Ratings
Unit
†
Device
FDMA908PZ
Package
Shipping
3000 /
Tape & Reel
Thermal Resistance, Junction to Ambient
(Note 1a)
52
°C/W
R
q
JA
DFN6
(Pb−Free,
Halide Free)
R
Thermal Resistance, Junction to Ambient
(Note 1b)
145
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
April, 2023 − Rev. 5
FDMA908PZ/D
FDMA908PZ
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
I
I
= −250 mA, V = 0 V
−12
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= −250 mA, referenced to 25°C
−
−10
mV/°C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= −9.6 V, V = 0 V
−
−
−
−
−1
mA
mA
DSS
GSS
DS
GS
I
=
8 V, V = 0 V
10
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = −250 mA
−0.4
−0.6
−1
V
GS(th)
GS
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
= −250 mA, referenced to 25°C
−
2.8
−
mV/°C
DVGS(th)
DTJ
D
R
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
GS
V
DD
= −4.5 V, I = −12 A
−
−
−
−
−
10
13
18
13
63
12.5
18
28
16
−
mW
DS(on)
D
= −2.5 V, I = −10 A
D
= −1.8 V, I = −8 A
D
= −4.5 V, I = −12 A, T = 125°C
D
J
g
FS
= −5 V, I = −12 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −6 V, V = 0 V, f = 1 MHz
−
−
−
2638
649
3957
974
pF
pF
pF
iss
GS
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
602
903
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
= −6 V, I = −12 A, V = −4.5 V,
GEN
−
−
−
−
−
−
−
11
12
21
23
223
121
34
−
ns
ns
d(on)
DD
D
GS
R
= 6 W
t
r
t
Turn−Off Delay Time
Fall Time
131
71
ns
d(off)
t
f
ns
Q
g
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
DD
= −6 V, I = −12 A, V = −4.5 V
24
nC
nC
nC
D
GS
Q
3.4
5.3
gs
gd
Q
−
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
V
V
= 0 V, I = −2 A (Note 2)
−
−
−
−
−0.6
−0.8
26
−1.2
−1.2
42
V
SD
GS
S
= 0 V, I = −12 A (Note 2)
GS
S
t
Reverse Recovery Time
I = −12 A, di/dt = 100 A/ms
F
ns
rr
Q
Reverse Recovery Charge
8.5
17
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
JC
q
q
JA
by design while R
is determined by the user’s board design.
q
CA
a. 52°C/W when mounted
b. 145°C/W when mounted
on a minimum pad of 2 oz copper
2
on a 1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
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2
FDMA908PZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
3
40
30
20
V
V
= −4.5 V
= −3 V
GS
GS
V
GS
= −1.5 V
V
GS
= −2.5 V
2
V
GS
= −1.8 V
V
GS
= −1.8 V
V
GS
= −3 V
V
GS
= −2.5 V
1
0
V
= −1.5 V
GS
V
= −4.5 V
GS
10
0
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
0.0
0.5
1.0
1.5
2.0
0
10
20
−I , Drain Current (A)
30
40
−V , Drain to Source Voltage (V)
DS
D
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs. Drain
Current and Gate Voltage
60
1.4
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
I
V
= −12 A
D
= −4.5 V
GS
1.3
1.2
1.1
1.0
0.9
0.8
0.7
I
D
= −12 A
40
20
0
T = 125°C
J
T = 25°C
J
4.5
−75 −50 −25
0
25
50
75 100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
T , Junction Temperature (5C)
J
−V , Gate to Source Voltage (V)
GS
Figure 3. Normalized On−Resistance
Figure 4. On−Resistance vs. Gate to Source
vs. Junction Temperature
Voltage
100
10
40
30
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
V
DS
= −5 V
T = 150°C
J
T = 25°C
J
1
T = 150°C
J
20
10
0
0.1
T = 25°C
J
T = −55°C
J
0.01
0.001
T = −55°C
J
0.0
0.4
0.8
1.2
0.0
0.5
1.0
1.5
2.0
−V , Body Diode Forward Voltage (V)
SD
−V , Gate to Source Voltage (V)
GS
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage
vs. Source Current
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3
FDMA908PZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
5000
4.5
3.0
1.5
0.0
I
D
= −12 A
C
iss
V
= −4 V
DD
V
DD
= −6 V
C
oss
1000
V
DD
= −8 V
C
rss
f = 1 MHz
V
GS
= 0 V
300
0.1
0
5
10
15
20
25
1
10
20
Q , Gate Charge (nC)
g
−V , Drain to Source Voltage (V)
DS
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain to Source
Voltage
−3
60
10
10
V
DS
= 0 V
−4
10
10
−5
1 ms
T = 125°C
J
10 ms
−6
−7
−8
−9
10
10
10
10
1
100 ms
THIS AREA IS
LIMITED BY R
DS(on)
1 s
10 s
DC
T = 25°C
J
SINGLE PULSE
T = MAX RATED
0.1
J
R
= 145°C/W
CURVE BENT TO
MEASURED DATA
q
JA
T = 25°C
A
−10
0.01
10
50
5
0.1
1
0
10
15
10
0.01
−V , Gate to Source Voltage (V)
GS
−V , Drain to Source Voltage (V)
DS
Figure 9. Gate Leakage Current
vs. Gate to Source Voltage
Figure 10. Forward Bias Safe Operating Area
100
SINGLE PULSE
R
= 145°C/W
q
JA
T = 25°C
A
10
1
0.1
10
−2
−1
−3
10
10
1
10
100
1000
t, Pulse Width (s)
Figure 11. Single Pulse Maximum Power Dissipation
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4
FDMA908PZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
= 145°C/W
(Note 1b)
NOTES:
DUTY CYCLE: D = t / t
R
q
JA
1
2
PEAK T = P
× Z
× R
+ T
JA A
q
q
J
DM
JA
0.01
−2
−1
−3
10
10
1
10
100
10
1000
t, Rectangular Pulse Duration (s)
Figure 12. Junction−to−Ambient Transient Thermal Response Curve
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
MicroFET is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN6 2x2, 0.65P
CASE 506DT
ISSUE O
DATE 31 JUL 2016
2.05
A
(0.20)
(0.45)
0.05
C
B
2X
1.00
6
5
4
2.05
2.30
0.66
1.05
1.35
0.05
C
0.475(6X)
0.65
PIN #1 LOCATION
0.8 0.05
2X
TOP VIEW
1
2
3
0.40 (6X)
RECOMMENDED LAND PATTERN
0.10
C
0.20 0.05
C
Pin #
Function
Drain
0.08
C
1
2
3
4
5
6
7
8
Drain
0.025 0.025
Gate
SEATING
PLANE
Source
Drain
SIDE VIEW
Drain
Drain
Source
2.05 0.05
0.90 0.10
(0.200) 4X
NOTES:
(0.15)
(0.50)
(0.30)
PIN #1 IDENT
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
1
2
3
8
0.61 0.05
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
0.265 0.065
(6X)
1.00 0.05
2.05 0.05
7
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
(0.50)
0.65
5
4
6
0.30 0.05 (6X)
0.10
0.05
C A B
C
1.30
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13616G
DFN6 2X2, 0.65P
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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© Semiconductor Components Industries, LLC, 2019
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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