FDMC7572S [ONSEMI]
N 沟道，Power Trench® SyncFET™，25V，40A，3.15mΩ;
| 型号： | FDMC7572S |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，Power Trench® SyncFET™，25V，40A，3.15mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2011
FDMC7572S
N-Channel Power Trench® SyncFETTM
25 V, 40 A, 3.15 mΩ
Features
General Description
Max rDS(on) = 3.15 mΩ at VGS = 10 V, ID = 22.5 A
The FDMC7572S has been designed to minimize losses in
power conversion application. Advancements in both silicon and
package technologies have been combined to offer the lowest
rDS(on) while maintaining excellent switching performance. This
device has the added benefit of an efficient monolithic Schottky
body diode.
Max rDS(on) = 4.7 mΩ at VGS = 4.5 V, ID = 18 A
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
SyncFET Schottky Body Diode
100% UIL Tested
Applications
Synchronous Rectifier for DC/DC Converters
RoHS Compliant
Notebook Vcore/ GPU low side switch
Networking Point of Load low side switch
Telecom secondary side rectification
Bottom
S
Top
Pin 1
D
D
D
G
5
6
7
8
4
3
2
1
S
S
S
S
S
G
D
D
D
D
D
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
25
±20
V
V
(Note 4)
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
TC = 25 °C
C = 25 °C
40
T
103
ID
A
TA = 25 °C
(Note 1a)
(Note 3)
22.5
120
-Pulsed
EAS
Single Pulse Avalanche Energy
Power Dissipation
84
mJ
W
TC = 25 °C
TA = 25 °C
52
PD
Power Dissipation
(Note 1a)
2.3
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
2.4
53
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMC7572S
FDMC7572S
Power 33
3000 units
1
©2011 Fairchild Semiconductor Corporation
FDMC7572S Rev.C1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 1 mA, VGS = 0 V
D = 10 mA, referenced to 25 °C
VDS = 20 V, VGS = 0 V
25
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
21
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
500
100
μA
Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 1 mA
D = 10 mA, referenced to 25 °C
GS = 10 V, ID = 22.5 A
1.2
1.7
-5
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
mV/°C
V
2.5
3.6
3.5
122
3.15
4.7
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5 V, ID = 18 A
mΩ
VGS = 10 V, ID = 22.5 A, TJ = 125 °C
VDS = 5 V, ID = 22.5 A
4.5
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
2031
596
134
1.1
2705
795
205
2.4
pF
pF
pF
Ω
VDS = 13 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
11
3.6
26
3
22
10
41
10
44
20
ns
ns
VDD = 13 V, ID = 22.5 A,
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V
31
14
6.5
3.9
nC
nC
nC
nC
Qg
VDD = 13 V
ID = 22.5 A
Qgs
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 22.5 A
(Note 2)
(Note 2)
0.79
0.47
24
1.2
0.8
39
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 2 A
trr
Reverse Recovery Time
ns
IF = 22.5 A, di/dt = 300 A/μs
Qrr
Reverse Recovery Charge
19
34
nC
NOTES:
2
1. R
is determined with the device mounted on a 1in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
θCA
θJA
θJC
the user's board design.
125 °C/W when mounted on
a minimum pad of 2 oz copper
53 °C/W when mounted on a
1 in pad of 2 oz copper
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. E of 84 mJ is based on starting T = 25 °C, L = 1 mH, I = 13 A, V = 23 V, V = 10 V. 100% test at L = 0.3 mH, I = 20 A.
AS
J
AS
DD
GS
AS
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
FDMC7572S Rev.C1
www.fairchildsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted
8
7
6
5
4
3
2
1
0
120
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
VGS = 2.5 V
VGS = 3 V
VGS = 3.5 V
90
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
60
VGS = 3.5 V
VGS = 4.5 V
30
VGS = 2.5 V
VGS = 10 V
0
0
30
60
ID, DRAIN CURRENT (A)
90
120
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
Figure 1. On-Region Characteristics
1.5
12
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 22.5 A
ID = 22.5 A
VGS = 10 V
1.4
1.3
1.2
1.1
1.0
0.9
0.8
10
8
6
TJ = 125 o
C
4
2
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
F i gu re 3 . N orma li zed On - Res is ta nc e
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
120
200
100
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
90
60
30
0
TJ = 125 o
C
VDS = 5 V
1
TJ = 25 oC
TJ = 125 o
C
0.1
TJ = 25 o
C
TJ = -55 o
C
0.01
0.001
TJ = -55 o
C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
www.fairchildsemi.com
FDMC7572S Rev.C1
3
Typical Characteristics TJ = 25 °C unless otherwise noted
3000
1000
10
ID = 22.5 A
8
Ciss
VDD = 16 V
VDD = 10 V
6
4
2
0
VDD = 13 V
Coss
f = 1 MHz
100
60
Crss
V
GS
= 0 V
30
0.1
1
10
0
4
8
12
16
20
24
28
32
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
120
80
40
0
30
TJ = 25 oC
VGS = 10 V
10
TJ = 100 o
C
VGS = 4.5 V
TJ = 125 o
C
RθJC = 2.4 oC/W
Limited by Package
1
0.01
0.1
1
10
100
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
200
100
2000
1000
100
10
SINGLE PULSE
θJA = 125 oC/W
TA = 25 o
VGS = 10 V
100 us
R
C
10
1
1 ms
10 ms
100 ms
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
1 s
T
J = MAX RATED
RθJA = 125 oC/W
A = 25 oC
0.1
10 s
DC
T
1
0.01
0.5
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
0.01
0.1
1
10
100
100 1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
www.fairchildsemi.com
FDMC7572S Rev.C1
4
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
R
θJA = 125 oC/W
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
www.fairchildsemi.com
FDMC7572S Rev.C1
5
Typical Characteristics (continued)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 13 shows the reverses recovery
characteristic of the FDMC7572S.
10-2
25
20
TJ = 125 o
C
10-3
10-4
10-5
10-6
15
TJ = 100 o
C
di/dt = 300 A/μs
10
5
0
TJ = 25 o
C
-5
0
50
100
150
200
0
5
10
15
20
25
TIME (ns)
VDS, REVERSE VOLTAGE (V)
Figure 13. FDMC7572S SyncFET body
diode reverse recovery characteristic
Figure 14. SyncFET body diode reverses
leakage versus drain-source voltage
www.fairchildsemi.com
FDMC7572S Rev.C1
6
Dimensional Outline and Pad Layout
3.40
2.37 MIN
3.40
3.20
A
KEEP
OUT
AREA
SYM
PKG
C
L
C
L
8
5
B
(0.45)
8
5
2.15 MIN
0.70 MIN
1.70
3.40
3.20
C
PKG
L
(0.40)
(0.65)
1
4
1
4
0.65
0.42 MIN
SEE
DETAIL A
1.95
LAND PATTERN
RECOMMENDATION
1.95
0.10 C A B
0.37
0.27
0.65
0.50
0.30
1
4
(0.20)
PKG
L
C
2.09
1.89
(1.65)
(0.67)
8
5
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
(0.39)
0.52
(2.27)
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME:
0.10 C
1.00
0.85
0.08 C
C
0.05
0.23
0.18
0.00
SEATING
PLANE
DETAIL A
SCALE: 2X
www.fairchildsemi.com
FDMC7572S Rev.C1
7
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®
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Motion-SPM™
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Rev. I55
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FDMC7572S Rev.C1
8
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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