FDMC86102LZ [ONSEMI]
N 沟道,屏蔽门极,PowerTrench® MOSFET,100 V,22A,24mΩ;型号: | FDMC86102LZ |
厂家: | ONSEMI |
描述: | N 沟道,屏蔽门极,PowerTrench® MOSFET,100 V,22A,24mΩ PC 开关 脉冲 光电二极管 晶体管 |
文件: | 总8页 (文件大小:243K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET - N-Channel,
Shielded Gate,
POWERTRENCH)
Pin 1
G
S
S
S
D
D
D
100 V, 24 mꢀ , 22 A
D
Top
Bottom
WDFN8 MPL
CASE 511DH
FDMC86102LZ
Description
This N−Channel logic Level MOSFETs are produced using
onsemi’s advanced POWERTRENCH process that incorporates
Shielded Gate technology. This process has been optimized for the
on−state resistance and yet maintain superior switching performance.
G−S zener has been added to enhance ESD voltage level.
N−Channel
S
S
1
2
8
7
D
D
Features
S
3
4
6
5
D
D
• Shielded Gate MOSFET Technology
• Max R
• Max R
• HBM ESD Protection Level > 6 kV Typical (Note 4)
• 100% UIL Tested
• RoHS Compliant
= 24 mW at V = 10 V, I = 6.5 A
GS D
DS(on)
G
= 35 mW at V = 4.5 V, I = 5.5 A
DS(on)
GS
D
MARKING DIAGRAM
Applications
• DC−DC Switching
FDMC
86102Z
AKKXY
MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Ratings
100
Unit
V
FDMC86102Z
A
KK
XY
= Specific Device Code
= Assembly Plant Code
= Lot Run Traceability Code
= Numeric Date Code
V
DS
V
GS
20
V
I
D
Drain Current
A
− Continuous
T
= 25°C
22
7
C
− Continuous
T = 25°C
A
ORDERING INFORMATION
(Note 1a)
†
Device
Package
Shipping
− Pulsed
30
84
41
2.3
E
AS
Single Pulse Avalanche Energy (Note 3)
mJ
W
FDMC86102LZ
WDFN8
(Pb-Free,
Halide Free)
3000 /
Tape & Reel
P
D
Power Dissipation
T = 25°C
C
Power Dissipation
(Note 1a)
T = 25°C
A
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
January, 2023 − Rev. 3
FDMC86102LZ/D
FDMC86102LZ
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Ambient (Note 1a)
3
°C/W
R
q
JC
JA
R
53
q
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain−to−Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
100
−
−
−
V
DSS
D
GS
Breakdown Voltage
Temperature Coefficient
= 250 mA, referenced to 25°C
−
71
mV/°C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
V
V
= 80 V, V = 0 V
−
−
−
−
1
mA
mA
DSS
GSS
DS
GS
I
Gate−to−Source Leakage Current
=
20 V, V = 0 V
10
GS
DS
ON CHARACTERISTICS
V
Gate−to−Source Threshold Voltage
V
I
= V , I = 250 mA
1.0
1.6
2.2
V
GS(th)
GS
DS
D
Gate−to−Source Threshold Voltage
Temperature Coefficient
= 250 mA, referenced to 25°C
−
−6
−
mV/°C
DVGS(th)
DTJ
D
R
Static Drain−to−Source
V
GS
V
GS
V
GS
V
DS
= 10 V, I = 6.5 A
−
−
−
−
19
25
31
24
24
35
40
−
mW
DS(on)
D
On Resistance
= 4.5 V, I = 5.5 A
D
= 10 V, I = 6.5 A, T = 125°C
D
J
g
FS
Forward Transconductance
= 5 V, I = 6.5 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 50 V, V = 0 V, f = 1 MHz
−
−
−
−
969
181
9
1290
240
15
pF
pF
pF
W
iss
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
0.4
−
g
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
= 50 V, I = 6.5 A, V = 10 V,
GEN
−
−
−
−
−
−
−
−
7.1
2.3
19
15
10
35
10
22
11
−
ns
d(on)
DD
D
GS
R
= 6 W
t
r
t
Turn−Off Delay Time
Fall Time
d(off)
t
f
2.5
15.3
7.6
2.4
2.5
Q
Q
Total Gate Charge
Total Gate Charge
Gate−to−Source Charge
Gate−to−Drain “Miller” Charge
V
GS
V
GS
V
DD
V
DD
= 0 V to 10 V, V = 50 V, I = 6.5 A
nC
g(tot)
g(tot)
DD
D
= 0 V to 4.5 V, V = 50 V, I = 6.5 A
DD
D
Q
= 50 V, I = 6.5 A
D
gs
Q
= 50 V, I = 6.5 A
−
gd
D
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2
FDMC86102LZ
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source−to−Drain Diode Forward
V
V
= 0 V, I = 6.5 A (Note 2)
−
−
−
−
0.80
0.72
37
1.3
1.2
59
V
V
SD
GS
S
Voltage
= 0 V, I = 2 A (Note 2)
GS
S
t
Reverse Recovery Time
I = 6.5 A, di/dt = 100 A/ms
F
ns
nC
rr
Q
Reverse Recovery Charge
27
43
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTES:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. R
is guaranteed
JC
q
q
JA
by design while R
is determined by the user’s board design.
q
CA
a) 53°C/W when mounted on
b) 125°C/W when mounted on
a minimum pad of 2 oz copper
2
a 1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. Starting T = 25_C; N−ch: L = 1 mH, I = 13 A, V = 90 V, V = 10 V.
J
AS
DD
GS
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
www.onsemi.com
3
FDMC86102LZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
30
25
20
15
8
7
6
V
= 10 V
GS
V
= 2.5 V
GS
V
= 4.5 V
GS
5
Pulse Duration = 80 ms
Duty Cycle = 0.5 % Max
V
= 3.5 V
V
= 3 V
GS
GS
V
GS
= 3 V
4
3
Pulse Duration = 80 ms
Duty Cycle = 0.5 % Max
V
GS
= 3.5 V
10
5
2
V
= 2.5 V
GS
1
0
V
GS
= 10 V
V
= 4.5 V
GS
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
5
10
15
20
25
30
V
DS
, Drain Source Voltage (V)
I
D,
Drain Current (A)
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
100
80
60
40
20
0
I = 6.5 A
D
I
= 6.5 A
= −10 V
D
Pulse Duration = 80 ms
Duty Cycle = 0.5 % Max
V
GS
T = 125°C
J
T = 25°C
J
−75 −50 −25
0
25 50 75 100 125 150
2
4
6
8
10
T , Junction Temperature (5C)
J
V
GS
, Gate to Source Voltage (V)
Figure 3. Normalized On−Resistance vs.
Figure 4. On-Resistance vs.
Junction Temperature
Gate−to−Source Voltage
30
30
10
Pulse Duration = 80 ms
Duty Cycle = 0.5 % Max
V
= 0 V
GS
25
20
15
10
V
DS
= −5 V
1
T = 150°C
J
T = 25°C
J
0.1
T = 150°C
J
T = 25°C
J
0.01
5
0
T = −55°C
J
T = −55°C
J
0.001
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
SD
, Body Diode Forward Voltage (V)
V
GS
, Gate to Source Voltage (V)
Figure 5. Transfer Characteristics
Figure 6. Source−to−Drain Diode
Forward Voltage vs. Source Current
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4
FDMC86102LZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
10
8
5000
1000
I
D
= 6.5 A
V
DD
= 25 V
C
iss
V
DD
= 50 V
C
oss
6
100
V
DD
= 75 V
4
C
rss
10
1
2
f = 1 MHz
V
GS
= 0 V
0
0
4
8
Q ,Gate Charge (nC)
12
16
0.1
1
10
100
V
DS
Drain to Source Voltage (V)
g
Figure 8. Capacitance vs Drain−to−Source
Figure 7. Gate Charge Characteristics
Voltage
30
25
20
15
10
5
50
10
R
= 3.0 °C/W
q
JC
T = 25°C
J
V
GS
= 10 V
T = 100°C
J
Limited by
Package
V
GS
= 4.5 V
T = 125°C
J
1
0
25
50
75
100
125
150
0.1
1
10 20
0.001
0.01
T , Case Temperature (5C)
C
t
, Time in Avalanche (ms)
AV
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
Figure 9. Unclamped Inductive
Switching Capability
−1
−2
10
50
10
V
DS
= 10.V
100 us
1 ms
10
−3
−4
10
10
10
10
10
1
T = 125°C
J
10 ms
−5
−6
−7
This Area is
T = 25°C
J
Limited by R
DS(ON)
100 ms
1 s
0.1
Single Pulse
T = Max Rated
J
10 s
DC
−8
R
= 125°C/W
T = 25°C
A
θ
JA
10
10
0.01
−9
0.005
0
4
8
12
16
20
24
28
32
0.01
0.1
1
10
100
500
V
GS
, Gate to Source Voltage (V)
V
DS
, Drain Source Voltage (V)
Figure 11. Gate Leakage Current vs.
Figure 12. Forward Bias Safe
Operating Area
Gate−to−Source Voltage
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5
FDMC86102LZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
2000
1000
100
10
Single Pulse
= 125°C/W
R
θ
JA
T = 25°C
A
1
0.5
−4
−3
−2
10
−1
100
1000
10
10
10
1
10
t, Pulse Width (s)
Figure 13. Single Pulse Maximum Power Dissipation
2
1
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.1
P
DM
0.05
0.02
0.01
t
1
0.01
t
2
Notes:
Duty Factor: D = t /t
Single Pulse
= 125°C/W
1
2
R
θ
JA
0.001
Peak T = P
x Z
x R
+ T
q
q
JA
J
DM
JA
A
0.0005
−4
−3
10
−2
10
−1
10
100
1000
10
1
10
t, Rectangular Pulse Duration (s)
Figure 14. Junction−to−Ambient Transient Thermal Response
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511DH
ISSUE O
DATE 31 JUL 2016
(3.40)
2.37
0.05 C
B
3.30
A
8
5
2X
0.45(4X)
(0.40)
2.15
3.30
(1.70)
KEEP OUT
AREA
(0.65)
0.70(4X)
0.05 C
PIN#1 IDENT
1
4
TOP VIEW
0.65
0.42(8X)
2X
1.95
RECOMMENDED LAND PATTERN
0.75 0.05
0.10 C
0.15 0.05
0.08 C
0.025 0.025
NOTES:
C
SIDE VIEW
SEATING
PLANE
A. DOES NOT CONFORM TO JEDEC
REGISTRATION MO−229
B. DIMENSIONS ARE IN MILLIMETERS.
3.30 0.05
2.27 0.05
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
(0.50)4X
(0.35)
PIN #1 IDENT
0.50 0.05 (4X)
(0.79)
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
1
4
(1.15)
3.30 0.05
2.00 0.05
R0.15
0.30 0.05 (3X)
8
5
0.35 0.05 (8X)
0.65
0.10
0.05
C A B
C
1.95
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13625G
WDFN8 3.3X3.3, 0.65P
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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