FDMS86500L [ONSEMI]
N 沟道，Power Trench® MOSFET，60V，158A，2.5mΩ;
| 型号： | FDMS86500L |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，Power Trench® MOSFET，60V，158A，2.5mΩ PC 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDMS86500L
MOSFET, N‐Channel,
POWERTRENCH)
60 V, 158 A, 2.5 mW
General Description
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This N−Channel MOSFET has been designed specifically
to improve the overall efficiency and to minimize switch node ringing
of DC/DC converters using either synchronous or synchronous or
conventional switching PWM controllers. It has been optimized for
S
D
D
D
low gate charge, low r
reverse recovery performance.
, fast switching speed and body diode
DS(on)
S
S
G
Features
• Max r
• Max r
= 2.5 mW at V = 10 V, I = 25 A
GS D
= 3.7 mW at V = 4.5 V, I = 20 A
D
DS(on)
DS(on)
GS
D
• Advanced Package and Silicon combination for low r
and high
N-Channel MOSFET
DS(on)
efficiency
• Next generation enhanced body diode technology, engineered for soft
Top
Bottom
S
Pin 1
recovery
S
• MSL1 robust package design
• 100% UIL tested
• RoHS Compliant
S
G
D
D
D
D
Applications
Power 56
(PQFN8)
CASE 483AE
• Primary Switch in Isolated DC−DC
• Synchronous Rectifier
• Load Switch
MARKING DIAGRAM
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
S
S
D
D
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current:
Ratings
60
Unit
V
$Y&Z&3&K
FDMS
86500L
V
DS
V
GS
S
D
D
20
V
G
I
D
A
− Continuous T = 25°C (Note 5)
158
100
25
C
− Continuous T = 100°C (Note 5)
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
C
− Continuous T = 25°C (Note 1a)
A
− Pulsed (Note 4)
799
E
Single Pulse Avalanche Energy (Note 3)
Power Dissipation:
240
mJ
W
AS
FDMS86500L
= Specific Device Code
P
D
T
= 25°C
104
2.5
C
T = 25°C (Note 1a)
A
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
T , T
Operating and Storage Junction Tempera-
ture Range
−55 to
+150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
November, 2018 − Rev. 2
FDMS86500L/D
FDMS86500L
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Package
Quantity
FDMS86500L
FDMS86500L
Power 56 (PQFN8)
(Pb-Free / Halogen Free)
3000/Tape&Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
THERMAL CHARACTERISTICS
Symbol
Parameter
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient (Note 1a)
Value
1.2
Unit
°C/W
R
q
JC
R
50
q
JA
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
60
V
DSS
D
GS
DBV
Breakdown Voltage Temperature
Coefficient
= 250 mA, referenced to 25°C
30
mV/°C
DSS
D
/DT
J
DSS
GSS
I
Zero Gate Voltage Drain Current
V
V
= 48 V, V = 0 V
1
mA
DS
GS
I
Gate to Source Leakage Current, Forward
=
20 V, V = 0 V
100
nA
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = 250 mA
1
1.8
3
V
GS(th)
GS
DS
D
DV
/DT
Gate to Source Threshold Voltage
Temperature Coefficient
= 250 mA, referenced to 25°C
−7
mV/°C
GS(th)
J
D
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
DS
= 10 V, I = 25 A
2.1
2.9
3.1
95
2.5
3.7
3.7
mW
DS(on)
D
= 4.5 V, I = 20 A
D
= 10 V, I = 25 A, T = 125°C
D
J
g
FS
= 5 V, I = 20 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 30 V, V = 0 V, f = 1 MHz
9420
1470
50
12530
1955
80
pF
pF
pF
W
iss
DS
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
f = 1MHz
0.1
1.1
3.0
g
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Rise Time
V
= 30 V, I = 25 A, V = 10 V,
GEN
27
16
43
28
ns
ns
ns
ns
nC
d(on)
DD
D
GS
R
= 6 W
t
r
t
Turn-Off Delay Time
Fall Time
63
100
16
d(off)
t
f
7.8
117
Q
Total Gate Charge
V
= 0 V to 10 V, V = 30 V,
165
g
GS
GS
DD
DD
I
D
= 25 A
V
= 0 V to 4.5 V, V = 30 V,
54
108
nC
DD
I
D
= 25 A
Q
Gate to Source Charge
V
= 30 V, I = 25 A
26.6
11.5
nC
nC
gs
D
Q
Gate to Drain “Miller” Charge
gd
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2
FDMS86500L
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
DRAIN-SOURCE DIODE CHARACTERISTICS
I
Continuous Drain to Source Diode
Forward Current
T
T
= 25°C
= 25°C
80
A
A
V
s
C
I
Pulse Drain to Source Diode
Forward Current
799
s,pulse
C
V
SD
Source to Drain Diode Forward Voltage
V
V
= 0 V, I = 2.1 A (Note 2)
0.68
0.79
54
1.2
1.3
87
GS
S
= 0 V, I = 25 A (Note 2)
GS
S
t
rr
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
I = 25 A, di/dt = 100 A/ms
F
ns
nC
ns
Q
42
67
rr
t
rr
I = 25 A, di/dt = 300 A/ms
F
46
73
Q
84
134
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTES:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. R
is determined
CA
q
q
JA
by the user’s board design.
a. 50 °C/W when mounted on a
1 in pad of 2 oz copper.
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. E of 220 mJ is based on starting T = 25°C, L = 0.3 mH, I = 40 A, V = 54 V, V = 10 V. 100% test at L = 0.1 mH, I = 66 A.
AS
J
AS
DD
GS
AS
4. Pulsed Id please refer to Figure 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal &
electro−mechanical application board design.
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
350
280
210
140
70
5
V
= 10 V
GS
= 5 V
VGS = 3.5 V
V
GS
4
V
= 4.5 V
GS
V
= 4 V
GS
VGS = 4 V
3
2
1
0
VGS = 4.5 V
V
= 3.5 V
GS
VGS = 10 V
VGS = 5 V
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
, DRAIN TO SOURCE VOLTAGE (V)
4
5
0
70
140
I , DRAIN CURRENT (A)
D
210
280
350
V
DS
Figure 1. On Region Characteristics
Figure 2. Normalized On−Resistance
vs. Drain Current and Gate Voltage
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3
FDMS86500L
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
10
8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
I
D = 25 A
ID = 25 A
VGS = 10 V
6
TJ = 125 o
C
4
2
TJ = 25 o
C
0
−75 −50 −25
0
25 50 75 100 125 150
2
4
6
8
10
T , JUNCTION TEMPERATURE (5C)
J
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figure 4. On−Resistance vs. Gate
to Source Voltage
500
350
280
210
140
70
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
VGS = 0 V
100
VDS = 5 V
10
1
TJ = 150 o
C
T
J = 25 oC
0.1
0.01
TJ = 150 o
C
TJ = 25 o
C
TJ = −55oC
TJ = −55oC
0
0.001
1
2
3
4
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
, GATE TO SOURCE VOLTAGE (V)
V
, BODY DIODE FORWARD VOLTAGE (V)
GS
SD
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
50000
10000
10
8
ID = 25 A
VDD = 20 V
Ciss
VDD = 30 V
6
Coss
1000
100
10
VDD = 40 V
4
Crss
2
f = 1 MHz
V
GS = 0 V
0
0
20
40
60
80
100
120
0.1
1
10
60
Q , GATE CHARGE (nC)
g
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
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4
FDMS86500L
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
160
120
80
100
TJ = 25 oC
TJ = 100 oC
VGS = 10 V
10
VGS = 4.5 V
TJ = 125 o
C
40
R
qJC = 1.2 oC/W
1
0
25
50
T
75
100
125
150
0.01
0.1
1
10
100
1000
o
t
, TIME IN AVALANCHE (ms)
, CASE TEMPERATURE (
C)
AV
c
Figure 9. Unclamped Inductive
Switching Capability
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
1000
100
10
20000
10000
SINGLE PULSE
qJC = 1.2 oC/W
R
10 ms
T
C = 25 oC
1000
100
10
100 ms
THIS AREA IS
LIMITED BY r DS(on)
1 ms
SINGLE PULSE
TJ = MAX RATED
1
R
qJC = 1.2 oC/W
10 ms
DC
CURVE BENT TO
MEASURED DATA
T
C = 25 oC
0.1
10−5
10−4
10−3
t, PULSE WIDTH (sec)
10−2
10−1
1
0.1
1
10
100 300
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
P
DM
0.1
0.01
0.05
0.02
0.01
t
1
t
2
NOTES:
(t) = r(t) x R
Z
SINGLE PULSE
qJC
qJC
R
= 1.2 5C/W
qJC
Peak T = P x Z (t) + T
C
J
DM
qJC
Duty Cycle, D = t / t
1
2
0.001
10−5
10−4
10−3
10−2
10−1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Transient Thermal Response Curve
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE C
DATE 21 JAN 2022
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13655G
PQFN8 5X6, 1.27P
PAGE 1 OF 1
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相关型号：
FDMS86500L_F142
Power Field-Effect Transistor, 25A I(D), 60V, 0.0025ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MO-240AA, ROHS COMPLIANT, POWER 56, 8 PIN
FAIRCHILD
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