FDMS86540 [ONSEMI]
N 沟道，Power Trench® MOSFET，60V，129A，3.4mΩ;
| 型号： | FDMS86540 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，Power Trench® MOSFET，60V，129A，3.4mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
May 2015
FDMS86540
N-Channel PowerTrench® MOSFET
60 V, 129 A, 3.4 mΩ
Features
General Description
Max rDS(on) = 3.4 mΩ at VGS = 10 V, ID = 20 A
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers.It has been optimized
for low gate charge, low rDS(on), fast switching speed and body
diode reverse recovery performance.
Max rDS(on) = 4.1 mΩ at VGS = 8 V, ID = 18.5 A
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
Next generation enhanced body diode technology,
engineered for soft recovery
Applications
MSL1 robust package design
100% UIL tested
Primary Switch in isolated DC-DC
Synchronous Rectifier
Load Switch
RoHS Compliant
Bottom
Top
Pin 1
S
D
D
D
D
S
S
S
S
S
G
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
60
±20
V
V
TC = 25 °C
TC = 100 °C
TA = 25 °C
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
129
82
ID
A
-Continuous
20
-Pulsed
642
EAS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
228
mJ
W
TC = 25 °C
TA = 25 °C
96
PD
(Note 1a)
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
1.3
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86540
FDMS86540
Power 56
3000 units
1
©2012 Fairchild Semiconductor Corporation
FDMS86540 Rev. 1.4
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
28
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 48 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
2
3.2
-11
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
mV/°C
V
GS = 10 V, ID = 20 A
2.7
3.1
3.8
73
3.4
4.1
4.8
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 8 V, ID = 18.5 A
mΩ
VGS = 10 V, ID = 20 A, TJ = 125 °C
VDS = 10 V, ID = 20 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
4837
1413
50
6435
1880
90
pF
pF
pF
Ω
VDS = 30 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
1.0
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
28
16
32
7.2
65
53
23
12
45
29
52
15
90
75
ns
ns
VDD = 30 V, ID = 20 A,
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 8 V
nC
nC
nC
nC
Qg
VDD = 30 V,
D = 20 A
I
Qgs
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 2.1 A
(Note 2)
(Note 2)
0.70
0.79
55
1.2
1.3
88
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 20 A
trr
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
ns
nC
ns
IF = 20 A, di/dt = 100 A/μs
IF = 20 A, di/dt = 300 A/μs
Qrr
trr
41
66
44
70
Qrr
76
122
nC
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is determined by the user's board design.
θCA
θJA
b) 125 °C/W when mounted on a
minimum pad of 2 oz copper.
a)
50 °C/W when mounted on a
1 in pad of 2 oz copper
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T = 25 °C, L = 0.3 mH, I = 39 A, V = 54 V, V = 10 V. 100% test at L = 0.1 mH, I = 57 A.
J
AS
DD
GS
AS
4. Pulse Id please refer to SOA curve for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2012 Fairchild Semiconductor Corporation
FDMS86540 Rev. 1.4
2
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted.
350
5
4
3
2
1
0
V
= 10 V
GS
= 9 V
VGS = 6 V
V
GS
280
210
140
70
V
= 8 V
GS
VGS = 7 V
V
= 7 V
= 6 V
GS
VGS = 8 V
V
GS
VGS = 9 V
210
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
5
0
70
140
280
350
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs. Drain Current and Gate Voltage
15
1.7
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 20 A
ID = 20 A
GS = 10 V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
V
12
9
6
TJ = 125 o
C
3
TJ = 25 o
C
0
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
F i gu re 3 . N orma li zed On - Res is ta nc e
vs. Junction Temperature
Figure4. On-Resistance vs. Gate to
Source Voltage
400
350
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
100
280
210
140
70
10
VDS = 5 V
TJ = 150 o
C
1
TJ = 25 oC
0.1
TJ = 150 o
C
TJ = 25 o
C
TJ = -55 o
C
0.01
TJ = -55 o
C
0
0.001
2
3
4
5
6
7
8
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs. Source Current
©2012 Fairchild Semiconductor Corporation
FDMS86540 Rev. 1.4
3
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted.
10
10000
1000
100
Ciss
ID = 20 A
VDD = 30 V
8
6
4
2
0
VDD = 40 V
VDD = 20 V
Coss
Crss
f = 1 MHz
= 0 V
V
GS
10
0.1
0
10
20
30
40
50
60
70
1
10
60
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s . D r a i n
to Source Voltage
140
120
100
80
100
10
1
RθJC = 1.3 oC/W
VGS = 10 V
VGS = 8 V
TJ = 25 o
C
60
TJ = 100 o
C
40
TJ = 125 o
C
20
0
25
50
75
100
125
150
0.01
0.1
1
10
100 300
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs. Case Temperature
1000
100
10
20000
SINGLE PULSE
θJC = 1.3 oC/W
C = 25 o
10000
1000
100
10 μs
R
T
C
100 μs
THIS AREA IS
LIMITED BY rDS(on)
1 ms
1
10 ms
DC
SINGLE PULSE
T
J = MAX RATED
θJC = 1.3 oC/W
C = 25 oC
0.1
0.01
R
CURVE BENT TO
MEASURED DATA
T
10
10-5
10-4
10-3
t, PULSE WIDTH (sec)
10-2
10-1
1
0.1
1
10
100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS86540 Rev. 1.4
4
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
P
DM
0.1
0.1
0.05
0.02
0.01
t
1
t
2
0.01
NOTES:
(t) = r(t) x R
Z
θJC
θJC
SINGLE PULSE
o
R
= 1.3 C/W
θJC
Peak T = P
x Z (t) + T
J
DM
θJC C
Duty Cycle, D = t / t
1
2
0.001
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS86540 Rev. 1.4
5
www.fairchildsemi.com
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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