FDP3632 [ONSEMI]
N 沟道，PowerTrench® MOSFET，100V，80A，9mΩ 推荐替代产品为 FDP090N10;
| 型号： | FDP3632 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，100V，80A，9mΩ 推荐替代产品为 FDP090N10 |
| 文件： | 总17页 (文件大小：864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET – Power, N-Channel,
POWERTRENCHꢀ
100 V, 80 A, 9 mW
FDH3632, FDP3632,
FDB3632
www.onsemi.com
Features
• R
= 7.5 mW (Typ.), V = 10 V, I = 80 A
GS D
DS(ON)
• Q (tot) = 84 nC (Typ.), V = 10 V
g
GS
V
DSS
R
MAX
I MAX
D
DS(ON)
• Low Miller Charge
• Low Q Body Diode
100 V
9 mW
80 A
rr
• UIS Capability (Single Pulse and Repetitive Pulse)
• These Devices are Pb−Free and are RoHS Compliant
D
S
Applications
G
• Synchronous Rectification
• Battery Protection Circuit
• Motor Drives and Uninterruptible Power Supplies
• Micro Solar Inverter
TO−247−3
CASE 340CK
G
D
S
TO−220−3
CASE 340AT
G
D
S
D2PAK−3
CASE 418AJ
MARKING DIAGRAM
$Y&Z&3&K
FDX3632
$Y
= ON Semiconductor Logo
&Z
&3
&K
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
FDX3632
= Specific Device Code
X = H/P/B
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2020 − Rev. 5
FDP3632/D
FDH3632, FDP3632, FDB3632
MOSFET MAXIMUM RATINGS (T = 25°C, Unless otherwise noted)
C
Symbol
Parameter
Value
100
20
Unit
V
V
DSS
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
GS
V
I
D
− Continuous (T < 111°C, V = 10 V)
80
A
C
GS
− Continuous (T
= 25°C, V = 10 V,
12
amb
GS
R
= 43°C/W)
q
JA
I
Drain Current
− Pulsed
Figure 4
337
A
mJ
W
D
E
AS
Single Pulse Avalanche Energy (Note 1)
Power Dissipation
(T = 25°C)
P
310
D
C
− Derate Above 25°C
Operating and Storage Temperature Range
2.07
W/°C
°C
T , T
−55 to +175
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Starting T = 25°C, L = 0.12mH, I = 75 A, V = 80 V.
J
AS
DD
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.48
62
Unit
2
R
q
JC
R
q
JA
R
q
JA
R
q
JA
Thermal Resistance, Junction to Case, Max. TO−220, D −PAK, TO−247
Thermal Resistance, Junction to Ambient, Max. TO−220 (Note 2)
_C/W
_C/W
_C/W
_C/W
2
2
Thermal Resistance, Junction to Ambient, D −PAK, Max. 1 in copper pad area
43
Thermal Resistance, Junction to Ambient, Max. TO−247 (Note 2)
30
2. Pulse Width = 100 s
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
FDB3632
Device
Package
Reel Size
330 mm
Tube
Tape Width
Quantity
2
FDB3632
FDP3632
FDH3632
D −PAK
24 mm
N/A
800 Units
50 Units
30 Units
FDP3632
TO−220
TO−247
FDH3632
Tube
N/A
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2
FDH3632, FDP3632, FDB3632
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
100
V
VDSS
D
GS
I
V
V
V
= 80 V, V = 0 V
1
mA
DSS
DS
DS
GS
GS
= 80 V, V = 0 V, T = 150_C
250
100
GS
C
I
Gate to Source Leakage Current
=
20 V
nA
GSS
ON CHARACTERISTICS
V
GS(TH)
R
DS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
2.0
4.0
V
GS
DS
D
I
D
I
D
I
D
= 80 A, V = 10 V
0.0075
0.009
0.018
0.009
0.015
0.022
W
GS
= 40 V, V = 6 V
GS
= 80 A, V = 10 V, T = 175 °C
GS
C
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V, f = 1 MHz
6000
820
200
84
pF
pF
pF
nC
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Total Gate Charge at 10 V
rss
Q
V
GS
V
DD
= 0 V to 10 V,
110
14
g(tot)
= 50 V, I = 80 A, I = 1 mA
D
g
Q
Threshold Gate Charge
V
GS
V
DD
= 0 V to 2 V,
11
nC
g(th)
= 50 V, I = 80 A, I = 1 mA
D
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 50 V, I = 80 A, I = 1 mA
30
20
20
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
RESISTIVE SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn-On Time
Turn-On Delay Time
Rise Time
V
DD
V
GS
= 50 V, I = 80 A,
102
213
ns
ns
ns
ns
ns
ns
ON
D
= 10 V, R = 3.6 W
GS
t
30
39
96
46
d(ON)
t
r
t
Turn-Off Delay Time
Fall Time
d(OFF)
t
f
t
Turn-Off Time
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
I
I
I
= 80 A
= 40 A
1.25
1
V
V
SD
SD
SD
SD
t
Reverse Recovery Time
= 75 A, dl /dt = 100 A/ms
64
ns
nC
rr
SD
Q
Reverse Recovered Charge
120
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
FDH3632, FDP3632, FDB3632
TYPICAL CHARACTERISTICS
T
C
= 25°C unless otherwise noted
1.2
1.0
0.8
0.6
0.4
0.2
0
125
100
75
CURRENT LIMITED
BY PACKAGE
V
= 10V
GS
50
25
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T
, CASE TEMPERATURE ( C)
C
C
Figure 1. Normalized Power
Dissipation vs. Ambient Temperature
Figure 2. Maximum Continuous
Drain Current vs Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
x R
PEAK T = P
x Z
+ T
JC C
Q
Q
J
DM
JC
0.01
−5
−4
−3
−2
−1
0
1
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
o
T
= 25 C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
C
FOR TEMPERATURES
o
1000
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 − T
C
V
= 10V
I = I
GS
25
150
100
50
−5
−4
−3
−2
−1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
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4
FDH3632, FDP3632, FDB3632
TYPICAL CHARACTERISTICS (Continued)
T
C
= 25°C unless otherwise noted
NOTE: Refer to ON Semiconductor Application Notes
AN−7514 and AN−7515
400
100
200
If R = 0
= (L)(I )/(1.3*RATED BV
10 ms
t
AV
− V )
DD
AS
DSS
If R ꢁ 0
t
= (L/R)ln[(I *R)/(1.3*RATED BV
− V ) +1]
DD
AV
AS
DSS
100
100 ms
o
OPERATION IN THIS
AREA MAY BE
STARTING T = 25
J
C
10
1
LIMITED BY r
DS(ON)
1ms
o
STARTING T = 150 C
J
10ms
DC
SINGLE PULSE
T
T
= MAX RATED
J
o
= 25 C
C
0.1
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.01
0.1
1
10
V
DS
t
, TIME IN AVALANCHE (ms)
AV
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
150
150
120
90
60
30
0
PULSE DURATION = 80 ms
V
= 6V
GS
DUTY CYCLE = 0.5% MAX
V
= 10V
GS
V
= 15V
V
= 5.5V
DD
GS
120
90
60
30
0
o
T
= 175 C
J
V
= 5V
GS
o
T
= 25 C
J
o
o
T
= 25 C
T
= −55 C
C
J
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
0
1
2
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3
4
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
10
9
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
8
V
= 10V
GS
7
V
= 10V, I =80A
D
GS
6
0
2 0
40
I , DRAIN CURRENT (A)
62
80
−80
−40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
D
J
Figure 9. Drain to Source On Resistance
vs Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
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FDH3632, FDP3632, FDB3632
TYPICAL CHARACTERISTICS (Continued)
T
C
= 25°C unless otherwise noted
1.2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
= V , I = 250 mA
DS D
I
= 250 mA
GS
D
1.1
1.0
0.9
−80
−40
0
40
80
120
o
160
200
−80
−40
0
40
80
120
160
200
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage
vs. Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
8
10000
V
= 50V
DD
C
ꢀ C + C
GS GD
ISS
C
^ C + C
OSS
DS
GD
6
1000
C
ꢀ C
GD
RSS
4
WAVEFORMS IN
DESCENDING ORDER:
2
I
I
= 80A
= 40A
D
D
V
= 0V, f = 1MHz
1
GS
0
100
0
20
40
60
80
100
0.1
10
100
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 13. Capacitance vs. Drain
to Source Voltage
Figure 14. Gate Charge Waveforms
for Constant Gate Currents
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FDH3632, FDP3632, FDB3632
TEST CIRCUITS WAVEFORMS
V
DS
L
VARY tp TO OBTAIN
REQUIRED PEAK I
AS
R
G
+
V
DD
DUT
−
V
GS
tp
0 V
I
AS
0.01 W
Figure 15. Unclamped Energy
Test Curcuit
Figure 16. Unclamped Energy
Waveforms
V
DS
L
V
GS
+
V
DD
DUT
−
I
g(REF)
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
R
L
+
V
GS
V
DD
−
DUT
R
GS
V
GS
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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FDH3632, FDP3632, FDB3632
Thermal Resistance vs. Mounting Pad Area
ON Semiconductor provides thermal information to assist
the designer’s preliminary application evaluation. Figure 21
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM,
in an application. Therefore the application’s ambient
defines the R
for the device as a function of the top copper
qJA
(component side) area. This is for a horizontally positioned
FR−4 board with 1 oz copper after 1000 seconds of steady
state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the ON Semiconductor
device Spice thermal model or manually utilizing
the normalized maximum transient thermal impedance
curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
temperature, TA (°C), and thermal resistance R
(°C/W)
qJA
must be reviewed to ensure that T is never exceeded.
JM
Equation 1 mathematically represents the relationship
and serves as the basis for establishing the rating of the part.
(TJM * TA)
(eq. 1)
PDM
+
RQJA
In using surface mount devices such as the TO−263
package, the environment in which it is applied will have
a significant influence on the parts current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is
attached and whether there is copper on one side
or both sides of the board.
19.84
(0.262 ) Area)
RQJA + 26.51 )
(eq. 2)
2. The number of copper layers and the thickness of
the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width,
the duty cycle and the transient thermal response
of the part, the board and the environment they
are in.
2
Area in in .
128
(1.69 ) Area)
RQJA + 26.51 )
(eq. 3)
2
Area in cm .
80
R
= 26.51+ 19.84/(0.262+Area) EQ.2
QJA
R
= 26.51+ 128/(1.69+Area) EQ.3
QJA
60
40
20
0.1
(0.645)
1
10
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm
)
Figure 21. Thermal Resistance vs. Mounting Pad Area
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FDH3632, FDP3632, FDB3632
PSPICE Electrical Model
.SUBCKT FDB3632 2 1 3 ; rev May 2002
CA 12 8 1.7e−9
Cb 15 14 2.5e−9
Cin 6 8 6.0e−9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 102.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.61e−9
Ldrain 2 5 1.0e−9
Lsource 3 7 2.7e−9
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 27
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.8e−3
Rgate 9 20 1.1
RSLC1 5 51 RSLCMOD 1.0e−6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 2.5e−3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*350),3))}
.MODEL DbodyMOD D (IS=5.9E−11 N=1.07 RS=2.3e−3 TRS1=3.0e−3 TRS2=1.0e−6
+ CJO=4e−9 M=0.58 TT=4.8e−8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e−3 TRS2=−8.9e−6)
.MODEL DplcapMOD D (CJO=15e−10 IS=1.0e−30 N=10 M=0.6)
.MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e−30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.1)
.MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.0e−3 TC2=−1.7e−6)
.MODEL RdrainMOD RES (TC1=8.5e−3 TC2=2.8e−5)
.MODEL RSLCMOD RES (TC1=2.0e−3 TC2=2.0e−6)
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FDH3632, FDP3632, FDB3632
.MODEL RsourceMOD RES (TC1=4e−3 TC2=1e−6)
.MODEL RvthresMOD RES (TC1=−4.0e−3 TC2=−1.8e−5)
.MODEL RvtempMOD RES (TC1=−4.4e−3 TC2=2.2e−6)
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−2)
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−2 VOFF=−4)
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.8 VOFF=0.4)
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=0.4 VOFF=−0.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
Figure 22. PSPICE Electrical Model
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FDH3632, FDP3632, FDB3632
SABER Electrical Model
REV May 2002
template FDB3632 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=5.9e−11,nl=1.07,rs=2.3e−3,trs1=3.0e−3,trs2=1.0e−6,cjo=4e−9,m=0.58,tt=4.8e−8,xti=4.2)
dp..model dbreakmod = (rs=0.17,trs1=3.0e−3,trs2=−8.9e−6)
dp..model dplcapmod = (cjo=15e−10,isl=10.0e−30,nl=10,m=0.6)
m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e−30, tox=1)
m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e−30, tox=1)
m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e−30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−2)
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−0.8,voff=0.4)
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=0.4,voff=−0.8)
c.ca n12 n8 = 1.7e−9
c.cb n15 n14 = 2.5e−9
c.cin n6 n8 = 6.0e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 102.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.61e−9
l.ldrain n2 n5 = 1.0e−9
l.lsource n3 n7 = 2.7e−9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.0e−3,tc2=−1.7e−6
res.rdrain n50 n16 = 3.8e−3, tc1=8.5e−3,tc2=2.8e−5
res.rgate n9 n20 = 1.1
res.rslc1 n5 n51 = 1.0e−6, tc1=2.0e−3,tc2=2.0e−6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 2.5e−3, tc1=4e−3,tc2=1e−6
res.rvthres n22 n8 = 1, tc1=−4.0e−3,tc2=−1.8e−5
res.rvtemp n18 n19 = 1, tc1=−4.4e−3,tc2=2.2e−6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
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11
FDH3632, FDP3632, FDB3632
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3))
}}
Figure 23. SABER Electrical Model
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12
FDH3632, FDP3632, FDB3632
SPICE Thermal Model
th
JUNCTION
REV May 2002
FDB3632
CTHERM1 TH 6 7.5e−3
CTHERM2 6 5 8.0e−3
CTHERM3 5 4 9.0e−3
CTHERM4 4 3 2.4e−2
CTHERM5 3 2 3.4e−2
CTHERM6 2 TL 6.5e−2
CTHERM1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
6
5
RTHERM1 TH 6 3.1e−4
RTHERM2 6 5 2.5e−3
RTHERM3 5 4 2.2e−2
RTHERM4 4 3 8.1e−2
RTHERM5 3 2 1.35e−1
RTHERM6 2 TL 1.5e−1
CTHERM2
CTHERM3
CTHERM4
SABER Thermal Model
SABER thermal model FDB3632
template thermal_model th tl
thermal_c th, tl
{
4
3
2
ctherm.ctherm1 th 6 =7.5e−3
ctherm.ctherm2 6 5 =8.0e−3
ctherm.ctherm3 5 4 =9.0e−3
ctherm.ctherm4 4 3 =2.4e−2
ctherm.ctherm5 3 2 =3.4e−2
ctherm.ctherm6 2 tl =6.5e−2
rtherm.rtherm1 th 6 =3.1e−4
rtherm.rtherm2 6 5 =2.5e−3
rtherm.rtherm3 5 4 =2.2e−2
rtherm.rtherm4 4 3 =8.1e−2
rtherm.rtherm5 3 2 =1.35e−1
rtherm.rtherm6 2 tl =1.5e−1
}
CTHERM5
CTHERM6
RTHERM5
RTHERM6
tl
CASE
Figure 24. Thermal Model
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countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
DATE 11 MAR 2021
SCALE 1:1
XXXXXX = Specific Device Code
A
= Assembly Location
WL
Y
= Wafer Lot
= Year
GENERIC MARKING DIAGRAMS*
WW
W
M
G
AKA
= Work Week
= Week Code (SSG)
= Month Code (SSG)
= Pb−Free Package
= Polarity Indicator
XX
AYWW
XXXXXXXXG
AKA
XXXXXXXXG
AYWW
XXXXXX
XXYMW
XXXXXXXXX
AWLYWWG
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
IC
Standard
Rectifier
SSG
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON56370E
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
DESCRIPTION:
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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