FL7930BMX-G_技术文档

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October 2013

FL7930B

Single-Stage Flyback and Boundary-Mode PFC

Controller for Lighting

Description

Features

The FL7930B is an active power factor correction

(PFC) controller for boost PFC applications that

operate in critical conduction mode (CRM). It uses a

voltage-mode PWM that compares an internal ramp

signal with the error amplifier output to generate a

MOSFET turn-off signal. Because the voltage-mode

CRM PFC controller does not need rectified AC line

voltage information, it saves the power loss of an input

voltage sensing network necessary for a current-mode

CRM PFC controller.

.

Additional OVP Detection Pin

V_IN-Absent Detection

Maximum Switching Frequency Limitation

Internal Soft-Start and Startup without Overshoot

Internal Total Harmonic Distortion (THD) Optimizer

Precise Adjustable Output Over-Voltage Protection

Open-Feedback Protection and Disable Function

Zero Current Detector (ZCD)

FL7930B provides over-voltage protection (OVP), open-

feedback protection, over-current protection (OCP),

input-voltage-absent detection, and under-voltage

lockout protection (UVLO). The additional OVP pin can

be used to shut down the boost power stage when

output voltage exceeds OVP level due to the resistors

that are connected at INV pin are damaged. The

FL7930B can be disabled if the INV pin voltage is lower

than 0.45 V and the operating current decreases to a

very low level. Using a new variable on-time control

method, total harmonic distortion (THD) is lower than in

conventional CRM boost PFC ICs.

150 μs Internal Startup Timer

MOSFET Over-Current Protection (OCP)

Under-Voltage Lockout with 3.5 V Hysteresis

Low Startup and Operating Current

Totem-Pole Output with High State Clamp

+500/-800 mA Peak Gate Drive Current

8-Pin, Small-Outline Package (SOP)

Applications

.

Ballast

General LED Lighting

Industrial, Commercial, and Residential Fixtures

Outdoor Lighting: Street, Roadway, Parking,

Construction, Ornamental LED Lighting Fixtures

Ordering Information

Operating

Temperature Range

Packing

Part Number

Top Mark

Package

Method

FL7930BMX_G

-40 to +125°C

FL7930BG

8-Lead Small Outline Package (SOP) Tape & Reel

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

Application Diagram

DC OUTPUT

Vcc

FL7930B

Line Filter

7

4

1

2

8

5

3

Out

V_CC

CS

INV

ZCD

AC INPUT

COMP

OVP

GND

6

Figure 1.

Typical Boost PFC Application

FL7930B

1

2

3

4

8

7

6

5

INV

VCC

C_F1

C_F2

C_HF

GATE

OVP

COMP

CS

GND

ZCD

Figure 2. Typical Application of Single-Stage Flyback Converter

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

2

Internal Block Diagram

V_CC

H:open

V_REF

2.5V_REF

8

V_CC

-

V_Z

Internal

Bias

V_BIAS

reset

+

V_TH(S/S)

8.5

12

5

-

ZCD

V_CC

+

Restart

Tmer

Gate

V_TH(ZCD)

7

OUT

Driver

f_MAX

Limit

V_O(MAX)

THD

Optimized

Sawtooth

Generator

S

Q

Control Range

Compensation

+

R

-

40kW

8pF

Overshoot-less

Control

4

6

+

CS

-

1

-

V_{CS_LIM}

INV

V_REF

Stair

Step

GND

+

Clamp

Circuit

reset

V_INAbsent

3

2

COMP

OVP

disable

Thermal

Shutdown

-

0.35 0.45

V_REF

2.5 2.675

+

INV_open

OVP

V_OVP,LH

disable

+

-

2.5 2.88

Figure 3.

Functional Block Diagram

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

3

Pin Configuration

V_CC

OUT GND ZCD

FL7930BG

8-SOP

INV OVP COMP CS

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin # Name

Description

This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter

should be resistively divided to 2.5 V.

1

2

3

INV

OVP

This pin is used to detect PFC output over voltage when INV pin information is not correct.

This pin is the output of the transconductance error amplifier. Components for the output voltage

compensation should be connected between this pin and GND.

COMP

This pin is the input of the over-current protection comparator. The MOSFET current is sensed

using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is

included to filter switching noise.

4

CS

This pin is the input of the zero-current detection (ZCD) block. If the voltage of this pin goes

higher than 1.5 V, then goes lower than 1.4 V, the MOSFET is turned on.

5

6

ZCD

GND

This pin is used for the ground potential of all the pins. For proper operation, the signal ground

and the power ground should be separated.

This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and

-800 mA, respectively. For proper operation, the stray inductance in the gate driving path must be

minimized.

7

8

OUT

V_CC

This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

Parameter

Min.

Max.

Unit

V_CC

I_OH, I_OL

I_CLAMP

I_DET

Supply Voltage

V_Z

+500

+10

8.0

V

Peak Drive Output Current

-800

-10

mA

Driver Output Clamping Diodes V_O>V_CCor V_O<-0.3 V

Detector Clamping Diodes

-10

Error Amplifier Input, Output, OVP Input, ZCD, RDY, and OVP Pins⁽¹⁾

CS Input Voltage⁽²⁾

-0.3

-10.0

V_IN

V

6.0

T_J

T_A

Operating Junction Temperature

+150

+125

+150

2.5

°C

Operating Temperature Range

-40

-65

T_STG

Storage Temperature Range

Human Body Model, JESD22-A114

Charged Device Model, JESD22-C101

Electrostatic Discharge

Capability

ESD

kV

2.0

Notes:

1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50 mA.

2. In case of DC input, the acceptable input range is -0.3 V~6 V: within 100 ns -10 V~6 V is acceptable, but

electrical specifications are not guaranteed during such a short time.

Thermal Impedance

Symbol

Parameter

Min.

Max.

Unit

Thermal Resistance, Junction-to-Ambient⁽³⁾

150

°C/W

_JA

Note:

3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

5

Electrical Characteristics

V_CC= 14 V and T_A= -40°C~+125°C, unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

V_CCSection

V_START

V_STOP

Start Threshold Voltage

Stop Threshold Voltage

UVLO Hysteresis

V_CCIncreasing

V_CCDecreasing

11

7.5

3.0

20

12

8.5

3.5

22

13

9.5

4.0

24

V

HY_UVLO

V_Z

Zener Voltage

I_CC=20 mA

V_OP

Recommended Operating Range

13

20

Supply Current Section

I_STARTStartup Supply Current

I_OPOperating Supply Current

V_CC=V_START-0.2 V

120

1.5

190

3.0

µA

mA

µA

Output Not Switching

I_DOP

Dynamic Operating Supply Current 50 kHz, C_I=1 nF

Operating Current at Disable V_INV=0 V

2.5

4.0

I_OPDIS

90

160

230

Error Amplifier Section

V_REF1

V_REF1

V_REF2

I_EA,BS

Voltage Feedback Input Threshold1 T_A=25°C

2.465

2.500

0.1

2.535

10.0

V

Line Regulation

V_CC=14 V~20 V

mV

µA

(4)

Temperature Stability of V_REF1

Input Bias Current

20

V_INV=1 V~4 V

-0.5

0.5

I_EAS,SR

I_EAS,SK

V_EAH

V_EAZ

g_m

Output Source Current

Output Sink Current

V_INV=V_REF-0.1 V

V_INV=V_REF+0.1 V

V_INV=1 V, V_CS=0 V

-12

12

µA

Output Upper Clamp Voltage

6.0

0.9

90

6.5

1.0

115

7.0

1.1

140

V

Zero Duty Cycle Output Voltage

Transconductance⁽⁴⁾

V

µmho

Maximum On-Time Section

t_ON,MAX1

t_ON,MAX2

Maximum On-Time Programming 1 T_A=25°C, V_ZCD=1 V

35.5

11.2

41.5

13.0

47.5

14.8

µs

T_A=25°C,

Maximum On-Time Programming 2

I_ZCD=0.469 mA

Current-Sense Section

Current Sense Input Threshold

Voltage Limit

V_CS

I_CS,BS

t_CS,D

0.7

0.8

-0.1

350

0.9

1.0

500

V

Input Bias Current

V_CS=0~1 V

-1.0

µA

ns

dV/dt=1 V/100 ns,

from 0 V to 5 V

Current Sense Delay to Output⁽⁴⁾

Continued on the following page…

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

6

Electrical Characteristics

V_CC= 14 V and T_A= -40°C~+125°C, unless otherwise specified.

Symbol

Parameter

Conditions

Min.

Typ. Max.

Unit

Zero-Current Detect Section

V_ZCD

Input Voltage Threshold⁽⁴⁾

1.35

0.05

5.5

0

1.50

0.10

6.2

1.65

0.15

7.5

1.00

1.0

-4

V

HY_ZCDDetect Hysteresis⁽⁴⁾

V_CLAMPHInput High Clamp Voltage

V_CLAMPLInput Low Clamp Voltage

I_ZCD,BSInput Bias Current

I_ZCD,SRSource Current Capability⁽⁴⁾

I_ZCD,SKSink Current Capability⁽⁴⁾

I_DET=3 mA

V

I_DET=-3 mA

V_ZCD=1 V~5 V

T_A=25°C

0.65

-0.1

V

-1.0

µA

mA

T_A=25°C

10

Maximum Delay From ZCD to Output

Turn-On⁽⁴⁾

dV/dt=-1 V/100 ns, from

5 V to 0 V

t_ZCD,D

100

9.2

200

ns

Output Section

V_OH

V_OL

Output Voltage High

I_O=-100 mA, T_A=25°C

I_O=200 mA, T_A=25°C

C_IN=1 nF

11.0

1.0

50

12.8

2.5

V

Output Voltage Low

Rising Time⁽⁴⁾

Falling Time⁽⁴⁾

t_RISE

t_FALL

100

14.5

1

ns

V

C_IN=1 nF

50

V_O,MAXMaximum Output Voltage

V_CC=20 V, I_O=100 µA

V_CC=5 V, I_O=100 µA

11.5

13.0

V_O,UVLOOutput Voltage with UVLO Activated

V

Restart / Maximum Switching Frequency Limit Section

t_RST

f_MAX

Restart Timer Delay

Maximum Switching Frequency⁽⁴⁾

50

150

300

350

µs

250

kHz

Soft-Start Timer Section

t_SS

Internal Soft-Soft⁽⁴⁾

3

5

7

ms

Protections

V_OVP,INVOVP Threshold Voltage at INV Pin

HY_OVP,INVOVP Hysteresis at INV Pin

V_OVP,OVPOVP Threshold Voltage at OVP Pin

HY_OVP,OVPOVP Hysteresis at OVP Pin

T_A=25°C

2.620 2.675 2.730

0.120 0.175 0.230

2.740 2.845 2.960

0.345

V

V_EN

HY_EN

T_SD

Enable Threshold Voltage

0.40

0.05

125

0.45

0.10

140

60

0.50

0.15

155

V

Enable Hysteresis

V

Thermal Shutdown Temperature⁽⁴⁾

Hysteresis Temperature of TSD⁽⁴⁾

°C

T_HYS

Note:

4. These parameters, although guaranteed by design, are not production tested.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

7

Comparison of FL6961 and FL7930B

Function

FL6961

FL7930B

FL7930B Advantages

.

No External Circuit for additional OVP

OVP Pin

None

Integrated

Reduction of Power Loss and BOM Cost Caused by

Additional OVP Circuit

.

Abnormal CCM Operation Prohibited

Frequency Limit

None

Integrated

Abnormal Inductor Current Accumulation Can Be

Prohibited

.

Increase System Reliability by Testing for Input Supply

Voltage

V_IN-Absent Detection

Guarantee Stable Operation at Short Electric Power

Failure

.

Reduce Voltage and Current Stress at Startup

Soft-Start and

Startup without

Overshoot

Eliminate Audible Noise Due to Unwanted OVP

Triggering

.

Can Avoid Burst Operation at Light Load and High Input

Voltage

Control Range

Compensation

Integrated

Internal

Reduce Probability of Audible Noise Due to Burst

Operation

.

No External Resistor is Needed

THD Optimizer

TSD

External

None

Stable and Reliable TSD Operation

Converter Temperature Range Limited Range

140°C with

60°C Hysteresis

Control Range

Compensation

None

Integrated

Comparison of FL7930B and FL7930C

Function

RDY Pin

OVP Pin

FL7930B

None

FL7930C

Integrated

None

FL7930B Remark

.

User Choice for the Use of Number #2 Pin

Integrated

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

8

Typical Performance Characteristics

Figure 5. Voltage Feedback Input Threshold 1

(V_REF1) vs. T_A

Figure 6.

Start Threshold Voltage (V_START) vs. T_A

Figure 7.

Stop Threshold Voltage (V_STOP) vs. T_A

Figure 8.

Startup Supply Current (I_START) vs. T_A

Figure 9.

Operating Supply Current (I_OP) vs. T_A

Figure 10. Output Upper Clamp Voltage (V_EAH) vs. T_A

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

9

Typical Performance Characteristics

Figure 11. Zero Duty Cycle Output Voltage (V_EAZ

vs. T_A

)

Figure 12. Maximum On-Time Program 1 (t_ON,MAX1

vs. T_A

)

Figure 13.Maximum On-Time Program 2 (t_ON,MAX2

vs. T_A

)

Figure 14. Current-Sense Input Threshold Voltage

Limit (V_CS) vs. T_A

Figure 15. Input High Clamp Voltage (V_CLAMPH

)

Figure 16. Input Low Clamp Voltage (V_CLAMPL) vs. T_A

vs. T_A

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

10

Typical Performance Characteristics

Figure 17. Output Voltage High (V_OH) vs. T_A

Figure 18. Output Voltage Low (V_OL) vs. T_A

Figure 19. Restart Timer Delay (t_RST) vs. T_A

Figure 20. OVP Threshold at OVP Pin (V_OVP,OVP

)

vs. T_A

Figure 21. Output Saturation Voltage (V_RDY,SAT

vs. T_A

)

Figure 22. OVP Threshold Voltage (V_OVP) vs. T_A

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

11

Applications Information

PFC

V_OUT

1. Startup: Normally, supply voltage (V_CC) of a PFC

block is fed from the additional power supply, which can

be called standby power. Without this standby power,

auxiliary winding for zero current detection can be used

as a supply source. Once the supply voltage of the PFC

block exceeds 12 V, internal operation is enabled until

the voltage drops to 8.5 V. If V_CCexceeds V_Z, 20 mA

-

2.885V

2^ndOVP

+

high

disable

2.885

OVP

-

2

2.675V/2.5V

2.5 2.675

OVP

+

-

INV Open

0.35 0.45

current is sinking from V_CC

.

+

0.45V/0.35V

2.5V

PFC Inductor

PFC

INV

V_IN

V_OUT

-

1

Aux. Winding

3

FL7930B Rev. 00

COMP

External V_CCcircuit

when no standby power exists.

Figure 24. Circuit Around INV Pin

PFC

V_OUT

390V_DC

413V

390V

V_CC

H:open

V_CC

’

2.5V_REF

8

V_REF

V_BIAS

-

V_Z

internal

bias

70V

reset

55V

+

V_TH(S/S)

20mA

V_INV

2.50V

2.65V

2.50V

8.5

12

2.24V

1.64V

0.45V

0.35V

Figure 23. Startup Circuit

V_CC

15V

2. INV Block: Scaled-down voltage from the output is

the input for the INV pin. Many functions are embedded

based on the INV pin: transconductance amplifier,

output OVP comparator, and disable comparator.

2.0V

COMP

I_OUT

Current Sourcing

Disable

OVP

I sinking

For the output voltage control, a transconductance

amplifier is used instead of the conventional voltage

amplifier. The transconductance amplifier (voltage-

controlled current source) aids the implementation of

the OVP and disable functions. The output current of

the amplifier changes according to the voltage

difference of the inverting and non-inverting input of

the amplifier. To cancel down the line input voltage

effect on power factor correction, the effective control

response of the PFC block should be slower than the

line frequency and this conflicts with the transient

response of the controller. Two-pole one-zero type

compensation can meet both requirements.

V_CC<2V, internal logic is not alive.

- Internal signals are unknown.

t

Figure 25. Timing Chart for INV Block

3. OVP Pin: Over-Voltage Protection (OVP) is

embedded by the information at the INV pin. That

information comes from the output through the voltage

dividing resistors. To scale down from a high voltage to

a low one, high resistance is normally used with low

resistance. If the resistor of high resistance gets

damaged and resistance is changed to high, though INV

pin information is normal, output voltage exceeds its

rated output. If this occurs, the output electrolytic

The OVP comparator shuts down the output drive block

when the voltage of the INV pin is higher than 2.675 V

and there is 0.175 V hysteresis. The disable comparator

disables operation when the voltage of the inverting input

is lower than 0.35 V and there is 100 mV hysteresis. An

external small-signal MOSFET can be used to disable the

IC, as shown in Figure 24. The IC operating current

decreases to reduce power consumption if the IC is

disabled. Figure 25 is the timing chart of the internal

circuit near the INV pin when rated PFC output voltage is

390 V_DCand V_CCsupply voltage is 15 V.

capacitor may be damaged. To prevent such

a

catastrophe additional OVP pin is assigned to double-

check output voltage. Additional OVP may be called

“second” OVP, while INV pin OVP is called “first” OVP.

Since the two OVP conditions are quite different, the

protection recovering mode is different.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

12

Once the first OVP triggers, switching stops immediately

and recovers switching when the output voltage is

decreased with a hysteresis. When the second OVP

triggers, switching can be recovered only when the V_CC

supply voltage falls below V_STOPand builds up higher

than V_STARTagain and V_OVPshould be lower than

hysteresis. If the second OVP is not used, the OVP pin

must be connected to the INV pin or to the ground.

where, V_AUXis the auxiliary winding voltage; T_INDand

T_AUXare boost inductor turns and auxiliary winding turns,

respectively; V_ACis input voltage for PFC converter; and

V_{OUT_PFC}is output voltage from the PFC converter.

PFC Inductor

PFC

V_IN

V_OUT

Aux. Winding

V_CC

R_ZCD

V_START

Negative Clamp

V_STOP

Circuit

ZCD

5

-

Error on INV

Resistors

Happens

V_INV

INV OVP

Level

+

C_ZCD

Restart

Timer

hysteresis

V_TH(ZCD)

Positive Clamp

Circuit

Optional

Gate

Driver

f_MAX

Limit

S

R

Q

THD

Optimized

Sawtooth

Generator

Though Output-

Voltage Reduced,

no Switching.

V_OVP

OVP Level

Figure 27. Circuit Near ZCD

Because auxiliary winding voltage can swing from

negative to positive voltage, the internal block in ZCD

pin has both positive and negative voltage clamping

circuits. When the auxiliary voltage is negative, an

internal circuit clamps the negative voltage at the ZCD

pin around 0.65 V by sourcing current to the serial

resistor between the ZCD pin and the auxiliary winding.

When the auxiliary voltage is higher than 6.5 V, current

is sinked through a resistor from the auxiliary winding to

the ZCD pin.

Switching stop

If error

I_MOSFET

Switching stop

only during

OVP

until V_CCdrops

below V_STOPand

recovers to

still exist,

OVP

triggers

again

V_START

t

Figure 26. Comparison of First and Second

OVP Recovery Modes

I_SW

4. Control Range Compensation: On time is controlled

by the output voltage compensator with FL7930B. Due

to this when input voltage is high and load is light,

control range becomes narrow compared to when input

voltage is low. That control range decrease is inversely

I_DIODE

V_ACIN

I_MOSFET

V_AUX& V_ZCD

proportional to the double square of the input voltage

1

( control range ∝ _input

). Thus at high line,

V_AUX

2

voltage

V_ZCD

unwanted burst operation easily happens at light load

and audible noise may be generated from the boost

inductor or inductor at input filter. Different from the

other converters, burst operation in PFC block is not

needed because the PFC block itself is normally

disabled during standby mode. To reduce unwanted

burst operation at light load, an internal control range

compensation function is implemented and shows no

burst operation until 5% load at high line.

6.2V

0.65V

t

Figure 28. Auxiliary Voltage Depends

on MOSFET Switching

The auxiliary winding voltage is used to check the boost

inductor current zero instance. When boost inductor

current becomes zero, there is a resonance between

boost inductor and all capacitors at the MOSFET drain

pin, including C_OSSof the MOSFET; an external

capacitor at the D-S pin to reduce the voltage rising and

falling slope of the MOSFET; a parasitic capacitor at

inductor; and so on to improve performance. Resonated

voltage is reflected to the auxiliary winding and can be

used for detecting zero current of boost inductor and

valley position of MOSFET voltage stress. For valley

detection, a minor delay by the resistor and capacitor is

needed. A capacitor increases the noise immunity at the

ZCD pin. If ZCD voltage is higher than 1.5 V, an internal

ZCD comparator output becomes HIGH and LOW when

the ZCD goes below 1.4 V. At the falling edge of

comparator output, internal logic turns on the MOSFET.

5. Zero-Current Detection: Zero-current detection

(ZCD) generates the turn-on signal of the MOSFET

when the boost inductor current reaches zero using an

auxiliary winding coupled with the inductor. When the

power switch turns on, negative voltage is induced at the

auxiliary winding due to the opposite winding direction

(see Equation 1). Positive voltage is induced (see

Equation 2) when the power switch turns off:

T

AUX

V

 

 V

AC

AUX

(1)

(2)

T

IND

T

AUX

V





V

 V

AC



AUX

PFCOUT

T

IND

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

13

V_DS

Ignores ZCD

Noise

ZCD _{after COMPARATOR}

V_OUT^PFC- V_IN

V_IN

MOSFET Gate

Max f_SWLimit

Error Happens!

I_INDUCTOR

t

I_DIODE

I_MOSFET

Inhibit Region

Figure 31. Maximum Switching Frequency

Limit Operation

V_ZCD

6. Control: The scaled output is compared with the

internal reference voltage and sinking or sourcing

current is generated from the COMP pin by the

transconductance amplifier. The error amplifier output is

compared with the internal sawtooth waveform to give

proper turn-on time based on the controller.

1.5V

1.4V

MOSFET gate

ON

150ns Delay

PFC

V_OUT

ON

t

Figure 29. Auxiliary Voltage Threshold

6.2V

THD optimized

Sawtooth

Generator

1V

When no ZCD signal is available, the PFC controller

cannot turn on the MOSFET, so the controller checks

every switching off time and forces MOSFET turn on

when the off time is longer than 150 μs. This restart

timer triggers MOSFET turn-on at startup and may be

used at the input voltage zero cross period.

+

-

MOSFET Off

Sawtooth

INV

1

3

-

V_REF

Stair

Step

+

Clamp

Circuit

COMP

V_OUT

V_IN

R1

C1

C2

V_CC

Figure 32. Control Circuit

Unlike a conventional voltage-mode PWM controller,

FL7930B turns on the MOSFET at the falling edge of

ZCD signal. The “ON” instant is determined by the

external signal and the turn-on time lasts until the error

amplifier output (V_COMP) and sawtooth waveform meet.

When load is heavy, output voltage decreases, scaled

output decreases, COMP voltage increases to

compensate low output, turn-on time lengthens to give

more inductor turn-on time, and increased inductor

current raises the output voltage. This is how a PFC

negative feedback controller regulates output.

t_RESTART

150s

MOSFET Gate

ZCD _{after COMPARATOR}

t

Figure 30. Restart Timer at Startup

Because the MOSFET turn-on depends on the ZCD

input, switching frequency may increase to higher than

several megahertz due to the mis-triggering or noise on

the nearby ZCD pin. If the switching frequency is higher

than needed for critical conduction mode (CRM),

operation mode shifts to continuous conduction mode

(CCM). In CCM, unlike CRM where the boost inductor

current is reset to zero at the next switch on; inductor

current builds up at every switching cycle and can be

raised to very high current that exceeds the current

rating of the power switch or diode. This can seriously

damage the power switch. To avoid this, maximum

switching frequency limitation is embedded. If ZCD

signal is applied again within 3.3 μs after the previous

rising edge of gate signal, this signal is ignored

internally and FL7930B waits for another ZCD signal.

This slightly degrades the power factor performance at

light load and high input voltage.

The maximum of V_COMPis limited to 6.5 V, which

dictates the maximum turn-on time. Switching stops

when V_COMPis lower than 1.0 V.

ZCD _{after COMPARATOR}

V_COMP& Sawtooth

0.155 V / s

MOSFET Gate

t

Figure 33. Turn-On Time Determination

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

14

V_CC

The roles of PFC controller are regulating output voltage

and input current shaping to increase power factor. Duty

control based on the output voltage should be fast

enough to compensate output voltage dip or overshoot.

For the power factor, however, the control loop must not

react to the fluctuating AC input voltage. These two

requirements conflict; therefore, when designing a

feedback loop, the feedback loop should be least ten

times slower than AC line frequency. That slow

response is made by C1 at the compensator. R1 makes

gain boost around operation region and C2 attenuates

gain at higher frequency. Boost gain by R1 helps raise

the response time and improves phase margin.

V_START=12V

SS

V_REF^END=2.5V

V_REF

5ms

V_INV=0.4V

g_M

Gain

COMP

(V_REF^SS-V_INV

)

g_M=I_SOURCE

I_SOURCE

Integrator

C₁

Proportional

Gain

R₁

COMP

V_COMP

I_SOURCE

R_COMP=V_COMP

Freq.

C₂

High-Frequency

Noise Filter

t

Figure 36. Soft-Start Sequence

Figure 34. Compensators Gain Curve

8. Startup without Overshoot: Feedback control speed

of PFC is quite slow. Due to the slow response, there is

a gap between output voltage and feedback control.

That is why over-voltage protection (OVP) is critical at

the PFC controller and voltage dip caused by fast load

changes from light to heavy is diminished by a bulk

capacitor. OVP can be triggered during startup phase.

Operation on and off by OVP at startup may cause

audible noise and can increase voltage stress at startup,

which is normally higher than in normal operation. This

operation is improved when soft start time is very long.

However, too much startup time enlarges the output

voltage building time at light load. FL7930B has

overshoot protection at startup. During startup, the

feedback loop is controlled by an internal proportional

gain controller and when the output voltage reaches the

rated value, it switches to an external compensator after

a transition time of 30 ms. This internal proportional gain

controller eliminates overshoot at startup and an

external conventional compensator takes over

successfully afterward.

For the transconductance error amplifier side, gain

changes based on differential input. When the error is

large, gain is large to suppress the output dip or peak

quickly. When the error is small, low gain is used to

improve power factor performance.

I_COMP

Powering

250mho

115mho

Braking

V_OUT

Conventional Controller

Startup

Figure 35. Gain Characteristic

Overshoot

7. Soft-Start: When V_CCreaches V_START, the internal

reference voltage is increased like a stair step for 5 ms.

As a result, V_COMPis also raised gradually and MOSFET

turn-on time increases smoothly. This reduces voltage

and current stress on the power switch during startup.

Overshoot-less Startup Control

Control Transition

V_COMP

Depend on Load

Internal Controller

t

Figure 37. Startup without Overshoot

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

15

9. THD Optimization: Total harmonic distortion (THD)

is the factor that dictates how closely input current

shape matches sinusoidal form. The turn-on time of the

PFC controller is almost constant over one AC line

period due to the extremely low feedback control

response. The turn-off time is determined by the current

decrease slope of the boost inductor made by the input

voltage and output voltage. Once inductor current

becomes zero, resonance between C_OSSand the boost

inductor makes oscillating waveforms at the drain pin

and auxiliary winding. By checking the auxiliary winding

voltage through the ZCD pin, the controller can check

the zero current of boost inductor. At the same time, a

minor delay is inserted to determine the valley position

of drain voltage. The input and output voltage difference

is at its maximum at the zero cross point of AC input

voltage. The current decrease slope is steep near the

zero cross region and more negative inductor current

flows during a drain voltage valley detection time. Such

a negative inductor current cancels down the positive

current flows and input current becomes zero, called

“zero-cross distortion” in PFC.

To improve this, lengthened turn-on time near the zero

cross region is a well-known technique, though the

method may vary and may be proprietary. FL7930B

optimizes this by sourcing current through the ZCD pin.

Auxiliary winding voltage becomes negative when the

MOSFET turns on and is proportional to input voltage.

The negative clamping circuit of ZCD outputs the

current to maintain the ZCD voltage at a fixed value.

The sourcing current from the ZCD is directly

proportional to the input voltage. Some portion of this

current is applied to the internal sawtooth generator

together with a fixed-current source. Theoretically the

fixed-current source and the capacitor at sawtooth

generator determine the maximum turn-on time when no

current is sourcing at ZCD clamp circuit and available

turn-on time gets shorter proportional to the ZCD

sourcing current.

V_AUX

R_ZCD

V_CC

I_IN

THD Optimizer

N

1

I_INDUCTOR

ZCD

5

I_DIODE

I_MOSFET

V_ZCD

I_NEGATIVE

Zero Current

Detect

V_REF

1.5V

I_MOT

1.4V

150ns

MOSFET Gate

C_MOT

reset

ON

Sawtooth Generator

t

Figure 40. Circuit of THD Optimizer

Figure 38.

Input and Output Current

Near Input Voltage Peak

t_ONis typically constant over 1 AC line frequency

but t_ONis changed by ZCD voltage.

V_ZCD

t_ON

I_IN

I_INDUCTOR

V_ZCD

t

I_NEGATIVE

t_ONnot shortter

t_ONget shortter

V_ZCDat FET on

1.5V

1.4V

Figure 41. Effect of THD Optimizer

150ns

MOSFET Gate

ON

By THD optimizer, turn-on time over one AC line period

is proportionally changed, depending on input voltage.

Near zero cross, lengthened turn-on time improves

THD performance.

ON

t

Figure 39. Input and Output Current Near

Input Voltage Peak Zero Cross

FL7930B • Rev. 1.0.4

www.fairchildsemi.com

16

V_OUT

V_IN

10. V_IN-Absent Detection: To reduce power loss

caused by input voltage sensing resistors and to

optimize THD, the FL7930B omits AC input voltage

detection. Therefore, no information about AC input is

available from the internal controller. In many cases, the

V_CCof PFC controller is supplied by an independent

power source like standby power. In this scheme, some

mismatch may exist. For example, when the electric

power is suddenly interrupted during two or three AC

line periods; V_CCis still live during that time, but output

voltage drops because there is no input power source.

Consequently, the control loop tries to compensate for

the output voltage drop and V_COMPreaches its

maximum. This lasts until AC input voltage is live again.

When AC input voltage is live again, high V_COMPallows

high switching current and more stress is put on the

MOSFET and diode. To protect against this, FL7930B

checks if the input AC voltage exists. If input does not

exist, soft-start is reset and waits until AC input is live

again. Soft-start manages the turn-on time for smooth

operation when it detects AC input is applied again and

applies less voltage and current stress on startup.

Though V_INis eliminated,

operation of controller is

normal due to the large

bypass capacitor.

V_AUX

D_MAX

f_MIN

D_MIN

MOSFET Gate

NewV_COMP

f_MIN

Input Voltage Absent Detected

I_DS

V_OUT

V_IN

Smooth Soft-

Start

t

Though V_INis eliminated,

operation of controller is

normal due to the large

bypass capacitor.

Figure 43. With V_IN-Absent Circuit

11. Current Sense: The MOSFET current is sensed

using an external sensing resistor for over-current

protection. If the CS pin voltage is higher than 0.8 V, the

V_AUX

over-current protection comparator generates

a

protection signal. An internal RC filter of 40 kΩ and 8 pF

is included to filter switching noise.

12. Gate Driver Output: FL7930B contains a single

totem-pole output stage designed for a direct drive of

the power MOSFET. The drive output is capable of up

to +500 / -800 mA peak current with a typical rise and

fall time of 50 ns with 1 nF load. The output voltage is

clamped to 13 V to protect the MOSFET gate even if the

V_CCvoltage is higher than 13 V.

D_MAX

MOSFET Gate

V_COMP

f_MIN

I_DS

High Drain

Current!

t

Figure 42. Without V_IN-Absent Circuit

FL7930B • Rev. 1.0.4

www.fairchildsemi.com

17

PCB Layout Guide

PFC block normally handles high switching current and

the voltage low-energy signal path can be affected by

the high-energy path. Cautious PCB layout is mandatory

for stable operation.

5

A stabilizing capacitor for V_CCis recommended as

close as possible to the V_CCand ground pins. If it is

difficult, place the SMD capacitor as close to the

corresponding pins as possible.

1

The gate drive path should be as short as possible.

The closed-loop that starts from the gate driver,

MOSFET gate, and MOSFET source to ground of

PFC controller should be as close as possible. This

is also crossing point between power ground and

signal ground. Power ground path from the bridge

diode to the output bulk capacitor should be short

and wide. The sharing position between power

ground and signal ground should be only at one

position to avoid ground loop noise. Signal path of

the PFC controller should be short and wide for

external components to contact.

2

The PFC output voltage sensing resistor is normally

high to reduce current consumption. This path can

be affected by external noise. To reduce noise

potential at the INV pin, a shorter path for output

sensing is recommended. If a shorter path is not

possible, place some dividing resistors between

PFC output and the INV pin — closer to the INV pin

is better. Relative high voltage close to the INV pin

can be helpful.

3

4

The ZCD path is recommended close to auxiliary

winding from boost inductor and to the ZCD pin. If

that is difficult, place a small capacitor (below

50 pF) to reduce noise.

Figure 44. Recommended PCB Layout

The switching current sense path should not share

with another path to avoid interference. Some

additional components may be needed to reduce

the noise level applied to the CS pin.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

18

Typical Application Circuit

Input Voltage

Range

Rated Output

Power

Output Voltage

(Maximum Current)

Application

Device

LED Lighting

FL7930B

90-265 V_AC

195 W

390 V (0.5 A)

Features

.

Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.

Power factor at rated load is higher than 0.98 at universal input.

Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.

Key Design Notes

.

When auxiliary V_CCsupply is not available, V_CCpower can be supplied through Zero Current Detect (ZCD)

winding. The power consumption of R103 is quite high, so its power rating needs checking.

.

Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should

be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need

to strike a balance between power consumption and noise immunity.

.

Quick charge diode (D106) can be eliminated if output diode inrush current capability is sufficient. Through D106,

system operation is normal due to the controller’s highly reliable protection features.

Schematic

Optional

D106

600V 3A

D105

600V 8A

194H, 39:5

DC OUTPUT

LP101,EER3124N

BD101,

600V,15A

V_AUX

R103,

10k,1W

C104,

12nF

R109

47

Q101

FCPF

20N60

D102,

UF4004

R108

4.7

D103,1N4148

8

7

V_CC

Out

C102,

680nF

5

ZCD

4

CS

3

Comp

1

INV

2

OVP

GND

6

C114, C115,

2.2nF 2.2nF

C101,

220nF

R101,1M-J

ZNR101,

10D471

Circuit for V_CC. If external V_CCis used, this circuit is not needed.

Figure 45. Demonstration Circuit

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

19

Transformer

EER3019N

9,10

1,2

Naux

9,10

1,2

6,7

N_P

N_aux

N_p

6,7

3,4

Figure 46. Transformer Schematic Diagram

Winding Specifications

Position

Bottom

Top

No

Pin (S → F)

Wire

Turns

Winding Method

N_p

3, 4 → 1, 2

0.1φ×50

39

Solenoid Winding

Insulation: Polyester Tape t = 0.05mm, 3 Layers

N_AUX9,10 → 6,7 0.3φ

Insulation: Polyester Tape t = 0.05 mm, 4 Layers

5

Solenoid Winding

Electrical Characteristics

Specification

Remark

100 kHz, 1 V

Inductance

3, 4 → 1, 2

194 H ± 5%

Core & Bobbin

Core: EER3019, Samhwa (PL-7) (Ae=137.0mm²)

Bobbin: EER3019

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

20

Bill of Materials

Part #

Value

Note

Part #

Value

Note

Resistor

Switch

R101

R102

R103

R104

1W

1/2W

1W

Q101 FCPF20N60

20 A, 600 V, SuperFET^®

1 MW

330 kW

10 kW

Diode

D101

D102

1N4746

UF4004

1 W, 18 V, Zener Diode

1 A, 400 V Glass Passivated

High-Efficiency Rectifier

1/4W

30 kW

R107

R108

R109

1/4W

D103

D104

1N4148

1 A, 100 V Small-Signal Diode

10 kW

4.7 kW

8 A, 600 V, General-Purpose

Rectifier

D105

D106

47 kW

R110

1/4W

3 A, 600 V, General-Purpose

Rectifier

10 kW

0.80 kW

3.9 kW

R111

5W

R112, 113,

114,116,117,118

1/4W

IC101

FL7930B

CRM PFC Controller

R115,119

1/4W

75 kW

Capacitor

Fuse

NTC

C101

C102

220 nF / 275 V_AC

680 nF / 275 V_AC

0.68 µF / 630 V

12 nF / 50 V

Box Capacitor

FS101

TH101

BD101

LF101

T1

5 A / 250 V

5D-15

C103

C104

Box Capacitor

Ceramic Capacitor

SMD (1206)

Bridge Diode

15 A, 600 V

C105

C107

100 nF / 50 V

33 µF / 50 V

Electrolytic Capacitor

Line Filter

C108

C109

220 nF / 50 V

47 nF / 50 V

Ceramic Capacitor

23 mH

EER3019

10D471

Transformer

C110,116

C112

1 nF / 50 V

Ceramic Capacitor

Ae=137.0 mm²

47 nF / 50 V

ZNR

C111

C114

C115

220 µF / 450 V

2.2 nF / 450 V

Electrolytic Capacitor ZNR101

Box Capacitor

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

21

Physical Dimensions

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

0.40

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08Arev14

F) FAIRCHILD SEMICONDUCTOR.

SEATING PLANE

(1.04)

DETAIL A

SCALE: 2:1

Figure 47. 8-Lead, Small Outline Package (SOP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/M0/M08A.pdf.

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

22

www.fairchildsemi.com

FL7930B • Rev. 1.0.4

23

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1


型号：	FL7930BMX-G
厂家：	ONSEMI
描述：	单级反激和边界模式 PFC 控制器，用于照明控制器功率因数校正光电二极管
文件：	总25页 (文件大小：1785K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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