FSL3276ALRN [ONSEMI]
绿色模式安森美半导体降压开关;
| 型号： | FSL3276ALRN |
| 厂家： | 
ONSEMI |
| 描述： | 绿色模式安森美半导体降压开关 开关 半导体 |
| 文件： | 总15页 (文件大小：975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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March 2016
FSL3276ALR
Non-Isolated High-Voltage Buck Switch for Low Power
Application in Building Automation / IoT
Description
Features
The FSL3276ALR is configured as a non-isolated high-
voltage buck switch and is ideal for low-power
applications. Its peak current is adjustable down to
70 mA which enables optimum inductor size selection.
The modulation control is designed to reduce standby
power to 25 mW at 230 VAC input. Though the Pulse
Width Modulator (PWM) and SenseFET are ideally
integrated for a high-performance offline buck, it can
also be configured as a buck-boost or non-isolated
flyback with minimal external components. The device
integrates a high-voltage power regulator that enables
operation without an auxiliary bias winding. An internal
.
.
.
Built-in Avalanche Rugged SenseFET: 650 V
Fixed Operating Frequency: 50 kHz
No-Load Power Consumption: < 25 mW at 230 VAC
with External Bias; <120 mW at 230 VAC without
External Bias
.
.
.
.
.
.
.
.
No Need for Auxiliary Bias Winding
Frequency Modulation for Attenuating EMI
Pulse-by-Pulse Current Limiting
Ultra-Low Operating Current: 250 µA
Built-in Soft-Start and Startup Circuit
Adjustable Peak Current Limit
transconductance
amplifier
reduces
external
components for the feedback compensation circuit. The
integrated PWM controller includes: 10 V regulator for
no external bias circuit, Under-Voltage Lockout (UVLO),
Leading-Edge Blanking (LEB), an optimized gate turn-
on / turn-off driver, EMI attenuator, Thermal Shutdown
(TSD), temperature-compensated precision current
sources for loop compensation, and fault-protection
circuitry. Protections include: Overload Protection
(OLP), Over-Voltage Protection (OVP), Open Feedback
Loop Protection (OFLP), and Abnormal Over-Current
Protection (AOCP). FSL3276ALR offers good soft-start
performance during startup. The internal high-voltage
startup switch and the Burst-Mode operation with very
low operating current reduce the power loss in Standby
Mode. As the result, it is possible to reach power loss of
120 mW without external bias and 25 mW with external
Built-in Transconductance (Error) Amplifier
Various Protections: Overload Protection (OLP),
Over-Voltage Protection (OVP), Open Feedback
Loop Protection (OFLP), AOCP (Abnormal Over-
Current Protection), Thermal Shutdown (TSD)
.
Fixed 650 ms Restart Time for Safe Auto-Restart
Mode of All Protections
Applications
.
.
Building Automation/ IoT
Auxiliary Power Supply for Appliances and
Industrial Applications
bias when input voltage is 230 VAC
.
Ordering Information
Typical Output Power(1)
85 VAC ~ 265 VAC
Operating
Part
Packing
Method
Junction
Temperature
PKG
& Open Frame(2)
Current
Limit
Number
RDS(ON),MAX
Buck
Flyback
Application(3) Application
FSL3276ALRN -40°C ~125°C
7-DIP
Rail
0.30 A
30 Ω
1.2 W
2.4 W
Notes:
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50°C ambient.
3. Based on 15 V output voltage condition. Output voltage can limit the maximum output power.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
Application Diagrams
+
+
DC
OUT
_
HV-DC
INPUT
VCOMP
Drain
VFB
ILIMIT
VCC
Drain GND
HV-DC
INPUT
DC
OUT
_
Figure 1. Buck Converter Application
Figure 2. Non-Isolation Flyback Converter
Application
Block Diagram
Drain
6,7
VCC
2
10V HVREG
VCC Good
Internal
Bias
VBIAS
VSTART
/ VSTOP
Transconductance
Amplifier
VFB
4
VBURH/VBURL
Green-
Mode
OSC
Controller
VBIAS
VREF
Q
Q
S
R
IPK
Gate
Driver
3R
R
PWM
Soft
Start
LEB
ILIMIT
3
5
VSENSE
650ms
Protection
Timing Control
VSENSE
VCOMP
40ms
Delay
LEB
RSENSE
VOLP
Vcc
1
GND
VFB
VAOCP
VOVP
TSD
VOFLP
Figure 3. Internal Block Diagram
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
2
Pin Configuration
Drain
Drain
GND
VCC
7DIP
ILIMIT
VFB
Vcomp
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
Ground. SenseFET source terminal on the primary side and internal control ground.
1
GND
Positive Supply Voltage Input. This pin is the positive supply input, which provides the
internal operating current for startup and steady-state operation. This pin voltage is regulated
to 10 V, without the external bias circuit, via internal switch (see Figure 3). When the external
bias voltage is higher than 10 V, it disables the internal high-voltage regulator and reduces
power consumption. It is used to prevent the over voltage protection when VCC exceeds
24.5 V.
2
VCC
Peak Current Limit. Adjusts the peak current limit of the SenseFET. The internal 50 µA
current source is diverted to the parallel combination of an internal 46 kΩ (3R + R) resistors
and any external resistor to GND on this pin to determine the peak current limit.
3
4
5
ILIMIT
Feedback Voltage. Inverting input of the transconductance amplifier. This pin controls
converter output voltage by outputting a current proportional to the difference between the
reference voltage and the output voltage divided by external resistors. It is triggered when
Feedback voltage drops below 0.5 V for the Open Feedback Loop Protection (OFLP).
VFB
Comp Voltage. Output of the transconductance amplifier. The compensation networks are
placed between the VCOMP and GND pins to achieve stability and good dynamic performance.
VCOMP voltage used to prevent the over load protection when VCOMP voltage exceeds 3 V.
VCOMP
Drain. High-voltage power SenseFET drain connection. In addition, during startup and steady-
state operation; the internal high-voltage current source supplies internal bias and charges the
external capacitor connected to the VCC pin. Once VCC reaches 8 V, all internal blocks are
activated. The internal high-voltage current source is enabled until VCC reaches 10 V. After
that, the internal high-voltage regulator turns on and off regularly to maintain VCC at 10 V.
6,7
Drain
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C, unless otherwise specified.
Symbol
Parameter
Drain Pin Voltage
Min.
Max.
Unit
VDS
VCC
VCOMP
VFB
-0.3
-0.3
-0.3
-0.3
-0.3
650.0
V
V
Supply Voltage
26.0
VCOMP Pin Voltage
Internally Clamped Voltage(4)
V
Feedback Voltage
12.0
12.0
2.8
V
ILIMIT
IDM
Current Limit Pin Voltage
Drain Current Pulsed(5)
Single Pulsed Avalanche Energy(6)
Total Power Dissipation
Operating Junction Temperature(7)
Maximum Junction Temperature
Storage Temperature
V
A
EAS
10.5
1.25
125
150
150
mJ
W
°C
°C
°C
PD
-40
-55
TJ
TSTG
Notes:
4. VCOMP is clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 μA)
5. Repetitive rating: pulse width is limited by maximum junction temperature.
6. L=10 mH, starting TJ=25C.
7. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Thermal Impedance
TA=25°C unless otherwise specified.
Symbol
Parameter
Value
Unit
θJA
Junction-to-Ambient Thermal Impedance(8)
100
°C/W
Note:
8. JEDEC recommended environment, JESD51-2, and test board, JESD51-3, with minimum land pattern.
ESD Capability
Symbol
Parameter
Human Body Model, JESD22-A114(9)
Charged Device Model, JESD22-C101(9)
Value
Unit
4
2
ESD
kV
Note:
9. Meets JEDEC standards JESD 22-A114 and JESD 22-C101.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
4
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
SenseFET Section
Drain Source Breakdown
Voltage
BVDSS
IDSS
RDS(ON)
CISS
COSS
CRSS
VCC = 0 V, ID = 250 µA
VDS = 520 V, TA = 125°C
VGS = 10 V, ID = 0.3 A
650
V
Zero Gate Voltage Drain
Current
250
30
µA
Ω
Drain-Source On-State
Resistance
20
97
VGS = 0 V, VDS = 25 V,
f = 1 MHz
Input Capacitances
pF
pF
pF
VGS = 0 V, VDS = 25 V,
f = 1 MHz
Output Capacitance
13.6
2.4
VGS = 0 V, VDS = 25 V,
f = 1 MHz
Reverse Transfer Capacitance
tr
tf
Rise Time
Fall Time
VDD = 325 V, ID = 0.7 A
VDD = 325 V, ID = 0.7 A
7.6
ns
ns
26.1
Control Section
fOSC Switching Frequency
fM
VCOMP = 2.5 V
45
50
±3
55
kHz
kHz
µs
Frequency Modulation(10)
Maximum Turn-On Time
VCOMP = 2.5 V, Randomly
VCOMP = 2.5 V
ton.max
VSTART
VSTOP
IPK
11.2
7.2
6.3
35
13.3
8.0
7.0
50
15.4
8.8
7.7
65
VCOMP = 0 V, VCC Sweep
After Turn On
V
UVLO Threshold Voltage
V
Current Limit Source Current
Soft-Start Time
VCOMP = 2.5 V
µA
ms
tSS
VCOMP = 2.5 V
7
10
13
Burst Mode Section
Burst-mode HIGH Threshold
Voltage
VBURH
VCC = 15 V, VCOMP Increase
VCC = 15 V, VCOMP Decrease
0.67
0.59
0.75
0.83
0.76
V
Burst-mode LOW Threshold
Voltage
VBURL
0.69
60
V
HYSBUR
Burst-mode Hysteresis
mV
Protection Section
VCOMP = 2.5 V, di/dt =
300 mA/µs,
ILIM
Peak Current Limit
0.27
0.30
0.33
A
tCLD
Current Limit Delay(10)
Overload Protection
200
3.3
ns
V
VOLP
VCOMP Increase
VCOMP = 2.5 V
2.7
0.8
3.0
1.0
Abnormal Over-Current
Protection(10)
VAOCP
1.2
V
tLEB
VOFLP
VOVP
Leading-Edge Blanking Time(10)
FB Open Loop Protection
Over-Voltage Protection
200
0.5
ns
V
VFB Decrease
VCC Increase
0.4
0.6
23.0
24.5
26.0
V
Thermal Shutdown
Temperature(10)
TSD
125
135
150
°C
HYSTSD
tDELAY
TSD Hysteresis Temperature(10)
Overload Protection Delay(10)
Restart Time After Protection(10)
60
40
°C
ms
ms
VCOMP > 3 V
tRESTART
650
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
5
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
Transconductance Amplifier Section
Transconductance of Error
Amplifier
Gm
190
240
290
µmho
VREF
IEA.SR
IEA.SK
Voltage Feedback Reference
Output Sourcing Current
Output Sink Current
2.45
2.50
-12
12
2.55
V
VFB = VREF - 0.05 V
VFB = VREF + 0.05 V
µA
µA
High-Voltage Regulator Section
VHVREG HV Regulator Voltage
Total Device Section
Operating Supply Current
VCOMP = 0 V, VDRAIN = 40 V
9
10
11
V
IOP1
(Control Part Only, without
Switching)
0 V < VCOMP < VBURL
0.25
0.35
1.3
mA
Operating Supply Current
(While Switching)
IOP2
ICH
VBURL < VCOMP < VOLP
0.8
6
mA
mA
µA
Startup Charging Current
VCC = 0 V, VDRAIN > 40 V
VCC = Before VSTART
VCOMP = 0 V
,
ISTART
Startup Current
120
155
VCC = VCOMP = 0 V,
VDRAIN Increase
VDRAIN
Minimum Drain Supply Voltage
35
V
Note:
10. Though guaranteed by design, they are not 100% tested in production.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
6
Typical Performance Characteristics
Switching Frequency (fOSC
)
HV Regulator Voltage (VHVREG)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Figure 5. Operating Frequency vs. Temperature
Temperature (℃)
Figure 6. HV Regulator Voltage vs. Temperature
Start Threshold Voltage (VSTART
)
Stop Threshold Voltage (VSTOP)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Figure 7. Start Threshold Voltage vs. Temperature
Temperature (℃)
Figure 8. Stop Threshold Voltage vs. Temperature
Burst Mode High Voltage (VBURH
)
Burst Mode Low Voltage (VBURL)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 9. Burst Mode High Voltage vs. Temperature Figure 10. Burst Mode Low Voltage vs. Temperature
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
7
Typical Performance Characteristics (Continued)
Operating Supply Current (IOP1
)
Feedback Voltage Reference (VREF)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 11. Operating Supply Current 1
vs. Temperature
Figure 12. Feedback Voltage Reference
vs. Temperature
Transconductance of gm amp (Gm)
FB Open Loop Protection (VFB_OLP)
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.15
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 13. Transconductance of gm Amplifier
vs. Temperature
Figure 14. FB Open Loop Protection Voltage
vs. Temperature
Overload Protection (VOLP)
Over-Voltage Protection (VOVP)
1.15
1.15
1.10
1.05
1.00
0.95
0.90
0.85
1.10
1.05
1.00
0.95
0.90
0.85
-40
-20
0
25
50
75
100 125
-40
-20
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Figure 15. Overload Protection vs. Temperature
Figure 16. Over-Voltage Protection vs. Temperature
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
8
Functional Description
1. Startup and High-Voltage Regulator
3. Feedback Control
During startup, an internal high-voltage current source
(ICH) of the high-voltage regulator supplies the internal
bias current (ISTART) and charges the external capacitor
(CA) connected to the VCC pin, as illustrated in Figure
17. This internal high-voltage current source is enabled
until VCC reaches 10 V. During steady-state operation,
this internal high-voltage regulator (HVREG) maintains
FSL3276ALR employs current-mode control with a
transconductance amplifier for feedback control, as
shown in Figure 19. Two resistors are typically used on
the VFB pin to sense output voltage. An external
compensation circuit is recommended on the VCOMP pin to
control output voltage.
A built-in transconductance
amplifier accurately controls output voltage without
external components, such as Zener diode and transistor.
the VCC with 10 V and provides operating current (IOP
)
for all internal circuits. Therefore, FSL3276ALR needs
no external bias circuit. The high-voltage regulator is
disabled when the external bias is higher than 10 V.
Drain
6,7
Green-
mode
Controller
OSC
VOUT
VBIAS
Transconductance
Amplifier
IPK
VFB
VDC.link
3R
4
5
PWM
LEB
Gate
VREF
D1
D2
R
driver
Drain
6,7
VCOMP
VCC
RSENSE
ICH
2
10V HVREG
CC1
RC1
CC2
ISTART (during start-up)
Iop (during steady-state operation)
CA
VBIAS
UVLO
Figure 19. Pulse Width Modulation (PWM) Circuit
3.1
Transconductance Amplifier (gm Amplifier)
The output of the transconductance amplifier sources
and sinks the current, respectively, to and from the
compensation circuit connected on the VCOMP pin (see
Figure 20). This compensated VCOMP pin voltage
controls the switching duty cycle by comparing with the
voltage across the RSENSE. When the feedback pin
voltage exceeds the internal reference voltage (VREF) of
2.5 V; the transconductance amplifier sinks the current
from the compensation circuit, VCOMP is pulled down,
and the duty cycle is reduced. This typically occurs
when input voltage is increased or output load is
decreased. A two-pole and one-zero compensation
network is recommended for optimal output voltage
Figure 17. Startup and HVREG Block
2. Oscillator Block
The oscillator frequency is set internally and the
FSL3276ALR has random frequency fluctuation
a
function. Fluctuation of the switching frequency can
reduce EMI by spreading the energy over a wider
frequency range than the bandwidth measured by the
EMI test equipment. The amount of EMI reduction is
directly related to the range of the frequency variation.
The range of frequency variation is fixed internally;
however, its selection is randomly chosen by the
combination of an external feedback voltage and an
internal free-running oscillator. This randomly chosen
switching frequency effectively spreads the EMI noise
near switching frequency and allows the use of a cost-
effective inductor instead of an AC input line filter to
satisfy world-wide EMI requirements.
control and AC dynamics. Typically 220 nF, 220 kΩ, and
330 pF are used for CC1, RC1, and CC2, respectively.
IEA [A]
Sinking current 12uA at
2.55V
+24uA
-24uA
IDS
several
mseconds
tSW=1/fSW
Sourcing current 12uA at
2.45V
tSW
t
Dt
GM [umho]
fSW
480umho
MAX
fSW+1/2DfSW
240umho
MAX
no repetition
fSW-1/2DfSW
VFB
2.4V
2.6V
VFB
VREF
(2.5V)
several
miliseconds
Figure 20. Characteristics of gm Amplifier
t
Figure 18. Frequency Fluctuation Waveform
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
9
3.2
Pulse-by-pulse Current Limit
path limits the maximum power current and, when the
output consumes more than this maximum power, the
output voltage (VO) decreases below its rated voltage.
This reduces feedback pin voltage, which increases the
output current of the internal transconductance
amplifier. Eventually VCOMP is increased. When VCOMP
reaches 3 V, the internal fixed OLP delay (40 ms) is
activated. After this delay, the switching operation is
terminated, as shown in Figure 22.
Because current-mode control is employed, the peak
current flowing through the SenseFET is limited by the
inverting input of PWM comparator, as shown in Figure
19. Assuming that 50 µA current source flows only
through the internal resistors (3R + R = 46 kΩ), the
cathode voltage of diode D2 is about 2.4 V. Since D1 is
blocked when VCOMP exceeds 2.4 V, the maximum
voltage of the cathode of D2 is clamped at this voltage.
Therefore, the peak value of the current of the
SenseFET is limited.
OSC
OLP
Q
Q
S
R
3R
3.3
Leading Edge Blanking (LEB)
PWM
Gate
driver
At the instant the internal SenseFET is turned on;
primary-side capacitance and secondary-side rectifier
diode reverse recovery of flyback application, the
freewheeling diode reverse recovery, and other parasitic
capacitance of buck application typically cause a high-
current spike through the SenseFET. Excessive voltage
across the sensing resistor (RSENSE) leads to incorrect
feedback operation in the current-mode control. To
counter this effect, the FSL3276ALR has a Leading-
Edge Blanking (LEB) circuit (see Figure 19). This circuit
inhibits the PWM comparator for a short time (tLEB) after
the SenseFET is turned on.
LEB
R
VCOMP
RSENSE
5
40ms
delay
OLP
VOLP
Figure 21. Overload Protection Internal Circuit
Vcc
HVREG
VSTART
VSTOP
20ms
Ids
40ms 650ms
Normal
with SS
SS 40ms 650ms
4. Protection Circuits
The protective functions include Overload Protection
(OLP), Over-Voltage Protection (OVP), Under-Voltage
Lockout (UVLO), Open Feedback Loop Protection
(OFLP), Abnormal Over-Current Protection (AOCP),
and Thermal Shutdown (TSD). All of the protections
operate in Auto-Restart Mode. Since these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
cost and PCB space. If a fault condition occurs,
switching is terminated and the SenseFET remains off.
At the same time, internal protection timing control is
activated to decrease power consumption and stress on
passive and active components during Auto-Restart.
When internal protection timing control is activated, VCC
is regulated with 10 V through the internal high-voltage
regulator until switching is terminated. This internal
protection timing control continues until restart time
(650 ms) is counted. After counting to 650 ms, the
internal high-voltage regulator is disabled and VCC is
decreased. When VCC reaches the UVLO stop voltage
VSTOP (7 V), the protection is reset and the internal high-
voltage current source charges the VCC capacitor via the
drain pin again. When VCC reaches the UVLO start
voltage, VSTART (8 V), the FSL3276ALR resumes normal
operation. In this manner, Auto-Restart can alternately
enable and disable the switching of the power
SenseFET until the fault condition is eliminated.
Power on
Over loading
Over loading Over loading
disappear
Over loading
disappear
Figure 22. Overload Protection (OLP) Waveform
4.2
Abnormal Over-Current Protection (AOCP)
When output is shorted at high input voltage, much
higher drain current peak than pulse-by-pulse current
limit can flow through the SenseFET because turn on
time is the same as the minimum turn-on time of
FSL3276ALR. Even OLP is occasionally not enough to
protect the FSL3276ALR in that abnormal case, since
severe current stress is imposed on the SenseFET until
OLP is triggered. FSL3276ALR includes the internal
Abnormal Over-Current Protection (AOCP) circuit
shown in Figure 23. The voltage across the RSENSE is
compared with a preset AOCP level (VAOCP) after tLEB
and, if the voltage across the RSENSE is greater than the
AOCP level, the set signal is triggered after four
switching times by an internal 2-bit counter, shutting
down the SMPS, as shown in Figure 24. This LEB time
can inhibit miss-triggering due to the leading-edge
spike.
OSC
AOCP
Q
Q
S
R
3R
PWM
Gate
driver
4.1
Overload Protection (OLP)
LEB
R
Overload is defined as the load current exceeding a pre-
set level due to an unexpected event. In this situation,
the protection circuit should be activated to protect the
SMPS. However, even when the SMPS operates
normally, the OLP circuit can be enabled during the load
transition or startup. To avoid this undesired operation,
an internal fixed delay (40 ms) circuit determines
whether it is a transient situation or a true overload
situation (see Figure 21). The current-mode feedback
RSENSE
LEB
2-bit
counter
AOCP
VAOCP
Figure 23. AOCP Circuit
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
10
Vcc
HVREG
To avoid undesired activation during startup, this
function is disabled during soft-start time.
VSTART
VSTOP
OSC
OFLP
Ids
650ms
650ms
Q
Q
S
R
Normal
with SS
3R
4 switchings
PWM
OFLP
VOUT
Gate
driver
LEB
R
RH
VFB
RSENSE
4
SS
Output Short
disappear
Output Short
RL
& 4 switchings
VOFLP
Figure 24. AOCP Waveform
Thermal Shutdown (TSD)
Figure 26. Open Feedback loop Protection Circuit
4.3
The SenseFET and control IC integrated on the same
package makes it easier to detect the temperature of
the SenseFET. When the junction temperature exceeds
5. Soft-Start
The internal soft-start circuit slowly increases the
SenseFET current after it starts. The typical soft-start
time is 10 ms, as shown in Figure 27, where progressive
increments of the SenseFET current are allowed during
startup. The pulse width to the power switching device is
progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors.
The voltage on the output capacitors is gradually
increased to smoothly establish the required output
voltage. Soft-start also helps to prevent transformer
saturation and reduces stress on the secondary diode.
135°C,
thermal
shutdown
is
activated.
The
FSL3276ALR is restarted after the temperature
decreases to 60°C.
4.4
Over-Voltage Protection (OVP)
If any feedback loop components fail due to a soldering
defect, VCOMP climbs up in manner similar to the
overload situation, forcing the preset maximum current
to be supplied to the SMPS until the OLP is triggered. In
this case, excessive energy is provided to the output
and the output voltage may exceed the rated voltage
before the OLP is activated. To prevent this situation, an
Over-Voltage Protection (OVP) circuit is employed. In
general, output voltage can be monitored through VCC
and, when VCC exceeds 24.5 V, OVP is triggered,
resulting in termination of switching operation. To avoid
undesired activation of OVP during normal operation,
VCC should be designed below 24.5 V (see Figure 25).
1.25ms
ILIM
Soft start envelope
0.2ILIM
OSC
OVP
Drain Current
Q
Q
S
R
3R
PWM
OVP
Gate
driver
8-Steps
t
LEB
R
Figure 27. Internal Soft-Start
VCC
RSENSE
6. Burst Mode Operation
2
To minimize power dissipation in Standby Mode, the
FSL3276ALR enters Burst Mode. As the load decreases,
the comp voltage (VCOMP) decreases. As shown in
Figure 28, the device automatically enters Burst Mode
when the feedback voltage drops below VBURL. At this
point, switching stops and the output voltages start to
drop at a rate dependent on the standby current load.
VOVP
Figure 25. Over Voltage Protection Circuit
Open Feedback Loop Protection (OFLP)
4.5
In the event of a feedback loop failure, especially a
shorted lower-side resistor of the feedback pin; not only
does VCOMP rise in a similar manner to the overload
situation, but VFB starts to drop to IC ground level.
Although OLP and OVP also can protect the SMPS in
this situation, OFLP can reduce stress on SenseFET
more. If there is no OFLP, output voltage is much higher
than rated voltage before OLP or OVP trigger. When
VFB drops below 0.5 V, OFLP is activated, switching off.
This causes VCOMP to rise. Once it passes VBURH
,
switching resumes. VCOMP then falls and the process
repeats. Burst Mode alternately enables and disables
switching of the SenseFET and reduces switching loss
in Standby Mode.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
11
VO
Voset
(1)
300 mA : 70 mA = (46 kΩ + RX): RX
Transconductance
VFB
4
Amplifier
VCOMP
VBIAS
VREF
IPK
VBURH
VBURL
3R
PWM
VCOMP
5
3
R
IDS
ILIMIT
VSENSE
RX
Figure 29. Current Limit Adjustment
VDS
140
130
120
110
100
90
time
Switching
disabled
Switching
disabled
t1
t2 t3
t4
Figure 28. Burst Mode Operation
7. Green Mode Operation
As output load condition is reduced, the switching loss
becomes the largest power loss factor. FSL3276ALR
uses the VCOMP pin voltage to monitor output load
condition. As output load decreases, VCOMP decreases
and switching frequency declines. Once VCOMP drops to
under 0.8 V, the switching frequency varies between
21 kHz and 23 kHz before Burst Mode operation,
random frequency fluctuation still functions.
80
70
15kΩ 18kΩ 20kΩ 24kΩ 27kΩ 30kΩ 33kΩ 39kΩ 43kΩ 47kΩ 51kΩ
Resistance value to adjust the peak current limit
Figure 30. Current Limit vs. Rx
8. Adjusting Current Limit
As shown in Figure 29, the inverting input voltage of a
PWM comparator that determines pulse-by-pulse
current limit level is generated by the internal resistor R
and current IPK with a maximum value of 50 µA. When
the external resistor RX is connected between ILIMIT
and GND, IPK current can be adjusted because the
added Rx will be configured with internal resistor (3R+R)
with total 46 kΩ in parallel and it will flow inversely
proportional to RX value connected. For example, if no
resistor is connected, pulse-by-pulse current limit for
MOSFET switching current will be the maximum level
(300 mA). On the other hand, the minimum level can be
set down to 70 mA by the Rx value that can be got from
following shown in equation (1). Figure 30 shows the
adjusted current limit according to the RX.
© 2015 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSL3276ALR • Rev.1.2
12
9.779
9.525
A
7
5
B
6.477
6.223
PIN #1
(0.787)
4
1
TOP VIEW
7.874
7.620
12°
2.54
12°
3.937
3.683
3.429
3.175
0.381
0.203
3.556
3.048
C
0.508 MIN
SEATING
PLANE
7.53
1.651
1.397
9.398
7.874
0.508
0.406
M
0.10
C
FRONT VIEW
SIDE VIEW
NOTES:
A. REFERENCE JEDEC MS-001, VARIATION BA
EXCEPT FOR NUMBER OF LEADS.
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR EXTRUSIONS.
E. DRAWING FILENAME: MKT-NA07Drev2
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