LV52204MU [ONSEMI]
LED Boost Driver with PWM;
| 型号： | LV52204MU |
| 厂家： | 
ONSEMI |
| 描述： | LED Boost Driver with PWM |
| 文件： | 总16页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA2176A
LV52204MU
Bi-CMOS IC
http://onsemi.com
LED Boost Driver with PWM
and 1-Wire Dimming
Overview
The LV52204MU is a high voltage boost driver for LED drive. LED current is set by the external resistor R1 and LED
dimming can be done by changing FB voltage with PWM or 1-Wire.
Features
• Operating Voltage from 2.7V to 5.5V
• Integrated 40V MOSFET
• 1-Wire 32 level digital and PWM dimming
• 600kHz Switching Frequency
UDFN6 2 × 2 , 0.65P
Typical Applications
• LED Display Backlight Control
D1
L1
22μH
VBAT
C1
1μF
C2
1μF
PWM/
1-WIRE
LV52204
C3
220nF
R1
10Ω
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of this data sheet.
Semiconductor Components Industries, LLC, 2014
May, 2014
51914NK/O0213NK /32013NKPC 20130225-S00003 No.A2176-1/16
LV52204MU
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum supply voltage
Maximum pin voltage1
Maximum pin voltage2
Allowable power dissipation
Operating temperature
Storage temperature
V
max
CC
V
5.5
40
CC
V1 max
V2 max
Pd max
Topr
SW
V
Other pin
Ta = 25°C *1
5.5
V
2.05
W
°C
°C
-30 to +85
-55 to +125
Tstg
*1 Mounted on a specified board: 70mm×50mm×1.2mm (4 layer glass epoxy)
Caution 1) Absolute maximum ratings represent the values which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommendation Operating Condition at Ta = 25°C
Parameter
Supply voltage range1
PWM frequency
Symbol
Conditions
Ratings
Unit
V
V
op
V
2.7 to 5.5
CC
CC
PWM MODE
Fpwm
300 to 100k
Hz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics Analog block at Ta = 25°C, V
= 3.6V, unless otherwise specified
CC
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Standby current dissipation
DC/DC current dissipation
FB voltage
I
I
1
2
SHUTDOWN
= 30V, I
0
0.2
38
5
1
μA
mA
V
CC
V
= 20mA
LED
CC
OUT
Vfb
Ifb
PWM duty 100%
0.19
0.21
1
FB pin leak current
OVP voltage
μA
V
Vovp
Ron
SW
37
39
SWOUT ON resistance
NMOS switch current limit
OSC frequency
IL = 100mA
Vfb = 200mV
700
0.7
mΩ
A
ILIM
Fosc
600
kHz
V
High level input voltage
Low level input voltage
Under voltage lockout
V
V
H
L
SWIRE
SWIRE
1.5
0
V
IN
CC
0.4
V
IN
Vuvlo
Vack
V
falling
2.2
V
IN
Rpullup = 15kΩ
SWIRE output voltage
for Acknowledge
0.4
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
No.A2176-2/16
LV52204MU
Recommended SWIRE Timing at Ta = 25°C, V
= 3.6V, unless otherwise specified
CC
Ratings
typ
Parameter
Symbol
Ton1
Conditions
Unit
min
max
SWIRE setup time1
from shutdown
2
μs
PWM duty more than 2%,
VIN≥3.3V, -30°C to 85°C *2
SWIRE setup time2
from shutdown
Ton2
20
1
μs
SWIRE mode selectable time
Tsel
Tw0
2.2
ms
SWIRE delay time to start
digital mode detection
SWIRE low time to switch to
digital mode
100
μs
Tw1
260
μs
SWIRE low time to shutdown
Toff
8.9
2
ms
SWIRE start time for digital
mode programming
Tstart
μs
SWIRE end time for digital
mode programming
Tend
2
360
μs
SWIRE High time of bit 0
Th0
Tl0
Bit detection = 0
Bit detection = 0
Bit detection = 1
Bit detection = 1
2
Th0 × 2
Tl1 × 2
2
180
360
360
180
μs
μs
μs
μs
ms
μs
μs
SWIRE Low time of bit 0
SWIRE High time of bit 1
SWIRE Low time of bit1
DCDC startup delay
Th1
Tl1
Tdel
Tackd
Tack
2
Delay time of Acknowledge
Duration of Acknowledge
2
512
*2 Guaranteed by design
Block Diagram
VBAT
SW
4
V
CC
6
UVLO
TSD
OCP
OVP
600kHz PWM
Controler
FB
1
3
SWIRE
FCAP
5
2
PWM/
1-Wire
VREF
CONTROL
VREF
GND
No.A2176-3/16
LV52204MU
Pin Connections
FB 1
FCAP 2
GND 3
6 VIN
5 SWIRE/PWM
4 SW
Top view
Pin Function
PIN #
Pin Name
Description
1
2
3
4
5
6
FB
Feedback pin.
FCAP
GND
SW
Filtering capacitor terminal for PWM mode.
Ground
Switch pin. Drain of the internal power FET.
1-wire dimming control and PWM dimming input (active High).
Supply voltage.
SWIRE
V
CC
Expose-pad
Connect to GND on PCB.
Pd max -- Ta
3.0
2.0
Mounted on a specified board: 70×50×1.2mm3
(4 layer glass epoxy)
2.05
1.0
0.82
0
--30
0
30
60
90
120
Ambient temperature, Ta -- °C
No.A2176-4/16
LV52204MU
LED Current Setting
LED current is set by an external resistor connected between the FB pin and ground.
I
= V /R .
FB FB
LED
The V can be controled by two dimming modes, PWM Mode or Digital Mode.In PWM mode, PWM input is
FB
converted into a near DC current by the internal resistor R that was equivalent to 60kΩ (±10%) and the external
capacitor C
as a low pass filter with a cut-off frequency fc = 1/2πR
. The V can be adjusted by altering
FCAP
FCAP
FB
the duty cycle of the PWM signal (See Fig.1).
= 200 (mV) × PWM Duty (%)
V
FB
On the other hand, V can be selected one from among 32steps in Digital Mode (See Fig.2).
FB
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
60
40
40
20
0
20
0
0
10
20
30
40
50
60
70
80
90
100
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
PWM Duty (%)
Data
Fig1. V
FB
vs. PWM Duty (PWM mode)
Fig2. V
vs. Data Register Value (Digital mode)
FB
Dimming Mode Selection
Dimming Mode is selected by a specific pattern of the SWIRE within Tsel (1ms) from the startup of the device every
time. In order to startup the device, the SWIRE must keep high for longer than Ton.
PWM Mode
The dimming mode is set to PWM mode when it is not recognized as a digital mode within Tsel. To enter Digital Mode,
the SWIRE is required keeping in low state for Tw1 (See Fig.4). If the PWM frequency is used faster than 6.6kHz, the
dimming mode is set to PWM mode only. But slower than 6.6kHz, it is necessary to avoid entering the digital mode
condition, such as SWIRE keeps high for longer than Tsel. PWM is enabled after Tdel from Tsel.
Tsel
Tdel
Ton
Toff
Shutdown
SWIRE
(PWM Freq > 6.6kHz)
PWM Enable
Tsel
Tdel
Toff
Shutdown
SWIRE
(PWM Freq < 6.6kHz)
PWM Enable
Fig3. SWIRE Timing Diagram in PWM mode
No.A2176-5/16
LV52204MU
Digital Mode
To enter Digital Mode, SWIRE should be taken high for more than Tw0 (100μs) from the first rising edge and keep low
state for Tw1(260μs) before Tsel(1ms).
Tdel
Tsel
Tw1
Toff
Shutdown
Tw0
Shutdown
SWIRE
Device Address & data
Device Address & data
Digital Mode
Fig4. SWIRE Timing Diagram in Digital mode
It is required sending the device address byte and the data byte to select V . The bit detection is determined by the
FB
ratio of Th and Tl (See Fig6). The start condition for the bit transmission required SWIRE high for at least Tstart. The
end condition is required SWIRE low for at least Tend.When data is not being transferred, SWIRE is set in the “H” state.
These registers are initialized with POR (Power On Reset).
In the LV52204MU, the device address (DA7 to DA0) is specified as “01110010”. D7 is setting for the acknowledge
response. If the device address and the data byte are transferred on D7 = 1, the ACK signal is sent from the receive side
to the send side. The acknowledge signal is issued when SWIRE on the send side is released and SWIRE on the receive
side is set to low state. D6 and D5 need to send 0. D4 to D0 allow to changing the FB voltage.
Register
DA7
BIT
7
Description
0
1
1
1
0
0
1
0
DA6
6
DA5
5
DA4
4
Device
Address
DA3
3
DA2
2
DA1
1
DA0
0
Table1. Device Address Description
Register
D7
BIT
Description
0 = Acknowledge disabled
1 = Acknowledge enabled
7
D6
D5
D4
D3
D2
D1
D0
6
5
4
3
2
1
0
0
0
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
Data
Table2. Data Description
FB Voltage Control
FB Voltage Control
S
S
0
0
1
1
1
1
0
0
1
0
E
E
S
0
0
0
E
E
Device Address
ACK:Disable
1
1
0
0
1
0
S
1
0
0
A
Device Address
Start Condition
ACK:Enable
End Condition
S
E
A
Acknowledge
Fig5. Example of writing data
No.A2176-6/16
LV52204MU
Tstart
Tstart
DA7
DA0
D7
D0
TI0 > Th0 * 2
Tend
Tend
Data
(D7 to D0)
Device Address
(DA7 to DA0)
TI0 Th0
Low state (Bit=0)
Acknowledge : Disable (D7 = D0)
Tstart
Tstart
Tack
TI1 > Th1 * 2
A
C
K
TI1 Th1
High state (Bit=1)
DA7
DA0
D7
D0
Tend
Tack
Device Address
(DA7 to DA0)
Data
(D7 to D0)
Acknowledge : Enable (D7 = 1)
Fig6.Bit detection Diagram
D7
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FB voltage (mV)
0
0
5
1
2
8
3
11
4
14
5
17
6
20
7
23
8
26
9
29
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
35
38
44
50
56
62
68
74
80
86
92
98
104
116
128
140
152
164
176
188
*200
(*Default)
Table3. Data Register vs. FB Voltage
No.A2176-7/16
LV52204MU
Start up and Shutdown
The device becomes enabled when SWIRE is initially taken high.The dimming mode is determined within Tsel and the
boost converter start up after Tdel. To place the device into shutdown mode, the SWIRE must be held low for Toff.
PWM MODE
V
IN
Tsel
Tdel
Toff
SWIRE
FB
200m * duty
Shutdown delay
FCAP
DCDC_EN
(internal signal)
Digital MODE
V
IN
Tdel
Tsel
Tw1
Toff
SWIRE
Device Address & data
Device Address & data
Programed value
Shutdown delay
Tw0
FB
FCAP
DCDC_EN
(internal signal)
Fig7.Start up and shutdown diagram
No.A2176-8/16
LV52204MU
Open LED Protection
If SW terminal voltage exceeds a threshold Vovp (38V typ) for 8 cycles, boost converter enters shutdown mode. In
order to restart the IC, SWIRE signal is required again.
Over Current Protection
Current limit value for built-in power MOS is around 0.7A. The power MOS is turned off for each switching cycle when
peak current through it exceeds the limit value.
Under Voltage Lock Out (UVLO)
UVLO operation works when V terminal voltage is below 2.2V.
IN
Thermal Shutdown
When chip temperature is too high, boost converter is stopped.
Application Circuit Diagram
10LEDs
D1
L1
22μH
VBAT
C1
1μF
C2
1μF
PWM/
1-Wire
C3
220nF
R1
10Ω
L1: VLS3012T-220M49 (TDK), VLF504015MT-220M (TDK)
D1: MBR0540T1 (ON semi), NSR05F40 (ONsemi)
C2: GRM21BR71H105K (Murata), C1608X5R1H105K (TDK)
No.A2176-9/16
LV52204MU
6LEDs
D1
L1
10μH
VBAT
C1
1μF
C2
1μF
PWM/
1-WIRE
C3
220nF
R1
10Ω
L1: VLS3012T-100M72 (TDK), VLF302512M-100M (TDK)
D1: MBR0540T1 (ON semi), NSR05F40 (ONsemi)
C2: GRM21BR71H105K (Murata), C1608X5R1H105K (TDK)
No.A2176-10/16
LV52204MU
Typical Characteristics (V = 3.6V, L = 22μH, T = 25°C, unless otherwise specified)
IN
Efficiency -- Output current
=3.6V
Efficiency -- Output current
100
90
80
70
60
100
90
80
70
60
V
10LED
IN
10LED
8LED
3.6V
50
40
50
40
0
5
10
15
20
0
5
10
15
20
100
90
LED current -- mA
LED current -- mA
FB voltage -- DATA register
Mode=Digital
FB voltage -- PWM duty
200
150
100
200
150
100
Mode=PWM
50
0
50
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
0
10
20
30
40
50
60
70
80
90
Data register
PWM duty -- %
FB voltage -- Temperature
FB voltage -- Temperature
200
180
160
200
180
160
Duty=100%
DATA=31
140
120
100
80
140
120
100
80
Duty=50%
Duty=10%
DATA=16
60
60
40
40
DATA=06
20
0
20
0
Mode=Digital
Mode=PWM
--30
--15
0
15
30
45
60
75
90
--30
--15
0
15
30
45
60
75
Temperature -- °C
Temperature -- °C
V
current -- V
LED current -- PWM frequency
IN
IN
1000
20
800
600
400
75%
50%
25%
15
10
5
0
200
0
2
3
4
5
6
0.1
1
10
100
V
IN
-- V
PWM frequency -- kHz
No.A2176-11/16
LV52204MU
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB
ISSUE C
NOTES:
D
A
B
E
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE
TERMINALS.
NOTE 5
PIN ONE
REFERENCE
5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED
TO THE THERMAL PAD.
MILLIMETERS
DIM
A
A1
A3
b
MIN
0.45
0.00
0.127 REF
0.25
MAX
0.55
0.05
0.10 C
END VIEW
0.10 C
0.35
TOP VIEW
D
2.00 BSC
D2
E
E2
e
1.50
2.00 BSC
0.80
0.65 BSC
1.70
A3
A3
EXPOSED Cu
MOLD CMPD
DETAIL B
1.00
0.10 C
L
L1
0.25
---
0.35
0.15
A
A1
0.08 C
6X
A1
SEATING
PLANE
GENERIC
MARKING DIAGRAM*
DETAIL B
NOTE 4
C
SIDE VIEW
D2
ALTERNATE
CONSTRUCTIONS
DETAIL A
XXM
L
L
L
1
3
XX = Specific Device Code
L1
M
= Date Code
= Pb−Free Package
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E2
(Note: Microdot may be in either location)
6
4
6X
b
e
M
0.10 C A
B
M
0.05
C
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
OUTLINE
1.70
6X
0.47
2.30
0.95
1
0.65
6X
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
LV52204MU is as follows.
MARKING DIAGRAM
T4 = Device Code
M
= Date Code
= Pb-Free Package
No.A2176-12/16
LV52204MU
No.A2176-13/16
LV52204MU
No.A2176-14/16
LV52204MU
No.A2176-15/16
LV52204MU
RDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
3000 / Tape & Reel
UDFN6 (2×2)
( Pb-Free )
LV52204MUTBG
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PS No.A2176-16/16
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