M74VHCT157ADTR2G [ONSEMI]
Quad 2−Channel Multiplexer; 四路2通道多路复用器
| 型号： | M74VHCT157ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2−Channel Multiplexer |
| 文件： | 总7页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT157A
Quad 2−Channel Multiplexer
The MC74VHCT157A is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2−input digital multiplexers with common select
(S) and enable (E) inputs. When E is held High, selection of data is
inhibited and all the outputs go Low.
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MARKING
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
DIAGRAMS
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5.0 V CMOS level output swings.
The VHCT157A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
16
1
SOIC−16
D SUFFIX
CASE 751B
VHCT157AG
AWLYWW
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage−input/output voltage mismatch, battery backup, hot
insertion, etc.
The inputs tolerate voltages up to 7.0 V, allowing the interface of
5.0 V systems to 3.0 V systems.
16
VHCT
157A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
1
Features
• High Speed: t = 4.1 ns (Typ) at V = 5.0 V
PD
CC
16
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT157
ALYWG
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
1
1
• Designed for 2.0 V to 5.5 V Operating Range
A
WL, L
Y
= Assembly Location
= Wafer Lot
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
= Year
WW, W = Work Week
G or G
= Pb−Free Package
• ESD Performance:
(Note: Microdot may be in either location)
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 82 FETs or 20 Equivalent Gates
• Pb−Free Packages are Available*
FUNCTION TABLE
Inputs
Outputs
E
S
Y0 − Y3
H
L
L
X
L
H
L
A0−A3
B0−B3
A0 − A3, B0 − B3 = the levels of
the respective Data−Word Inputs.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 2
MC74VHCT157A/D
MC74VHCT157A
V
E
S
1
2
16
15
CC
A0
B0
Y0
A3
B3
Y3
A2
B2
Y2
3
4
14
13
A1
5
6
12
11
B1
7
8
10
Y1
GND
9
Figure 1. Pin Assignment
2
3
A0
B0
A1
B1
4
7
Y0
5
6
Y1
Y2
NIBBLE
INPUTS
DATA
OUTPUTS
11
10
14
13
A2
B2
A3
B3
9
12
Y3
15
1
E
S
Figure 2. Expanded Logic Diagram
15
1
E
S
EN
G1
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high−impedance circuit. For
2
3
5
6
MUX
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
proper operation, V and V
should be
in
out
11
10
14
13
A2
B2
9
constrained to the range GND v (V or V
)
in
out
v V
.
CC
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
A3
B3
12
GND or V ). Unused outputs must be left
CC
open.
Figure 3. IEC Logic Symbol
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2
MC74VHCT157A
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
CC
V
V
IN
V
DC Output Voltage
Output in 3−State
V
OUT
High or Low State
−0.5 to V +0.5
CC
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
OUT
I
DC Supply Current, V and GND Pins
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ESD
Charged Device Model (Note 4)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
$300
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
143
164
°C/W
JA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
4.5
0
Max
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
5.5
V
IN
V
Output in 3−State
High or Low State
0
V
V
OUT
CC
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
0
125
20
°C
A
t , t
r
V = 5.0 V + 0.5 V
CC
ns/V
f
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO
0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHCT157A
DC CHARACTERISTICS (Voltages Referenced to GND)
V
T
A
= 25°C
T
A
≤ 85°C
−55°C ≤ T ≤
A
CC
125°C
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Min
Max Unit
V
Minimum High−Level Input
Voltage
4.5 to
5.5
2
2
0.8
2
V
IH
V
Maximum Low−Level Input
Voltage
4.5 to
5.5
0.8
0.8
0.8
V
V
IL
V
Maximum High−Level Output
Voltage
V
= V or V
= −50 mA
OH
IN
IH
IL
IL
IL
IL
I
4.5
4.5
4.5
4.4
4.5
0.0
4.4
3.8
4.4
OH
V
= V or V
IN
IH
I
= −8 mA
3.94
3.66
OH
V
Maximum Low−Level Output
Voltage
V
= V or V
V
OL
IN
IH
I
= 50 mA
0.1
0.1
0.1
OL
V
= V or V
IN
IH
I
= 8 mA
4.5
0 to 5.5
5.5
0.36
0.1
0.44
1.0
0.52
1.0
OH
I
Input Leakage Current
V
V
= 5.5 V or GND
mA
mA
IN
IN
IN
I
Maximum Quiescent Supply
Current
= V or GND
4.0
40.0
40.0
CC
CC
I
Additional Quiescent Supply
Current (per Pin)
Any one input:
= 3.4 V
All other inputs:
5.5
1.35
0.5
1.5
5
1.5
5
mA
CCT
V
IN
V
= V or GND
IN
CC
I
Output Leakage Current
V
= 5.5 V
0
mA
OPD
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
−55°C ≤ T
≤
A
125°C
T
A
= 25°C
T = ≤ 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15pF
Unit
t
t
t
,
Maximum Propagation Delay;
A to B to Y
V
V
V
V
V
V
5.6
8.0
7.0
10.0
1.0
1.0
7.7
11.0
1.0
1.0
7.7
11.0
ns
PLH
t
CC
CC
CC
CC
CC
CC
L
C = 50pF
L
PHL
= 5.0 0.5 V C = 15pF
4.1
5.6
6.4
8.4
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
L
C = 50pF
L
,
Maximum Propagation Delay;
S to Y
= 3.3 0.3 V C = 15pF
6.1
8.5
7.5
10.5
1.0
1.0
8.2
11.5
1.0
1.0
8.2
11.5
ns
ns
PLH
L
t
C = 50pF
L
PHL
= 5.0 0.5 V C = 15pF
5.3
6.8
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50pF
L
,
Maximum Propagation Delay;
E to Y
= 3.3 0.3 V C = 15pF
6.1
8.5
7.5
10.5
1.0
1.0
8.2
11.5
1.0
1.0
8.2
11.5
PLH
L
t
C = 50pF
L
PHL
= 5.0 0.5 V C = 15pF
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
L
C = 50pF
L
C
Maximum Input Capacitance
4
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
20
C
PD
Power Dissipation Capacitance (Note 6)
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
0.8
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
V
OLP
OL
Quiet Output Minimum Dynamic V
− 0.3
− 0.8
2.0
V
V
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
IHD
V
0.8
ILD
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4
MC74VHCT157A
V
V
CC
CC
50%
50%
A, B or S
A, B or S
GND
GND
t
t
PHL
PHL
t
t
PLH
PLH
50% V
50% V
CC
CC
Y
Y
Figure 5. Switching Waveform
Figure 6. Inverting Switching
TEST POINT
OUTPUT
DEVICE
UNDER
C *
L
TEST
INPUT
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT157AD
MC74VHCT157ADG
SOIC−16
48 Units / Rail
48 Units / Rail
SOIC−16
(Pb−Free)
MC74VHCT157ADR2
MC74VHCT157ADR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74VHCT157ADT
MC74VHCT157ADTG
MC74VHCT157ADTR2
M74VHCT157ADTR2G
MC74VHCT157AM
TSSOP−16*
TSSOP−16*
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
96 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
50 Units / Rail
MC74VHCT157AMG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74VHCT157AMEL
MC74VHCT157AMELG
SOEIAJ−16
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74VHCT157A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T B
A
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
F
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
−T−
D
PLANE
G
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6
MC74VHCT157A
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
F
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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For additional information, please contact your
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MC74VHCT157A/D
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128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000009
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
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