MC100E136FNG [ONSEMI]
5V ECL 6-Bit Universal Up/Down Counter; 5V ECL 6位通用加/减计数器
| 型号： | MC100E136FNG |
| 厂家： | 
ONSEMI |
| 描述： | 5V ECL 6-Bit Universal Up/Down Counter |
| 文件： | 总12页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E136, MC100E136
5VꢀECL 6-Bit Universal
Up/Down Counter
Description
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. The device generates a look-ahead-carry
output and accepts a look-ahead-carry input. These two features allow
for the cascading of multiple E136’s for wider bit width counters that
operate at very nearly the same frequency as the stand alone counter.
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count.
For more information on utilizing the look-ahead-carry features of the
device please refer to the applications section of this data sheet. The
differential COUT output facilitates the E136’s use in programmable
divider and self-stopping counter applications.
Unlike the H136 and other similar universal counter designs, the E136
carry−out and look-ahead-carry−out signals are registered on chip.
This design alleviates the glitch problem seen on many counters
where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the
E136 and H136 counters. The user, regardless of familiarity with the
H136, should read this data sheet carefully. Note specifically (see
logic diagram) the operation of the carry out outputs and the
look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input
pull−down resistor. The master reset is an asynchronous signal which
when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function
properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left
open. This practice will minimize switching noise which can reduce
the maximum count frequency of the device or significantly reduce
margins against other noise in the system.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE136G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
The 100 Series contains temperature compensation.
Features
• 550 MHz Count Frequency
• Meets or Exceeds JEDEC Standard EIA/JESD78
IC Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 506 devices
• Fully Synchronous Up and Down Counting
• Look-Ahead-Carry Input and Output
• Asynchronous Master Reset
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Pb−Free Packages are Available*
• Internal Input 50 kW Pulldown Resistors
• ESD Protection: Human Body Model: > 2 kV,
Machine Model: > 200 V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 9
MC10E136/D
MC10E136, MC100E136
D3
D4
24
D5
23
V
Q5
21
Q4
20
V
CCO
CCO
22
19
25
26
27
18
D2
S2
Q3
17
Q2
S1
16
28
1
V
V
CC
V
15
14
EE
CCO
Pinout: 28-lead PLCC
(Top View)
CLK
2
COUT
COUT
13
12
CIN
3
4
CLIN
CLOUT
5
6
7
8
9
10
11
MR
D1
D0
V
Q0
Q1
V
CCO
CCO
* All V and V
pins are tied together on the die.
CCO
CC
Warning: All V , V
, and V pins must be externally con-
CCO EE
CC
nected to Power Supply to guarantee proper operation.
Figure 1. 28−Lead Pinout
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D
0
− D
ECL Preset Data Inputs
5
Q
S1, S2
MR
− Q
ECL Data Outputs
Mode Control Pins
Master Reset
0
5
CLK
ECL Clock Input
COUT,
COUT
ECL Differential Carry-Out Output (Active
LOW)
CLOUT
CIN
CLIN
ECL Look-Ahead-Carry Out (Active LOW)
ECL Carry-In Input (Active LOW)
ECL Look-Ahead-Carry In Input (Active LOW)
Positive Supply
V
V
, V
CC CCO
EE
Negative Supply
Table 2. FUNCTION TABLE
(Expanded Truth Table on page 3)
S1
S2
CIN MR CLK
FUNCTION
L
L
L
H
H
L
X
L
H
L
H
X
X
L
L
L
L
L
L
H
Z
Z
Z
Z
Z
Z
X
Preset Parallel Data
Increment (Count Up)
Hold Count
Decrement (Count Down)
Hold Count
Hold Count
Reset (Qn = LOW)
L
H
H
H
X
L
H
X
Figure 2. E136 Universal Up/Down Counter Logic
Diagram
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2
MC10E136, MC100E136
Table 3. EXPANDED TRUTH TABLE
Function S1 S2 MR CIN CLIN CLK D5 D4 D3 D2 D1 D0 Q5 Q4 Q3 Q2 Q1 Q0 COUT CLOUT
Preset
Down
L
L
L
X
X
Z
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
H
H
L
H
L
H
H
H
H
Preset
Up
L
L
L
X
X
Z
H
H
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
Hold
L
L
Hold
Preset
Up
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
H
H
Hold
Up
Hold
H
L
H
H
L
Hold
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
Z = Low to High Transition
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3
MC10E136, MC100E136
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
PECL Mode Power Supply
NECL Mode Power Supply
V
V
8
CC
EE
I
EE
CC
= 0 V
−8
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
0 to +85
°C
°C
A
T
Storage Temperature Range
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
JC
V
PECL Operating Range
NECL Operating Range
4.2 to 5.7
−5.7 to −4.2
V
V
EE
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
Typ
25°C
Typ
85°C
Typ
Min
Max
150
Min
Max
150
Min
Max
150
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
125
125
125
EE
V
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
3980
3050
3830
3050
4070
3210
3995
3285
4160
3370
4160
3520
150
4020
3050
3870
3050
4105
3210
4030
3285
4190
3370
4190
3520
150
4090
3050
3940
3050
4185
3227
4110
3302
4280
3405
4280
3555
150
OH
OL
IH
V
V
V
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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4
MC10E136, MC100E136
Table 6. 10E SERIES NECL DC CHARACTERISTICS V
0°C
= 0.0 V; V = −5.0 V (Note 3)
EE
CCx
25°C
Typ
85°C
Typ
Min
Typ
125
Max
Min
Max
150
Min
Max
150
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
Input HIGH Voltage
Unit
mA
mV
mV
mV
mV
mA
I
150
125
125
EE
V
−1020
−930
−840
−980
−895
−810
−910
−815
−720
OH
OL
IH
V
V
V
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445
150 150 150
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.065
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
4. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 7. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 5)
CCx
EE
0°C
Typ
25°C
85°C
Typ
Min
Max
150
Min
Typ
125
Max
150
Min
Max
170
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mA
I
125
140
EE
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
Input HIGH Voltage
3975
3190
3835
3190
4050
3295
3975
3355
4120
3380
4120
3525
150
3975
3190
3835
3190
4050
3255
3975
3355
4120
3380
4120
3525
150
3975
3190
3835
3190
4050
3260
3975
3355
4120
3380
4120
3525
150
OH
OL
IH
V
V
V
Input LOW Voltage
IL
I
I
Input HIGH Current
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
6. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 8. 100E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 7)
CCx
EE
0°C
Typ
125
25°C
85°C
Typ
140
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Typ
Max
Min
Max
170
Unit
mA
mV
mV
mV
mV
mA
I
150
125
150
EEf
V
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Input HIGH Voltage
−1025 −950
−880 −1025 −950
−880 −1025 −950
−880
OH
OL
IH
V
V
V
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475
Input LOW Voltage
IL
I
I
Input HIGH Current
150
150
150
IH
IL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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5
MC10E136, MC100E136
Table 9. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 9)
CCx EE
CCx
EE
0°C
25°C
Typ
650
85°C
Typ
650
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
MHz
ps
f
Maximum Count Frequency
550
650
−
550
−
550
−
COUNT
t
t
Propagation Delay to Output
PLH
PHL
CLK to Q
MR to Q
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
850
850
800
825
1150
1150
1150
1150
1450
1450
1300
1400
CLK to COUT
CLK to CLOUT
t
t
Setup Time
Hold Time
ps
ps
s
S1, S2 1000
650
400
0
−
−
−
−
1000
800
150
800
650
400
0
−
−
−
−
1000
800
150
800
650
400
0
−
−
−
−
D
CLIN
CIN
800
150
800
400
400
400
h
S1, S2
D
CLIN
CIN
150
150
300
150
−200
−250
0
−
−
−
−
150
150
300
150
−200
−250
0
−
−
−
−
150
150
300
150
−200
−250
0
−
−
−
−
−250
−250
−250
t
t
t
Reset Recovery Time
Random Clock Jitter
Minimum Pulse Width
1000
700
< 1
−
1000
700
< 1
−
1000
700
< 1
−
ps
ps
ps
RR
JITTER
PW
CLK, MR
700
250
400
425
−
700
250
400
425
−
700
250
400
425
−
t
t
Rise/Fall Times 20% - 80%
600
600
600
ps
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
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6
MC10E136, MC100E136
APPLICATIONS INFORMATION
Overview
result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
The MC10E/100E136 is a 6-bit synchronous, presettable,
cascadable universal counter. Using the S1 and S2 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CLIN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.
Note from the schematic the use of the master information
from the least significant bits for control of the two carry out
functions. This architecture not only reduces the carry out
delay, but is essential to incorporate the registered carry out
functions. In addition to being faster, because these
functions are registered the resulting carry out signals are
stable and glitch free.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately
these types of counters require external gating for cascading
designs of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there
is a performance impact with this type of architecture it is
minor compared to the impact of the ripple propagate
designs. As a result the E016 type counters have been used
extensively in applications requiring very high speed, wide
bit width synchronous counters.
ON Semiconductor has incorporated several improvements
to past universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader in
its class. With the addition of look-ahead-carry features on the
terminal count signal, very large counter chains can be
designed which function at very nearly the same clock
frequency as a single free running device. More importantly
these counter chains require no external gating. Figure 1 below
illustrates the interconnect scheme for using the
look-ahead-carry features of the E136 counter.
Cascading Multiple E136 Devices
Many applications require counters significantly larger
than the 6 bits available with the E136. For these
applications several E136 devices can be cascaded to
increase the bit width of the counter to meet the needs of the
application.
In the past cascading several 136 type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the
Q0 −> Q5
Q0 −> Q5
Q0 −> Q5
Q0 −> Q5
CLOCK
CLK
CLK
CLK
CLK
LSB
MSB
“LO”
“LO”
COUT “LO”
CLOUT
COUT
CLOUT
COUT
CLOUT
COUT
CLOUT
CIN
CIN
CLIN
CIN
CLIN
CIN
CLIN
CLIN
D0 −> D5
D0 −> D5
D0 −> D5
D0 −> D5
111101
111110
111111
000000
000001
CLK
CLOUT
COUT
Figure 3. 24-bit Cascaded E136 Counter
http://onsemi.com
7
MC10E136, MC100E136
presented by the CLOUT of the LSC. The CIN’s in the
CIN
ACTIVE
LOW
higher order counter will ripple propagate through the chain
to update the count status for the next occurrence of terminal
count on the LSC. This ripple propagation will not affect the
CLIN
CLK
D
Q
6
count frequency as it has 2 −1 or 63 clock pulses to ripple
through without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the setup time of the CLIN input. This limit
will consist of the CLK to CLOUT delay of the E136 plus
the CLIN setup time plus any path length differences
between the CLOUT output and the clock.
Figure 4. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry
output (CLOUT) pulses low one clock pulse before the
counter reaches terminal count. Also note that both CLOUT
and the carry out pin (COUT) of the device pulse low for
only one clock period. The input structure for
look-ahead-carry in (CLIN) and carry in (CIN) is pictured
in Figure 2.
The CLIN input is registered and then ORed with the CIN
input. From the truth table one can see that both the CIN and
the CLIN inputs must be in a LOW state for the E136 to be
enabled to count (either count up or count down). The CLIN
inputs are driven by the CLOUT output of the lowest order
E136 and therefore are only asserted for a single clock
period. Since the CLIN input is registered it must be asserted
one clock period prior to the CIN input.
If the counter previous to a given counter is at terminal
count its COUT output and thus the CIN input of the given
counter will be in the “LOW” state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CLOUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CLOUT signal will be clocked
into the CLIN input of the higher order counters on the
following positive clock transition. Since both CIN and
CLIN are in the LOW state the next clock pulse will cause
the least significant counter to roll over and all higher order
counters, if signaled by their CIN inputs, to count by one.
Programmable Divider
Using external feedback of the COUT pin, the E136 can
be configured as a programmable divider. Figure 3
illustrates the configuration for a 6-bit count down
programmable divider. If for some reason a count up divider
is preferred the COUT signal is simply fed back to S2 rather
than S1. Examination of the truth table for the E136 shows
that when both S1 and S2 are LOW the counter will parallel
load on the next positive transition of the clock. If the S2
input is low and the S1 input is high the counter will be in the
count down mode and will count towards an all zero state
upon successive clock pulses. Knowing this and the
operation of the COUT output it becomes a trivial matter to
build programmable dividers.
For a programmable divider one wants to load a
predesignated number into the counter and count to terminal
count. Upon terminal count the counter should
automatically reload the divide number. With the
architecture shown in Figure 3 when the counter reaches
terminal count the COUT output and thus the S1 input will
go LOW, this combined with the low on S2 will cause the
counter to load the inputs present on D0-D5. Upon loading
the divide value into the counter COUT will go HIGH as the
counter is no longer at terminal count thereby placing the
counter back into the count mode.
Q0 −> Q5
Table 10. Preset Inputs Versus Divide Ratio
Divide
Ratio
Preset Data Inputs
“LO”
S2
S1
D5
D4
D3
D2
D1
D0
CLK
CLOCK
2
3
4
5
•
L
L
L
L
•
L
L
L
L
•
L
L
L
L
•
L
L
L
H
•
L
H
H
L
•
H
L
H
L
•
COUT
COUT
•
•
•
•
•
•
•
H
H
H
•
L
L
L
•
L
L
L
•
L
H
H
•
H
L
L
•
H
L
H
•
36
37
38
•
•
•
•
•
•
•
•
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
D0 −> D5
62
63
64
Figure 5. 6-bit Programmable Divider
During the clock pulse in which the higher order counter
is counting by one the CLIN is clocking in the high signal
http://onsemi.com
8
MC10E136, MC100E136
LOAD
100100
100011
100010
000011
000010
000001
000000
LOAD
• • •
• • •
CLOCK
S1
• • •
COUT
DIVIDE BY 37
Figure 6. Programmable Divider Waveforms
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N−1 must
be loaded into the counter. A single E136 device is capable
of divide ratios of 2 to 64 inclusive, Table 1 outlines the load
values for the various divide ratios. Figure 4 presents the
waveforms resulting from a divide by 37 operation. Note
that the availability of the COUT complementary output
COUT allows the user to choose the polarity of the divide by
output.
For single device programmable counters the E016
counter is probably a better choice than the E136. The E016
has an internal feedback to control the reloading of the
counter, this not only simplifies board design but also will
result in a faster maximum count frequency.
For programmable dividers of larger than 8 bits the
superiority of the E016 diminishes, and in fact for very wide
dividers the E136 will provide the capability of a faster count
frequency. This potential is a result of the cascading features
mentioned previously in this document. Figure 5 shows the
architecture of a 24-bit programmable divider implemented
using E136 counters. Note the need for one external gate to
control the loading of the entire counter chain. An ideal
device for the external gating of this architecture would be
the 4-input OR function in the 8-lead SOIC ECLinPS Lite™
family. However the final decision as to what device to use
for the external gating requires a balancing of performance
needs, cost and available board space. Note that because of
the need for external gating the maximum count frequency
of a given sized programmable divider will be less than that
of a single cascaded counter.
Q0 −> Q5
Q0 −> Q5
Q0 −> Q5
Q0 −> Q5
CLK
CLK
CLK
CLK
S1
S1
S1
S1
CLOCK
LSB
MSB
“LO”
“LO”
“LO”
CIN
COUT
CIN
CLIN
COUT
CIN
CLIN
COUT
CIN
COUT
CLIN
CLOUT
CLOUT
CLOUT
CLIN
CLOUT
D0 −> D5
D0 −> D5
D0 −> D5
D0 −> D5
OUT
Figure 7. 24-bit Programmable Divider Architecture
http://onsemi.com
9
MC10E136, MC100E136
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E136FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E136FNG
PLCC−28
(Pb−Free)
MC10E136FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E136FNR2G
PLCC−28
(Pb−Free)
MC100E136FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E136FNG
PLCC−28
(Pb−Free)
MC100E136FNR2
MC100E136FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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10
MC10E136, MC100E136
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
0.007 (0.180)
T
L−M
N
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T
L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T
L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L−M
L−M
N
M
S
S
N
0.007 (0.180)
T
L−M
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T
L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T
L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
http://onsemi.com
11
MC10E136, MC100E136
ECLinPS and ECLinPS Lite are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
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For additional information, please contact your local
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MC10E136/D
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