MC100E136 [ONSEMI]
6-BIT UNIVERSAL UP/DOWN COUNTER; 6位通用加/减计数器
| 型号： | MC100E136 |
| 厂家： | 
ONSEMI |
| 描述： | 6-BIT UNIVERSAL UP/DOWN COUNTER |
| 文件： | 总9页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable
universal counter. The device generates a look-ahead-carry output and
accepts a look-ahead-carry input. These two features allow for the
cacading of multiple E136’s for wider bit width counters that operate at
very nearly the same frequency as the stand alone counter.
• 550 MHz Count Frequency
6-BIT UNIVERSAL
• Fully Synchronous Up and Down Counting
• Internal 75 kΩ Input Pulldown Resistors
• Look-Ahead-Carry Input and Output
• Asynchronous Master Reset
UP/DOWN COUNTER
• Extended 100E V
EE
Range of –4.2 V to –5.46 V
The CLOUT output will pulse LOW for one clock cycle one count
before the E136 reaches terminal count. The COUT output will pulse
LOW for one clock cycle when the counter reaches terminal count. For
more information on utilizing the look-ahead-carry features of the device
please refer to the applications section of this data sheet. The differential
COUT output facilitates the E136’s use in programmable divider and
self-stopping counter applications.
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Unlike the H136 and other similar universal counter designs the E136
carry out and look-ahead-carry out signals are registered on chip. This
design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this
architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out
outputs and the look-ahead-carry in input when utilizing the master reset.
When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous
signal which when asserted will force the Q outputs LOW.
The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is
recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can
reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system.
D3
25
D4
24
D5
23
V
Q5
21
Q4
20
V
CCO
22
CCO
PIN NAMES
Pin
Function
Preset Data Inputs
Data Inputs
Mode Control Pins
Master Reset
Clock Input
Carry-Out Output (Active LOW)
Look-Ahead-Carry Out (Active LOW)
Carry-In Input (Active LOW)
Look-Ahead-Carry In Input (Active LOW)
19
18
D2
S2
S1
26
27
Q3
Q2
V
D
– D
5
0
Q
– Q
0
5
17
16
15
S1, S2
MR
CLK
COUT, COUT
CLOUT
CIN
28
1
CC
Pinout: 28-lead PLCC
(Top View)
V
V
CCO
EE
CLIN
CLK
2
3
4
14
13
12
COUT
COUT
CLOUT
FUNCTION TABLE (Expanded truth table on page 2–4)
CIN
S1
S2 CIN MR CLK
Function
CLIN
L
L
L
H
H
H
X
L
H
H
L
L
H
X
X
L
H
L
H
X
X
L
L
L
L
L
L
H
Z
Z
Z
Z
Z
Z
X
Preset Parallel Data
Increment (Count Up)
Hold Count
Decrement (Count Down)
Hold Count
5
6
7
8
9
10
11
MR
D1
D0
V
Q0
Q1
V
CCO
CCO
* All V
CC
and V
pins are tied together on the die.
Hold Count
Reset (Qn = LOW)
CCO
5/95
REV 2
Motorola, Inc. 1996
MC10E136 MC100E136
E136 Universal Up/Down Counter Logic Diagram
MOTOROLA
2–2
MC10E136 MC100E136
DC CHARACTERISTICS
(V
EE
= V (min) to V (max); V
EE EE CC
= V
CCO
= GND)
0°C
Typ
—
25°C
85°C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Typ
Max
Unit
µA
Condition
Input HIGH Current
I
IH
—
150
—
—
150
—
—
150
Power Supply Current
10E
100E
I
mA
EE
—
—
125
125
150
150
—
—
125
125
150
150
—
—
125
140
150
170
AC CHARACTERISTICS
(V
EE
= V (min) to V (max); V
EE EE CC
= V
CCO
= GND)
0°C
Typ
650
25°C
Typ
650
85°C
Typ
650
Characteristic
Symbol
Min
Max
Min
Max
Min
Max
Unit
MHz
ps
Condition
Maximum Count Frequency
f
550
—
550
—
550
—
COUNT
Propagation Delay to Output
CLK to Q
MR to Q
CLK to COUT
CLK to CLOUT
t
t
PLH
PHL
850
850
800
825
1150 1450
1150 1450
1150 1300
1150 1400
850
850
800
825
1150 1450
1150 1450
1150 1300
1150 1400
850
850
800
825
1150 1450
1150 1450
1150 1300
1150 1400
Setup Time
S1, S2
D
CLIN
CIN
t
ps
ps
s
1000
800
150
800
650
400
0
—
—
—
—
1000
800
150
800
650
400
0
—
—
—
—
1000
800
150
800
650
400
0
—
—
—
—
400
400
400
Hold Time
S1, S2
D
CLIN
CIN
t
h
150
150
300
150
–200
–250
0
—
—
—
—
150
150
300
150
–200
–250
0
—
—
—
—
150
150
300
150
–200
–250
0
—
—
—
—
–250
–250
–250
Reset Recovery Time
t
1000
700
400
—
1000
700
400
—
1000
700
400
—
ps
ps
RR
Minimum Pulse Width
CLK, MR
t
PW
700
—
700
—
700
—
Rise/Fall Times
COUT
Other
t
t
ps
r
f
275
300
—
—
600
700
275
300
—
—
600
700
275
300
—
—
600
700
20% - 80%
2–3
MOTOROLA
MC10E136 MC100E136
EXPANDED TRUTH TABLE
Function
Preset
S1
S2
MR
CIN CLIN CLK D5 D4 D3 D2 D1 D0 Q5 Q4 Q3 Q2 Q1 Q0 COUT CLOUT
L
L
L
X
X
Z
L
L
L
L
H
H
L
L
L
L
H
H
H
H
Down
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Preset
Up
L
L
L
X
X
Z
H
H
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
Hold
L
L
Hold
Preset
Up
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
L
H
H
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hold
Up
Hold
L
H
H
H
H
Hold
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
Z = Low to High Transition
MOTOROLA
2–4
MC10E136 MC100E136
APPLICATIONS INFORMATION
Overview
The MC10E/100E136 is a 6-bit synchronous, presettable,
result of the terminal count signal of the lower order counters
having to ripple through the entire counter chain. As a result
past counters of this type were not widely used in large bit
counter applications.
cascadable universal counter. Using the S1 and S2 control
pins the user can select between preset, count up, count
down and hold count. The master reset pin will reset the
internal counter, and set the COUT, CLOUT, and CLIN
flip-flops. Unlike previous 136 type counters the carry out
outputs will go to a high state during the preset operation. In
addition since the carry out outputs are registered they will
not go low if terminal count is loaded into the register. The
look-ahead-carry out output functions similarly.
An alternative counter architecture similar to the E016
binary counter was implemented to alleviate the need to
ripple propagate the terminal count signal. Unfortunately
these types of counters require external gating for cascading
designs of more than two devices. In addition to requiring
additional components, these external gates limit the
cascaded count frequency to a value less than the free
running count frequency of a single counter. Although there is
a performance impact with this type of architecture it is minor
compared to the impact of the ripple propagate designs. As a
result the E016 type counters have been used extensively in
applications requiring very high speed, wide bit width
synchronous counters.
Note from the schematic the use of the master information
from the least significant bits for control of the two carry out
functions. This architecture not only reduces the carry out
delay, but is essential to incorporate the registered carry out
functions. In addition to being faster, because these functions
are registered the resulting carry out signals are stable and
glitch free.
Motorola has incorporated several improvements to past
universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader
in its class. With the addition of look-ahead-carry features on
the terminal count signal, very large counter chains can be
designed which function at very nearly the same clock
frequency as a single free running device. More importantly
these counter chains require no external gating. Figure 1
below illustrates the interconnect scheme for using the
look-ahead-carry features of the E136 counter.
Cascading Multiple E136 Devices
Many applications require counters significantly larger
than the 6 bits available with the E136. For these applications
several E136 devices can be cascaded to increase the bit
width of the counter to meet the needs of the application.
In the past cascading several 136 type universal counters
necessarily impacted the maximum count frequency of the
resulting counter chain. This performance impact was the
Q0 –> Q5
Q0 –> Q5
Q0 –> Q5
Q0 –> Q5
CLOCK
CLK
CLK
CLK
CLK
LSB
MSB
“LO”
“LO”
COUT
“LO”
COUT
CLOUT
COUT
CLOUT
COUT
CIN
CIN
CLIN
CIN
CLIN
CIN
CLIN
CLOUT
CLIN
CLOUT
D0 –> D5
111101
D0 –> D5
D0 –> D5
D0 –> D5
111110
111111
000000
000001
CLK
CLOUT
COUT
Figure 1. 24-bit Cascaded E136 Counter
2–5
MOTOROLA
MC10E136 MC100E136
During the clock pulse in which the higher order counter is
counting by one the CLIN is clocking in the high signal
presented by the CLOUT of the LSC. The CIN’s in the higher
order counter will ripple propagate through the chain to
update the count status for the next occurrence of terminal
count on the LSC. This ripple propagation will not affect the
CIN
ACTIVE
LOW
CLIN
CLK
D
Q
6
count frequency as it has 2 –1 or 63 clock pulses to ripple
through without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the setup time of the CLIN input. This limit will
consist of the CLK to CLOUT delay of the E136 plus the CLIN
setup time plus any path length differences between the
CLOUT output and the clock.
Figure 2. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry output
(CLOUT) pulses low one clock pulse before the counter
reaches terminal count. Also note that both CLOUT and the
carry out pin (COUT) of the device pulse low for only one
clock period. The input structure for look-ahead-carry in
(CLIN) and carry in (CIN) is pictured in Figure 2.
Programmable Divider
Using external feedback of the COUT pin, the E136 can be
configured as a programmable divider. Figure 3 illustrates the
configuration for a 6-bit count down programmable divider. If
for some reason a count up divider is preferred the COUT
signal is simply fed back to S2 rather than S1. Examination of
the truth table for the E136 shows that when both S1 and S2
are LOW the counter will parallel load on the next positive
transition of the clock. If the S2 input is low and the S1 input is
high the counter will be in the count down mode and will
count towards an all zero state upon successive clock
pulses. Knowing this and the operation of the COUT output it
becomes a trivial matter to build programmable dividers.
The CLIN input is registered and then ORed with the CIN
input. From the truth table one can see that both the CIN and
the CLIN inputs must be in a LOW state for the E136 to be
enabled to count (either count up or count down). The CLIN
inputs are driven by the CLOUT output of the lowest order
E136 and therefore are only asserted for a single clock
period. Since the CLIN input is registered it must be asserted
one clock period prior to the CIN input.
If the counter previous to a given counter is at terminal
count its COUT output and thus the CIN input of the given
counter will be in the “LOW” state. This signals the given
counter that it will need to count one upon the next terminal
count of the least significant counter (LSC). The CLOUT
output of the LSC will pulse low one clock period before it
reaches terminal count. This CLOUT signal will be clocked
into the CLIN input of the higher order counters on the
following positive clock transition. Since both CIN and CLIN
are in the LOW state the next clock pulse will cause the least
significant counter to roll over and all higher order counters, if
signaled by their CIN inputs, to count by one.
For a programmable divider one wants to load a
predesignated number into the counter and count to terminal
count. Upon terminal count the counter should automatically
reload the divide number. With the architecture shown in
Figure 3 when the counter reaches terminal count the COUT
output and thus the S1 input will go LOW, this combined with
the low on S2 will cause the counter to load the inputs
present on D0-D5. Upon loading the divide value into the
counter COUT will go HIGH as the counter is no longer at
terminal count thereby placing the counter back into the
count mode.
Q0 –> Q5
Table 1. Preset Inputs Versus Divide Ratio
“LO”
S0
S1
Divide
Ratio
Preset Data Inputs
CLK
D5
D4
D3
D2
D1
D0
CLOCK
2
3
4
5
•
L
L
L
L
•
L
L
L
L
•
L
L
L
L
•
L
L
L
H
•
L
H
H
L
•
H
L
H
L
•
COUT
COUT
•
•
•
•
•
•
•
36
37
38
•
H
H
H
•
L
L
L
•
L
L
L
•
L
H
H
•
H
L
L
•
H
L
H
•
D0 –> D5
•
•
•
•
•
•
•
62
63
64
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
Figure 3. 6-bit Programmable Divider
MOTOROLA
2–6
MC10E136 MC100E136
LOAD
100011
100010
000011
000010
000001
000000
100100
LOAD
•••
•••
CLOCK
S1
•••
COUT
DIVIDE BY 37
Figure 4. Programmable Divider Waveforms
The exercise of building a programmable divider then
becomes simply determining what value to load into the
counter to accomplish the desired division. Since the load
operation requires a clock pulse, to divide by N, N–1 must be
loaded into the counter. A single E136 device is capable of
divide ratios of 2 to 64 inclusive, Table 1 outlines the load
values for the various divide ratios. Figure 4 presents the
waveforms resulting from a divide by 37 operation. Note that
the availability of the COUT complimentary output COUT
allows the user to choose the polarity of the divide by output.
For single device programmable counters the E016
counter is probably a better choice than the E136. The E016
has an internal feedback to control the reloading of the
counter, this not only simplifies board design but also will
result in a faster maximum count frequency.
superiority of the E016 diminishes, and in fact for very wide
dividers the E136 will provide the capability of a faster count
frequency. This potential is a result of the cascading features
mentioned previously in this document. Figure 5 shows the
architecture of a 24-bit programmable divider implemented
using E136 counters. Note the need for one external gate to
control the loading of the entire counter chain. An ideal
device for the external gating of this architecture would be the
4-input OR function in the 8-lead SOIC ECLinPS Lite family.
However the final decision as to what device to use for the
external gating requires a balancing of performance needs,
cost and available board space. Note that because of the
need for external gating the maximum count frequency of a
given sized programmable divider will be less than that of a
single cascaded counter.
For programmable dividers of larger than 8 bits the
Q0 –> Q5
Q0 –> Q5
Q0 –> Q5
Q0 –> Q5
CLK
CLK
CLK
CLK
S1
S1
S1
S1
CLOCK
LSB
MSB
“LO”
“LO”
“LO”
CIN
COUT
CIN
CLIN
COUT
CIN
CLIN
COUT
CIN
COUT
CLIN
CLOUT
CLOUT
CLOUT
CLIN
CLOUT
D0 –> D5
D0 –> D5
D0 –> D5
D0 –> D5
Figure 5. 24-bit Programmable Divider Architecture
2–7
MOTOROLA
MC10E136 MC100E136
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
M
S
S
0.007 (0.180)
T
L –M
N
B
Z
Y BRK
D
-N-
M
S
S
0.007 (0.180)
T
L –M
N
U
-L-
-M-
D
W
X
G1
S
S
S
0.010 (0.250)
0.007 (0.180)
T
L –M
L –M
N
V
28
1
VIEW D-D
M
M
S
S
S
0.007 (0.180)
0.007 (0.180)
T
T
L –M
L –M
N
A
R
H
M
S
S
T
N
Z
S
N
K1
C
E
0.004 (0.100)
SEATING
PLANE
G
K
-T-
VIEW S
J
M
S
S
0.007 (0.180)
T
L –M
N
F
G1
VIEW S
S
S
S
0.010 (0.250)
T
L –M
N
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
INCHES
MAX
MILLIMETERS
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.495
0.495
0.180
0.110
0.019
0.485
0.165
0.090
0.013
2.29
2.79
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
0.33
0.48
0.050 BSC
1.27 BSC
0.026
0.032
—
—
0.456
0.456
0.048
0.048
0.056
0.020
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
—
0.81
—
—
11.58
11.58
1.21
1.21
1.42
0.50
0.020
0.025
0.450
0.450
0.042
0.042
0.042
—
2
°
10°
2°
10°
0.410
0.040
0.430
—
10.42
1.02
10.92
—
MOTOROLA
2–8
MC10E136 MC100E136
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MC10E136/D
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