MC14572UBDR2G [ONSEMI]
Hex Gate; 六角门
| 型号： | MC14572UBDR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hex Gate |
| 文件： | 总6页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
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Features
MARKING
DIAGRAMS
• Diode Protection on All Inputs
• Single Supply Operation
16
PDIP−16
P SUFFIX
CASE 648
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14572UBCP
AWLYYWWG
• NOR Input Pin Adjacent to V Pin to Simplify Use As An Inverter
SS
1
• NAND Input Pin Adjacent to V Pin to Simplify Use As An
DD
1
Inverter
16
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application
SOIC−16
D SUFFIX
CASE 751B
14572UBG
AWLYWW
• NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
1
1
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• Pb−Free Packages are Available*
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14572UB
ALYWG
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
1
Parameter
Symbol
Value
Unit
V
DC Supply Voltage Range
V
DD
−0.5 to +18.0
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
+ 0.5
V
DD
Input or Output Current (DC or Transient)
per Pin
I , I
in out
10
mA
G
= Pb−Free Package
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
500
mW
°C
D
ORDERING INFORMATION
T
A
−55 to +125
−65 to +150
260
†
Device
Package
Shipping
Storage Temperature Range
T
stg
°C
MC14572UBCP
PDIP−16
25 Units / Rail
25 Units / Rail
Lead Temperature (8−Second Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
MC14572UBCPG
PDIP−16
(Pb−Free)
MC14572UBD
SOIC−16
48 Units / Rail
48 Units / Rail
MC14572UBDG
SOIC−16
(Pb−Free)
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14572UBDR2
SOIC−16 2500/Tape & Reel
MC14572UBDR2G SOIC−16 2500/Tape & Reel
(Pb−Free)
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
MC14572UBF
SOEIAJ−16
50 Units / Rail
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14572UB/D
MC14572UB
LOGIC DIAGRAM
PIN ASSIGNMENT
OUT
1
2
3
4
5
6
7
8
16
V
DD
A
2
4
ꢀ1
IN
OUT
IN
15 IN 2
A
B
F
14 IN 1
F
13 OUT
B
F
E
D
ꢀ3
ꢀ5
ꢀ9
OUT
IN 1
IN 2
12 IN
E
C
11 OUT
10 IN
C
6
7
C
D
V
SS
9
OUT
10
12
11
13
14
15
V
= PIN 16
= PIN 8
DD
V
SS
CIRCUIT SCHEMATIC
V
DD
V
DD
V
DD
7
6
2
1
13
14
15
5
V
SS
V
SS
V
SS
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2
MC14572UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
Typ
125_C
V
Vdc
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Characteristic
Output Voltage
Symbol
Unit
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
in
= 0 or V
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance (V = 0)
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
pF
in
C
in
in
Quiescent Current (Per Package)
I
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
T
5.0
10
15
I = (1.89 mA/kHz) f + I
mAdc
T
DD
DD
DD
I = (3.80 mA/kHz) f + I
T
I = (5.68 mA/kHz) f + I
T
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: I (C ) = I (50 pF) + (C – 50) Vfk where: I is in mA (per package), C in pF,
T
L
T
L
T
L
V = (V – V ) in volts, f in kHz is input frequency, and k = 0.006.
DD
SS
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3
MC14572UB
SWITCHING CHARACTERISTICS (Type 5) (C = 50 pF, T = 25_C)
L
A
Typ
(Note 6)
Characteristic
Symbol
V
DD
Min
Max
Unit
Output Rise Time
t
ns
TLH
t
t
t
= (3.0 ns/pF) C + 30 ns
= (1.5 ns/pF) C + 15 ns
= (1.1 ns/pF) C + 10 ns
5.0
10
15
−
−
−
180
90
65
360
180
130
TLH
TLH
TLH
L
L
L
Output Fall Time
t
ns
ns
THL
t
t
t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
THL
THL
THL
L
L
L
Propagation Delay Time
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 5 ns
t
5.0
10
15
−
−
−
90
50
40
180
100
80
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 17 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 15 ns
L
PLH PHL
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
V
DD
INPUT
7
16
V
16
V
INPUT
2
PULSE
PULSE
GENERATOR
6
OUTPUT
OUTPUT
GENERATOR
1
5
C
L
8
8
C
L
SS
SS
V
DD
20 ns
20 ns
V
16
DD
90%
50%
10%
90%
50%
10%
INPUT
14
INPUT
15
V
SS
OUTPUT
PULSE
GENERATOR
t
t
PHL
PLH
13
V
V
8
V
SS
C
L
OH
90%
50%
10%
90%
50%
10%
OUTPUT
OL
t
f
t
r
Figure 1. Switching Time Test Circuits and Waveforms
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4
MC14572UB
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T
A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
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5
MC14572UB
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢁꢀ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
E
16
9
ꢁꢀ2. CONTROLLING DIMENSION: MILLIMETER.
ꢁꢀ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
Q
1
H
E
M
_
E
ꢁꢀ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
ꢁꢀ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.20 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50
5.45 0.201
0.390
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase
or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative
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MC14572UB/D
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